Group : pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg
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Group : pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
WakeupAonTimer_intr_cg 100.00 1 100 1 64 64
WakeupDbgCable_intr_cg 100.00 1 100 1 64 64
WakeupPin_intr_cg 100.00 1 100 1 64 64
WakeupSensorCtrl_intr_cg 100.00 1 100 1 64 64
WakeupSysrst_intr_cg 100.00 1 100 1 64 64
WakeupUsb_intr_cg 100.00 1 100 1 64 64




Group Instance : WakeupAonTimer_intr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupAonTimer_intr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupAonTimer_intr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
interrupt_cp 2 0 2 100.00 100 1 1 2
status_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupAonTimer_intr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
interrupt_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupDbgCable_intr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupDbgCable_intr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupDbgCable_intr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
interrupt_cp 2 0 2 100.00 100 1 1 2
status_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupDbgCable_intr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
interrupt_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupPin_intr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupPin_intr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupPin_intr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
interrupt_cp 2 0 2 100.00 100 1 1 2
status_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupPin_intr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
interrupt_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupSensorCtrl_intr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupSensorCtrl_intr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupSensorCtrl_intr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
interrupt_cp 2 0 2 100.00 100 1 1 2
status_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupSensorCtrl_intr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
interrupt_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupSysrst_intr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupSysrst_intr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupSysrst_intr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
interrupt_cp 2 0 2 100.00 100 1 1 2
status_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupSysrst_intr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
interrupt_cross 8 0 8 100.00 100 1 1 0



Group Instance : WakeupUsb_intr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance WakeupUsb_intr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 8 0 8 100.00


Variables for Group Instance WakeupUsb_intr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
interrupt_cp 2 0 2 100.00 100 1 1 2
status_cp 2 0 2 100.00 100 1 1 2
wakeup_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance WakeupUsb_intr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
interrupt_cross 8 0 8 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36454 1 T1 5 T2 3 T3 3
auto[1] 9378 1 T7 6 T8 10 T11 28



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35190 1 T1 5 T2 3 T3 3
auto[1] 10642 1 T7 6 T8 12 T11 34



Summary for Variable status_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for status_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25771 1 T1 5 T2 3 T3 3
auto[1] 20061 1 T6 2 T7 6 T8 12



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19896 1 T1 5 T2 3 T3 3
auto[1] 25936 1 T7 15 T8 19 T11 55



Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for interrupt_cross

Bins
enable_cpstatus_cpwakeup_cpinterrupt_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 11982 1 T1 5 T2 3 T3 3
auto[0] auto[0] auto[1] auto[0] 9239 1 T7 6 T8 3 T11 12
auto[0] auto[1] auto[0] auto[0] 6036 1 T6 2 T9 3 T12 1
auto[0] auto[1] auto[1] auto[0] 2463 1 T13 8 T14 3 T15 36
auto[1] auto[0] auto[0] auto[0] 958 1 T11 4 T36 4 T37 2
auto[1] auto[0] auto[1] auto[0] 3592 1 T7 3 T8 4 T11 9
auto[1] auto[1] auto[0] auto[0] 920 1 T11 8 T36 6 T37 4
auto[1] auto[1] auto[1] auto[1] 3908 1 T7 3 T8 6 T11 7


User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
no_wakeup 0 Excluded
disable_pin 0 Excluded
no_status_pin 0 Excluded
missing_int 0 Excluded


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36518 1 T1 5 T2 3 T3 3
auto[1] 9314 1 T7 4 T8 6 T11 19



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35190 1 T1 5 T2 3 T3 3
auto[1] 10642 1 T7 6 T8 12 T11 34



Summary for Variable status_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for status_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25771 1 T1 5 T2 3 T3 3
auto[1] 20061 1 T6 2 T7 6 T8 12



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19896 1 T1 5 T2 3 T3 3
auto[1] 25936 1 T7 15 T8 19 T11 55



Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for interrupt_cross

Bins
enable_cpstatus_cpwakeup_cpinterrupt_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 11974 1 T1 5 T2 3 T3 3
auto[0] auto[0] auto[1] auto[0] 9186 1 T7 7 T8 6 T11 18
auto[0] auto[1] auto[0] auto[0] 6028 1 T6 2 T9 3 T12 1
auto[0] auto[1] auto[1] auto[0] 2463 1 T13 8 T14 3 T15 36
auto[1] auto[0] auto[0] auto[0] 966 1 T11 2 T36 4 T37 4
auto[1] auto[0] auto[1] auto[0] 3645 1 T7 2 T8 1 T11 3
auto[1] auto[1] auto[0] auto[0] 928 1 T11 2 T40 8 T149 2
auto[1] auto[1] auto[1] auto[1] 3775 1 T7 2 T8 5 T11 12


User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
no_wakeup 0 Excluded
disable_pin 0 Excluded
no_status_pin 0 Excluded
missing_int 0 Excluded


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36375 1 T1 5 T2 3 T3 3
auto[1] 9457 1 T7 4 T8 11 T11 36



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35190 1 T1 5 T2 3 T3 3
auto[1] 10642 1 T7 6 T8 12 T11 34



Summary for Variable status_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for status_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25771 1 T1 5 T2 3 T3 3
auto[1] 20061 1 T6 2 T7 6 T8 12



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19896 1 T1 5 T2 3 T3 3
auto[1] 25936 1 T7 15 T8 19 T11 55



Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for interrupt_cross

Bins
enable_cpstatus_cpwakeup_cpinterrupt_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 12004 1 T1 5 T2 3 T3 3
auto[0] auto[0] auto[1] auto[0] 9103 1 T7 7 T8 3 T11 13
auto[0] auto[1] auto[0] auto[0] 6132 1 T6 2 T9 3 T12 1
auto[0] auto[1] auto[1] auto[0] 2463 1 T13 8 T14 3 T15 36
auto[1] auto[0] auto[0] auto[0] 936 1 T11 2 T36 2 T37 2
auto[1] auto[0] auto[1] auto[0] 3728 1 T7 2 T8 4 T11 8
auto[1] auto[1] auto[0] auto[0] 824 1 T11 10 T36 4 T37 2
auto[1] auto[1] auto[1] auto[1] 3969 1 T7 2 T8 7 T11 16


User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
no_wakeup 0 Excluded
disable_pin 0 Excluded
no_status_pin 0 Excluded
missing_int 0 Excluded


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36523 1 T1 5 T2 3 T3 3
auto[1] 9309 1 T7 4 T8 13 T11 26



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35190 1 T1 5 T2 3 T3 3
auto[1] 10642 1 T7 6 T8 12 T11 34



Summary for Variable status_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for status_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25771 1 T1 5 T2 3 T3 3
auto[1] 20061 1 T6 2 T7 6 T8 12



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19896 1 T1 5 T2 3 T3 3
auto[1] 25936 1 T7 15 T8 19 T11 55



Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for interrupt_cross

Bins
enable_cpstatus_cpwakeup_cpinterrupt_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 12049 1 T1 5 T2 3 T3 3
auto[0] auto[0] auto[1] auto[0] 9090 1 T7 7 T8 4 T11 13
auto[0] auto[1] auto[0] auto[0] 6110 1 T6 2 T9 3 T12 1
auto[0] auto[1] auto[1] auto[0] 2463 1 T13 8 T14 3 T15 36
auto[1] auto[0] auto[0] auto[0] 891 1 T11 2 T36 4 T40 8
auto[1] auto[0] auto[1] auto[0] 3741 1 T7 2 T8 3 T11 8
auto[1] auto[1] auto[0] auto[0] 846 1 T11 6 T37 4 T38 2
auto[1] auto[1] auto[1] auto[1] 3831 1 T7 2 T8 10 T11 10


User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
no_wakeup 0 Excluded
disable_pin 0 Excluded
no_status_pin 0 Excluded
missing_int 0 Excluded


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36383 1 T1 5 T2 3 T3 3
auto[1] 9449 1 T7 1 T8 7 T11 28



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35190 1 T1 5 T2 3 T3 3
auto[1] 10642 1 T7 6 T8 12 T11 34



Summary for Variable status_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for status_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25771 1 T1 5 T2 3 T3 3
auto[1] 20061 1 T6 2 T7 6 T8 12



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19896 1 T1 5 T2 3 T3 3
auto[1] 25936 1 T7 15 T8 19 T11 55



Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for interrupt_cross

Bins
enable_cpstatus_cpwakeup_cpinterrupt_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 11981 1 T1 5 T2 3 T3 3
auto[0] auto[0] auto[1] auto[0] 9088 1 T7 8 T8 5 T11 14
auto[0] auto[1] auto[0] auto[0] 6128 1 T6 2 T9 3 T12 1
auto[0] auto[1] auto[1] auto[0] 2463 1 T13 8 T14 3 T15 36
auto[1] auto[0] auto[0] auto[0] 959 1 T36 8 T40 4 T149 4
auto[1] auto[0] auto[1] auto[0] 3743 1 T7 1 T8 2 T11 7
auto[1] auto[1] auto[0] auto[0] 828 1 T11 10 T36 2 T40 2
auto[1] auto[1] auto[1] auto[1] 3919 1 T8 5 T11 11 T36 14


User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
no_wakeup 0 Excluded
disable_pin 0 Excluded
no_status_pin 0 Excluded
missing_int 0 Excluded


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36522 1 T1 5 T2 3 T3 3
auto[1] 9310 1 T7 3 T8 11 T11 27



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35190 1 T1 5 T2 3 T3 3
auto[1] 10642 1 T7 6 T8 12 T11 34



Summary for Variable status_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for status_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25771 1 T1 5 T2 3 T3 3
auto[1] 20061 1 T6 2 T7 6 T8 12



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19896 1 T1 5 T2 3 T3 3
auto[1] 25936 1 T7 15 T8 19 T11 55



Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for interrupt_cross

Bins
enable_cpstatus_cpwakeup_cpinterrupt_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 12058 1 T1 5 T2 3 T3 3
auto[0] auto[0] auto[1] auto[0] 9185 1 T7 6 T8 4 T11 14
auto[0] auto[1] auto[0] auto[0] 6078 1 T6 2 T9 3 T12 1
auto[0] auto[1] auto[1] auto[0] 2463 1 T13 8 T14 3 T15 36
auto[1] auto[0] auto[0] auto[0] 882 1 T11 4 T36 8 T37 2
auto[1] auto[0] auto[1] auto[0] 3646 1 T7 3 T8 3 T11 7
auto[1] auto[1] auto[0] auto[0] 878 1 T11 8 T36 2 T37 2
auto[1] auto[1] auto[1] auto[1] 3904 1 T8 8 T11 8 T36 5


User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
no_wakeup 0 Excluded
disable_pin 0 Excluded
no_status_pin 0 Excluded
missing_int 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%