Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	479118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241907

1

T1

13

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	466459	1			T1	13		T2	1		T3	1
values[0x0]	127073	1			T1	11		T4	8		T6	10
values[0x1]	127493	1			T1	5		T4	8		T6	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	379357	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

341668

1

T1

13

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2431	1			T7	1		T11	2		T36	2
valid_sources[0x01]	2319	1			T7	3		T9	2		T11	3
valid_sources[0x02]	2308	1			T7	1		T11	2		T36	7
valid_sources[0x03]	2298	1			T12	1		T11	1		T35	1
valid_sources[0x04]	2462	1			T4	1		T7	1		T11	6
valid_sources[0x05]	2254	1			T6	1		T7	2		T9	2
valid_sources[0x06]	2072	1			T6	1		T11	12		T36	3
valid_sources[0x07]	2254	1			T7	3		T12	8		T11	4
valid_sources[0x08]	2564	1			T4	1		T6	1		T7	2
valid_sources[0x09]	2216	1			T7	2		T11	9		T36	6
valid_sources[0x0a]	2225	1			T7	2		T9	1		T11	4
valid_sources[0x0b]	4394	1			T7	1		T11	9		T35	7
valid_sources[0x0c]	2339	1			T11	7		T36	3		T41	1
valid_sources[0x0d]	11445	1			T7	4		T11	2		T35	4
valid_sources[0x0e]	2721	1			T4	1		T9	1		T11	4
valid_sources[0x0f]	2547	1			T7	1		T11	5		T35	1
valid_sources[0x10]	2056	1			T7	4		T11	2		T36	4
valid_sources[0x11]	2115	1			T4	1		T6	1		T9	1
valid_sources[0x12]	2212	1			T7	1		T11	5		T36	3
valid_sources[0x13]	2678	1			T7	2		T9	2		T11	4
valid_sources[0x14]	2289	1			T7	3		T11	4		T36	2
valid_sources[0x15]	2346	1			T1	2		T6	2		T7	6
valid_sources[0x16]	2289	1			T7	1		T11	6		T38	2
valid_sources[0x17]	2130	1			T7	1		T9	2		T11	5
valid_sources[0x18]	2369	1			T7	2		T11	5		T35	1
valid_sources[0x19]	2872	1			T11	6		T35	6		T36	2
valid_sources[0x1a]	2245	1			T7	2		T11	5		T35	1
valid_sources[0x1b]	2264	1			T11	3		T36	8		T56	1
valid_sources[0x1c]	2151	1			T7	3		T11	4		T35	5
valid_sources[0x1d]	2156	1			T7	4		T11	2		T35	2
valid_sources[0x1e]	2126	1			T7	2		T11	2		T35	1
valid_sources[0x1f]	2300	1			T9	2		T11	5		T36	3
valid_sources[0x20]	3277	1			T7	4		T11	3		T36	5
valid_sources[0x21]	2313	1			T6	3		T11	4		T35	4
valid_sources[0x22]	2814	1			T7	1		T9	1		T12	4
valid_sources[0x23]	2576	1			T7	4		T9	1		T11	3
valid_sources[0x24]	2349	1			T3	1		T6	6		T7	1
valid_sources[0x25]	2252	1			T4	1		T7	4		T11	4
valid_sources[0x26]	3026	1			T7	4		T8	359		T11	7
valid_sources[0x27]	2009	1			T6	1		T7	1		T11	2
valid_sources[0x28]	2394	1			T7	6		T11	2		T36	5
valid_sources[0x29]	2184	1			T7	3		T11	2		T35	1
valid_sources[0x2a]	2311	1			T11	3		T36	6		T38	1
valid_sources[0x2b]	2199	1			T7	1		T9	1		T11	3
valid_sources[0x2c]	2359	1			T7	3		T11	2		T35	3
valid_sources[0x2d]	2143	1			T1	1		T7	2		T11	7
valid_sources[0x2e]	2242	1			T1	3		T6	2		T7	2
valid_sources[0x2f]	2124	1			T7	1		T11	5		T35	1
valid_sources[0x30]	2105	1			T7	1		T11	3		T36	2
valid_sources[0x31]	2148	1			T7	3		T11	5		T36	3
valid_sources[0x32]	2470	1			T7	3		T9	1		T42	5
valid_sources[0x33]	2244	1			T6	2		T7	4		T11	3
valid_sources[0x34]	2543	1			T7	1		T11	1		T35	1
valid_sources[0x35]	2400	1			T7	1		T11	3		T36	2
valid_sources[0x36]	2294	1			T7	3		T11	7		T36	2
valid_sources[0x37]	2299	1			T7	4		T12	14		T11	4
valid_sources[0x38]	2219	1			T11	6		T36	7		T87	4
valid_sources[0x39]	2160	1			T7	2		T11	3		T35	3
valid_sources[0x3a]	2051	1			T6	1		T7	1		T11	4
valid_sources[0x3b]	2686	1			T4	3		T7	1		T11	4
valid_sources[0x3c]	2048	1			T4	1		T11	6		T36	2
valid_sources[0x3d]	2184	1			T7	4		T11	2		T35	1
valid_sources[0x3e]	4365	1			T7	1		T11	7		T36	3
valid_sources[0x3f]	3344	1			T11	1		T36	4		T88	6
valid_sources[0x40]	2033	1			T6	5		T7	1		T11	3
valid_sources[0x41]	2439	1			T7	2		T9	1		T12	7
valid_sources[0x42]	2196	1			T1	3		T7	2		T11	5
valid_sources[0x43]	2359	1			T7	4		T11	3		T36	4
valid_sources[0x44]	2215	1			T7	5		T11	3		T36	4
valid_sources[0x45]	3681	1			T7	5		T11	4		T35	4
valid_sources[0x46]	2360	1			T7	6		T9	4		T11	3
valid_sources[0x47]	2395	1			T6	1		T11	5		T35	1
valid_sources[0x48]	2600	1			T7	3		T11	4		T35	1
valid_sources[0x49]	3459	1			T6	2		T7	1		T11	8
valid_sources[0x4a]	2446	1			T7	4		T9	1		T11	3
valid_sources[0x4b]	2281	1			T7	2		T11	6		T36	3
valid_sources[0x4c]	2657	1			T7	2		T12	2		T11	3
valid_sources[0x4d]	2280	1			T7	3		T11	5		T36	6
valid_sources[0x4e]	2353	1			T7	2		T9	2		T11	5
valid_sources[0x4f]	2506	1			T5	1		T7	2		T11	4
valid_sources[0x50]	10487	1			T7	1		T9	1		T11	3
valid_sources[0x51]	2521	1			T7	2		T11	1		T35	6
valid_sources[0x52]	2305	1			T11	2		T35	1		T36	3
valid_sources[0x53]	3925	1			T7	2		T36	4		T38	2
valid_sources[0x54]	2254	1			T7	5		T11	3		T36	3
valid_sources[0x55]	2017	1			T6	2		T7	9		T11	3
valid_sources[0x56]	4555	1			T7	1		T11	3		T35	3
valid_sources[0x57]	2236	1			T4	1		T9	1		T12	24
valid_sources[0x58]	5264	1			T6	1		T7	2		T9	1
valid_sources[0x59]	2153	1			T11	3		T35	5		T36	4
valid_sources[0x5a]	4312	1			T6	3		T7	3		T11	2
valid_sources[0x5b]	2396	1			T7	3		T11	3		T35	5
valid_sources[0x5c]	2764	1			T4	2		T11	5		T36	5
valid_sources[0x5d]	2180	1			T7	2		T9	1		T11	4
valid_sources[0x5e]	2336	1			T7	2		T11	3		T36	4
valid_sources[0x5f]	2464	1			T9	2		T11	2		T36	2
valid_sources[0x60]	2338	1			T6	1		T10	1		T11	2
valid_sources[0x61]	2202	1			T7	1		T9	2		T11	3
valid_sources[0x62]	2117	1			T7	2		T11	2		T35	1
valid_sources[0x63]	2221	1			T7	1		T11	5		T35	1
valid_sources[0x64]	2542	1			T7	1		T9	1		T11	4
valid_sources[0x65]	2231	1			T9	1		T11	5		T36	3
valid_sources[0x66]	2284	1			T7	4		T11	3		T35	13
valid_sources[0x67]	3301	1			T7	2		T9	6		T11	5
valid_sources[0x68]	2083	1			T7	1		T11	4		T36	1
valid_sources[0x69]	2263	1			T7	1		T11	5		T36	7
valid_sources[0x6a]	6491	1			T7	3		T11	9		T36	3
valid_sources[0x6b]	2048	1			T7	2		T11	4		T36	7
valid_sources[0x6c]	7339	1			T7	7		T9	3		T11	7
valid_sources[0x6d]	2459	1			T12	1		T11	5		T36	3
valid_sources[0x6e]	2183	1			T7	3		T11	9		T36	3
valid_sources[0x6f]	2182	1			T7	2		T11	3		T36	2
valid_sources[0x70]	2332	1			T7	1		T9	2		T11	5
valid_sources[0x71]	2297	1			T7	4		T11	6		T35	5
valid_sources[0x72]	2286	1			T7	1		T9	1		T11	5
valid_sources[0x73]	2172	1			T7	2		T11	8		T35	8
valid_sources[0x74]	2110	1			T7	1		T11	4		T35	3
valid_sources[0x75]	2295	1			T1	8		T7	3		T11	3
valid_sources[0x76]	2482	1			T11	1		T36	3		T38	1
valid_sources[0x77]	2532	1			T7	4		T11	4		T36	6
valid_sources[0x78]	2068	1			T7	2		T11	4		T35	16
valid_sources[0x79]	2163	1			T7	2		T11	9		T35	6
valid_sources[0x7a]	9646	1			T7	3		T11	3		T36	4
valid_sources[0x7b]	3444	1			T7	1		T11	2		T35	1
valid_sources[0x7c]	5417	1			T7	4		T11	8		T36	4
valid_sources[0x7d]	2155	1			T7	1		T11	1		T36	2
valid_sources[0x7e]	2283	1			T7	3		T9	2		T11	3
valid_sources[0x7f]	2161	1			T6	1		T7	4		T11	6
valid_sources[0x80]	2346	1			T6	2		T7	1		T11	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

167535

1

T1

7

T2

1

T3

1

values[0x0]

all_enables

biggest_size

47699

1

T1

5

T4

4

T6

2

values[0x1]

all_enables

biggest_size

26673

1

T1

1

T6

4

T7

12