SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34803 | 1 | T9 | 2 | T11 | 290 | T36 | 400 | ||||
others[1] | 35005 | 1 | T6 | 1 | T11 | 308 | T36 | 403 | ||||
others[2] | 34912 | 1 | T6 | 1 | T11 | 292 | T36 | 388 | ||||
others[3] | 58713 | 1 | T9 | 1 | T11 | 500 | T36 | 688 | ||||
false | 14886 | 1 | T6 | 2 | T9 | 1 | T11 | 50 | ||||
true | 23443 | 1 | T1 | 5 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35085 | 1 | T11 | 285 | T36 | 404 | T40 | 285 | ||||
others[1] | 35040 | 1 | T6 | 1 | T9 | 1 | T11 | 309 | ||||
others[2] | 34830 | 1 | T11 | 311 | T36 | 403 | T40 | 293 | ||||
others[3] | 58541 | 1 | T6 | 1 | T11 | 501 | T36 | 654 | ||||
false | 10030 | 1 | T6 | 1 | T9 | 4 | T11 | 50 | ||||
true | 18680 | 1 | T1 | 5 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 603 | 1 | T6 | 1 | T35 | 1 | T88 | 4 | ||||
others[1] | 603 | 1 | T9 | 1 | T35 | 2 | T88 | 8 | ||||
others[2] | 575 | 1 | T35 | 3 | T88 | 4 | T41 | 1 | ||||
others[3] | 1027 | 1 | T6 | 1 | T12 | 3 | T88 | 6 | ||||
false | 10857 | 1 | T1 | 5 | T2 | 2 | T3 | 2 | ||||
true | 3114 | 1 | T6 | 2 | T9 | 3 | T12 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |