Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	19956878	13418	0	0
intr_enable_rd_A	19956878	23645	0	0
reset_en_rd_A	19956878	1396	0	0
reset_en_regwen_rd_A	19956878	1295	0	0
wake_info_capture_dis_rd_A	19956878	1248	0	0
wakeup_en_rd_A	19956878	1925	0	0
wakeup_en_regwen_rd_A	19956878	1220	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19956878	13418	0	0
T15	327192	100	0	0
T22	0	2	0	0
T47	34454	0	0	0
T48	2370	0	0	0
T49	0	23	0	0
T50	0	63	0	0
T90	0	7	0	0
T103	0	4	0	0
T129	0	57	0	0
T130	0	1	0	0
T131	0	10	0	0
T132	0	16	0	0
T133	2237	0	0	0
T134	18673	0	0	0
T135	3239	0	0	0
T136	1781	0	0	0
T137	6327	0	0	0
T138	3524	0	0	0
T139	8368	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19956878	23645	0	0
T6	1966	8	0	0
T7	14554	0	0	0
T8	18218	51	0	0
T9	1681	0	0	0
T10	15296	0	0	0
T11	61745	186	0	0
T12	3125	0	0	0
T35	7608	0	0	0
T36	22271	0	0	0
T41	0	97	0	0
T42	1405	0	0	0
T88	0	87	0	0
T140	0	15	0	0
T141	0	26	0	0
T142	0	93	0	0
T143	0	65	0	0
T144	0	13	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19956878	1396	0	0
T58	0	50	0	0
T59	0	115	0	0
T63	0	10	0	0
T64	0	5	0	0
T66	0	1	0	0
T67	0	6	0	0
T89	0	16	0	0
T90	304936	9	0	0
T94	4140	0	0	0
T95	17667	0	0	0
T96	1860	0	0	0
T97	3300	0	0	0
T98	1550	0	0	0
T99	19832	0	0	0
T100	3299	0	0	0
T101	10636	0	0	0
T102	28171	0	0	0
T113	0	23	0	0
T132	0	9	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19956878	1295	0	0
T52	0	7	0	0
T58	0	32	0	0
T63	0	17	0	0
T64	0	6	0	0
T66	0	12	0	0
T89	0	13	0	0
T90	304936	17	0	0
T92	0	7	0	0
T94	4140	0	0	0
T95	17667	0	0	0
T96	1860	0	0	0
T97	3300	0	0	0
T98	1550	0	0	0
T99	19832	0	0	0
T100	3299	0	0	0
T101	10636	0	0	0
T102	28171	0	0	0
T113	0	18	0	0
T145	0	7	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19956878	1248	0	0
T52	0	10	0	0
T63	0	9	0	0
T64	0	17	0	0
T66	0	7	0	0
T67	0	4	0	0
T89	0	13	0	0
T90	304936	12	0	0
T94	4140	0	0	0
T95	17667	0	0	0
T96	1860	0	0	0
T97	3300	0	0	0
T98	1550	0	0	0
T99	19832	0	0	0
T100	3299	0	0	0
T101	10636	0	0	0
T102	28171	0	0	0
T113	0	18	0	0
T131	0	11	0	0
T145	0	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19956878	1925	0	0
T58	0	122	0	0
T59	0	252	0	0
T63	0	7	0	0
T64	0	4	0	0
T66	0	15	0	0
T89	0	43	0	0
T90	304936	12	0	0
T94	4140	0	0	0
T95	17667	0	0	0
T96	1860	0	0	0
T97	3300	0	0	0
T98	1550	0	0	0
T99	19832	0	0	0
T100	3299	0	0	0
T101	10636	0	0	0
T102	28171	0	0	0
T113	0	41	0	0
T114	0	34	0	0
T132	0	1	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19956878	1220	0	0
T52	0	2	0	0
T58	0	28	0	0
T59	0	69	0	0
T63	0	11	0	0
T64	0	10	0	0
T66	0	3	0	0
T67	0	1	0	0
T89	0	15	0	0
T90	304936	12	0	0
T94	4140	0	0	0
T95	17667	0	0	0
T96	1860	0	0	0
T97	3300	0	0	0
T98	1550	0	0	0
T99	19832	0	0	0
T100	3299	0	0	0
T101	10636	0	0	0
T102	28171	0	0	0
T113	0	24	0	0