Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_dft_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_hw_debug_en	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1856	1856	0	0
OutputsKnown_A	38754430	37916622	0	0
gen_flops.OutputDelay_A	38754430	37883076	0	5568

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1856	1856	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754430	37916622	0	0
T1	4384	3558	0	0
T2	4978	4668	0	0
T3	4722	4436	0	0
T4	5460	4692	0	0
T5	3958	3692	0	0
T6	3932	3578	0	0
T7	29108	28982	0	0
T8	36436	36334	0	0
T9	3362	3034	0	0
T10	30592	30468	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38754430	37883076	0	5568
T1	4384	3528	0	6
T2	4978	4656	0	6
T3	4722	4424	0	6
T4	5460	4662	0	6
T5	3958	3680	0	6
T6	3932	3566	0	6
T7	29108	28976	0	6
T8	36436	36328	0	6
T9	3362	3022	0	6
T10	30592	30462	0	6

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	928	928	0	0
OutputsKnown_A	19377215	18958311	0	0
gen_flops.OutputDelay_A	19377215	18941538	0	2784

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	928	928	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	18958311	0	0
T1	2192	1779	0	0
T2	2489	2334	0	0
T3	2361	2218	0	0
T4	2730	2346	0	0
T5	1979	1846	0	0
T6	1966	1789	0	0
T7	14554	14491	0	0
T8	18218	18167	0	0
T9	1681	1517	0	0
T10	15296	15234	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	18941538	0	2784
T1	2192	1764	0	3
T2	2489	2328	0	3
T3	2361	2212	0	3
T4	2730	2331	0	3
T5	1979	1840	0	3
T6	1966	1783	0	3
T7	14554	14488	0	3
T8	18218	18164	0	3
T9	1681	1511	0	3
T10	15296	15231	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	928	928	0	0
OutputsKnown_A	19377215	18958311	0	0
gen_flops.OutputDelay_A	19377215	18941538	0	2784

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	928	928	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	18958311	0	0
T1	2192	1779	0	0
T2	2489	2334	0	0
T3	2361	2218	0	0
T4	2730	2346	0	0
T5	1979	1846	0	0
T6	1966	1789	0	0
T7	14554	14491	0	0
T8	18218	18167	0	0
T9	1681	1517	0	0
T10	15296	15234	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	18941538	0	2784
T1	2192	1764	0	3
T2	2489	2328	0	3
T3	2361	2212	0	3
T4	2730	2331	0	3
T5	1979	1840	0	3
T6	1966	1783	0	3
T7	14554	14488	0	3
T8	18218	18164	0	3
T9	1681	1511	0	3
T10	15296	15231	0	3