Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	19377215	41012	0	0
IoStatusRise_A	19377215	45633	0	0
MainStatusFall_A	19377215	41012	0	0
MainStatusRise_A	19377215	45653	0	0
UsbStatusFall_A	19377215	31276	0	0
UsbStatusRise_A	19377215	35140	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	41012	0	0
T1	2192	4	0	0
T2	2489	1	0	0
T3	2361	1	0	0
T4	2730	4	0	0
T5	1979	1	0	0
T6	1966	5	0	0
T7	14554	15	0	0
T8	18218	19	0	0
T9	1681	5	0	0
T10	15296	1	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	45633	0	0
T1	2192	5	0	0
T2	2489	3	0	0
T3	2361	3	0	0
T4	2730	5	0	0
T5	1979	3	0	0
T6	1966	7	0	0
T7	14554	16	0	0
T8	18218	20	0	0
T9	1681	7	0	0
T10	15296	2	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	41012	0	0
T1	2192	4	0	0
T2	2489	1	0	0
T3	2361	1	0	0
T4	2730	4	0	0
T5	1979	1	0	0
T6	1966	5	0	0
T7	14554	15	0	0
T8	18218	19	0	0
T9	1681	5	0	0
T10	15296	1	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	45653	0	0
T1	2192	5	0	0
T2	2489	3	0	0
T3	2361	3	0	0
T4	2730	5	0	0
T5	1979	3	0	0
T6	1966	7	0	0
T7	14554	16	0	0
T8	18218	20	0	0
T9	1681	7	0	0
T10	15296	2	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	31276	0	0
T1	2192	4	0	0
T2	2489	1	0	0
T3	2361	1	0	0
T4	2730	4	0	0
T5	1979	1	0	0
T6	1966	5	0	0
T7	14554	8	0	0
T8	18218	17	0	0
T9	1681	5	0	0
T10	15296	1	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	35140	0	0
T1	2192	5	0	0
T2	2489	3	0	0
T3	2361	3	0	0
T4	2730	5	0	0
T5	1979	3	0	0
T6	1966	7	0	0
T7	14554	9	0	0
T8	18218	17	0	0
T9	1681	7	0	0
T10	15296	2	0	0