Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	19377215	45275	0	0
RomAllowCheckGoodState_A	19377215	45326	0	0
RomBlockActiveState_A	19377215	30960	0	0
RomBlockCheckGoodState_A	19377215	392786	0	0
RomIntgChkDisFalse_A	19377215	18736412	0	0
RomIntgChkDisTrue_A	19377215	221899	0	0
RstreqChkEsctimeout_A	19377215	3370	0	0
RstreqChkFsmterm_A	19377215	180	0	0
RstreqChkGlbesc_A	19377215	3371	0	0
RstreqChkMainpd_A	19377215	811446	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	45275	0	0
T1	2192	5	0	0
T2	2489	3	0	0
T3	2361	3	0	0
T4	2730	5	0	0
T5	1979	3	0	0
T6	1966	7	0	0
T7	14554	16	0	0
T8	18218	20	0	0
T9	1681	7	0	0
T10	15296	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	45326	0	0
T1	2192	5	0	0
T2	2489	3	0	0
T3	2361	3	0	0
T4	2730	5	0	0
T5	1979	3	0	0
T6	1966	7	0	0
T7	14554	16	0	0
T8	18218	20	0	0
T9	1681	7	0	0
T10	15296	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	30960	0	0
T6	1966	219	0	0
T7	14554	0	0	0
T8	18218	0	0	0
T9	1681	299	0	0
T10	15296	0	0	0
T11	61745	0	0	0
T12	3125	0	0	0
T35	7608	0	0	0
T36	22271	0	0	0
T39	0	937	0	0
T40	0	1	0	0
T42	1405	0	0	0
T134	0	10	0	0
T136	0	224	0	0
T144	0	470	0	0
T146	0	16	0	0
T147	0	1244	0	0
T148	0	16	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	392786	0	0
T6	1966	39	0	0
T7	14554	0	0	0
T8	18218	0	0	0
T9	1681	102	0	0
T10	15296	0	0	0
T11	61745	4053	0	0
T12	3125	0	0	0
T35	7608	0	0	0
T36	22271	1266	0	0
T37	0	436	0	0
T38	0	137	0	0
T39	0	639	0	0
T40	0	820	0	0
T42	1405	0	0	0
T141	0	368	0	0
T149	0	4089	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	18736412	0	0
T1	2192	1779	0	0
T2	2489	2334	0	0
T3	2361	2218	0	0
T4	2730	2346	0	0
T5	1979	1846	0	0
T6	1966	1606	0	0
T7	14554	14491	0	0
T8	18218	18167	0	0
T9	1681	1447	0	0
T10	15296	15234	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	221899	0	0
T6	1966	183	0	0
T7	14554	0	0	0
T8	18218	0	0	0
T9	1681	70	0	0
T10	15296	0	0	0
T11	61745	1921	0	0
T12	3125	0	0	0
T35	7608	0	0	0
T36	22271	0	0	0
T39	0	2264	0	0
T40	0	156	0	0
T42	1405	0	0	0
T136	0	672	0	0
T138	0	191	0	0
T144	0	229	0	0
T147	0	390	0	0
T149	0	978	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	3370	0	0
T2	2489	1	0	0
T3	2361	1	0	0
T4	2730	0	0	0
T5	1979	1	0	0
T6	1966	2	0	0
T7	14554	0	0	0
T8	18218	0	0	0
T9	1681	1	0	0
T10	15296	1	0	0
T12	3125	6	0	0
T35	0	6	0	0
T39	0	1	0	0
T41	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	180	0	0
T19	26319	40	0	0
T20	0	40	0	0
T21	0	20	0	0
T24	0	40	0	0
T25	0	40	0	0
T26	2450	0	0	0
T27	7564	0	0	0
T28	2343	0	0	0
T29	5680	0	0	0
T30	872	0	0	0
T31	45257	0	0	0
T32	12043	0	0	0
T33	2744	0	0	0
T34	17607	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	3371	0	0
T2	2489	1	0	0
T3	2361	1	0	0
T4	2730	0	0	0
T5	1979	1	0	0
T6	1966	2	0	0
T7	14554	0	0	0
T8	18218	0	0	0
T9	1681	1	0	0
T10	15296	1	0	0
T12	3125	6	0	0
T35	0	6	0	0
T39	0	1	0	0
T41	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19377215	811446	0	0
T6	1966	76	0	0
T7	14554	0	0	0
T8	18218	0	0	0
T9	1681	49	0	0
T10	15296	0	0	0
T11	61745	6994	0	0
T12	3125	126	0	0
T35	7608	666	0	0
T36	22271	1656	0	0
T37	0	543	0	0
T38	0	1014	0	0
T39	0	728	0	0
T40	0	821	0	0
T42	1405	0	0	0