Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	419169	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

207932

1

T1

1

T2

90

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	396220	1			T1	1		T2	191		T3	57
values[0x0]	115308	1			T2	19		T3	8		T6	24
values[0x1]	115573	1			T2	29		T3	14		T6	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	332340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

294761

1

T1

1

T2

118

T3

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1920	1			T2	3		T12	11		T13	1
valid_sources[0x01]	1499	1			T6	1		T9	1		T20	1
valid_sources[0x02]	1843	1			T6	1		T13	1		T38	7
valid_sources[0x03]	6955	1			T6	2		T12	1		T13	2
valid_sources[0x04]	1824	1			T38	6		T174	2		T137	1
valid_sources[0x05]	1794	1			T12	1		T38	1		T174	9
valid_sources[0x06]	1678	1			T2	1		T6	1		T12	4
valid_sources[0x07]	1620	1			T2	1		T6	3		T13	3
valid_sources[0x08]	1649	1			T2	1		T39	2		T12	7
valid_sources[0x09]	1782	1			T2	1		T12	1		T36	1
valid_sources[0x0a]	3599	1			T2	1		T6	1		T12	14
valid_sources[0x0b]	1704	1			T6	2		T12	11		T38	4
valid_sources[0x0c]	1869	1			T6	1		T12	5		T36	2
valid_sources[0x0d]	2053	1			T2	2		T12	10		T38	3
valid_sources[0x0e]	1742	1			T2	1		T12	17		T13	2
valid_sources[0x0f]	10209	1			T2	2		T12	1		T13	3
valid_sources[0x10]	1806	1			T20	34		T12	3		T36	1
valid_sources[0x11]	1588	1			T2	1		T12	7		T38	2
valid_sources[0x12]	6851	1			T2	2		T36	2		T38	7
valid_sources[0x13]	1766	1			T2	2		T13	4		T81	4
valid_sources[0x14]	1672	1			T2	1		T13	6		T38	7
valid_sources[0x15]	1682	1			T6	1		T12	2		T13	1
valid_sources[0x16]	1681	1			T2	2		T20	1		T36	1
valid_sources[0x17]	1776	1			T6	1		T38	2		T174	5
valid_sources[0x18]	1559	1			T2	2		T20	25		T12	4
valid_sources[0x19]	1629	1			T4	1		T20	41		T12	2
valid_sources[0x1a]	1779	1			T6	1		T7	1		T12	14
valid_sources[0x1b]	1729	1			T2	1		T12	1		T13	1
valid_sources[0x1c]	3034	1			T6	1		T12	9		T36	2
valid_sources[0x1d]	1761	1			T6	2		T39	3		T20	6
valid_sources[0x1e]	2199	1			T2	1		T12	6		T13	2
valid_sources[0x1f]	1834	1			T20	13		T38	3		T174	10
valid_sources[0x20]	1830	1			T2	1		T12	1		T38	3
valid_sources[0x21]	1700	1			T12	1		T36	1		T38	3
valid_sources[0x22]	1801	1			T2	1		T39	2		T12	9
valid_sources[0x23]	3349	1			T12	10		T81	1		T80	1
valid_sources[0x24]	1743	1			T2	1		T6	2		T12	17
valid_sources[0x25]	1723	1			T6	2		T12	6		T13	3
valid_sources[0x26]	1741	1			T20	12		T12	13		T81	5
valid_sources[0x27]	1770	1			T2	1		T6	2		T13	1
valid_sources[0x28]	2126	1			T6	1		T12	3		T81	8
valid_sources[0x29]	1717	1			T2	1		T20	3		T12	2
valid_sources[0x2a]	1507	1			T2	2		T38	6		T50	5
valid_sources[0x2b]	2390	1			T8	13		T12	7		T81	2
valid_sources[0x2c]	2860	1			T2	1		T13	1		T38	2
valid_sources[0x2d]	1659	1			T2	2		T38	12		T174	9
valid_sources[0x2e]	1739	1			T13	3		T81	8		T38	2
valid_sources[0x2f]	1977	1			T6	1		T12	1		T38	7
valid_sources[0x30]	1871	1			T6	2		T38	6		T174	14
valid_sources[0x31]	3118	1			T2	2		T20	5		T81	3
valid_sources[0x32]	1762	1			T2	2		T81	1		T174	11
valid_sources[0x33]	2973	1			T12	1		T13	1		T36	2
valid_sources[0x34]	7095	1			T2	1		T36	2		T38	1
valid_sources[0x35]	3107	1			T20	10		T13	2		T80	1
valid_sources[0x36]	1644	1			T12	3		T13	1		T36	1
valid_sources[0x37]	1926	1			T2	1		T20	9		T47	33
valid_sources[0x38]	3773	1			T12	1		T36	2		T38	6
valid_sources[0x39]	1684	1			T20	44		T12	4		T36	1
valid_sources[0x3a]	1800	1			T2	1		T38	4		T174	4
valid_sources[0x3b]	1714	1			T36	4		T81	9		T38	11
valid_sources[0x3c]	1852	1			T8	3		T13	3		T80	1
valid_sources[0x3d]	2759	1			T2	1		T6	1		T20	5
valid_sources[0x3e]	1470	1			T2	1		T12	2		T81	1
valid_sources[0x3f]	1849	1			T2	1		T20	10		T38	4
valid_sources[0x40]	1645	1			T2	2		T81	3		T38	3
valid_sources[0x41]	1997	1			T2	1		T39	1		T20	13
valid_sources[0x42]	1775	1			T2	1		T6	1		T8	8
valid_sources[0x43]	1628	1			T2	2		T6	1		T12	1
valid_sources[0x44]	3243	1			T8	40		T36	1		T38	2
valid_sources[0x45]	1671	1			T2	1		T6	1		T36	1
valid_sources[0x46]	2140	1			T2	1		T12	8		T36	3
valid_sources[0x47]	1788	1			T2	1		T13	2		T38	2
valid_sources[0x48]	3122	1			T2	3		T6	1		T20	9
valid_sources[0x49]	2450	1			T2	3		T6	1		T20	8
valid_sources[0x4a]	1957	1			T2	2		T81	6		T38	3
valid_sources[0x4b]	1668	1			T81	5		T38	2		T174	10
valid_sources[0x4c]	5016	1			T2	2		T12	9		T13	3
valid_sources[0x4d]	5216	1			T8	24		T12	4		T36	1
valid_sources[0x4e]	2819	1			T6	1		T8	11		T36	2
valid_sources[0x4f]	1621	1			T12	9		T81	2		T38	3
valid_sources[0x50]	6101	1			T6	1		T36	1		T38	1
valid_sources[0x51]	5993	1			T39	1		T38	9		T174	6
valid_sources[0x52]	1890	1			T2	1		T12	5		T13	4
valid_sources[0x53]	1692	1			T2	1		T6	1		T8	17
valid_sources[0x54]	9224	1			T6	1		T12	4		T36	2
valid_sources[0x55]	1772	1			T2	1		T12	14		T36	5
valid_sources[0x56]	1718	1			T2	1		T6	2		T12	4
valid_sources[0x57]	1812	1			T2	1		T81	1		T38	6
valid_sources[0x58]	4482	1			T12	4		T38	1		T44	2
valid_sources[0x59]	1607	1			T2	2		T6	1		T20	2
valid_sources[0x5a]	4234	1			T2	2		T39	4		T12	1
valid_sources[0x5b]	1884	1			T38	4		T44	1		T174	9
valid_sources[0x5c]	1999	1			T2	2		T36	1		T38	3
valid_sources[0x5d]	1680	1			T2	1		T12	1		T13	2
valid_sources[0x5e]	1604	1			T2	2		T12	17		T81	2
valid_sources[0x5f]	1943	1			T6	1		T12	5		T36	4
valid_sources[0x60]	1778	1			T2	3		T20	59		T12	1
valid_sources[0x61]	1803	1			T2	3		T13	1		T174	3
valid_sources[0x62]	1760	1			T36	1		T38	5		T44	1
valid_sources[0x63]	1602	1			T6	1		T39	3		T20	1
valid_sources[0x64]	1667	1			T2	1		T36	2		T38	2
valid_sources[0x65]	3538	1			T8	6		T10	940		T13	1
valid_sources[0x66]	1481	1			T12	13		T13	1		T36	1
valid_sources[0x67]	1717	1			T2	4		T6	1		T12	3
valid_sources[0x68]	1515	1			T2	1		T6	1		T80	1
valid_sources[0x69]	1619	1			T2	2		T6	1		T36	3
valid_sources[0x6a]	1916	1			T2	1		T6	1		T190	1
valid_sources[0x6b]	1937	1			T12	27		T38	1		T191	1
valid_sources[0x6c]	1609	1			T13	2		T81	1		T38	1
valid_sources[0x6d]	1642	1			T2	1		T36	2		T38	11
valid_sources[0x6e]	5326	1			T12	2		T36	2		T80	3
valid_sources[0x6f]	1598	1			T2	3		T6	2		T12	2
valid_sources[0x70]	1554	1			T2	1		T20	8		T12	1
valid_sources[0x71]	2568	1			T2	2		T6	1		T12	5
valid_sources[0x72]	23050	1			T2	1		T5	1		T12	15
valid_sources[0x73]	6548	1			T8	6		T13	2		T14	4713
valid_sources[0x74]	2027	1			T2	3		T6	2		T8	12
valid_sources[0x75]	1833	1			T2	1		T6	1		T39	1
valid_sources[0x76]	2168	1			T13	2		T36	2		T38	6
valid_sources[0x77]	1973	1			T20	7		T12	7		T36	4
valid_sources[0x78]	1646	1			T6	1		T12	21		T38	1
valid_sources[0x79]	3440	1			T2	2		T36	2		T81	6
valid_sources[0x7a]	2211	1			T2	1		T39	1		T13	2
valid_sources[0x7b]	5690	1			T2	1		T8	20		T12	1
valid_sources[0x7c]	2677	1			T2	2		T20	14		T12	22
valid_sources[0x7d]	2691	1			T2	1		T8	2		T13	1
valid_sources[0x7e]	1760	1			T2	2		T12	1		T38	3
valid_sources[0x7f]	1752	1			T2	1		T36	1		T38	4
valid_sources[0x80]	1606	1			T12	9		T38	4		T174	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

139205

1

T1

1

T2

83

T3

18

values[0x0]

all_enables

biggest_size

43926

1

T2

6

T6

13

T7

1

values[0x1]

all_enables

biggest_size

24801

1

T2

1

T3

6

T6

2