SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34490 | 1 | T10 | 302 | T20 | 307 | T37 | 420 | ||||
others[1] | 35026 | 1 | T3 | 1 | T10 | 292 | T20 | 300 | ||||
others[2] | 34641 | 1 | T10 | 318 | T20 | 306 | T37 | 399 | ||||
others[3] | 57995 | 1 | T3 | 1 | T10 | 494 | T20 | 487 | ||||
false | 13155 | 1 | T3 | 2 | T10 | 50 | T20 | 50 | ||||
true | 21151 | 1 | T1 | 6 | T2 | 1 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34760 | 1 | T10 | 297 | T20 | 323 | T37 | 403 | ||||
others[1] | 34920 | 1 | T10 | 282 | T20 | 316 | T37 | 431 | ||||
others[2] | 34613 | 1 | T10 | 291 | T20 | 273 | T37 | 419 | ||||
others[3] | 57587 | 1 | T10 | 509 | T20 | 495 | T35 | 1 | ||||
false | 9146 | 1 | T3 | 3 | T10 | 50 | T20 | 50 | ||||
true | 17208 | 1 | T1 | 6 | T2 | 1 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 545 | 1 | T3 | 1 | T8 | 4 | T14 | 1 | ||||
others[1] | 543 | 1 | T8 | 5 | T12 | 1 | T14 | 4 | ||||
others[2] | 520 | 1 | T8 | 5 | T12 | 3 | T13 | 1 | ||||
others[3] | 873 | 1 | T8 | 11 | T13 | 2 | T14 | 5 | ||||
false | 9522 | 1 | T1 | 6 | T2 | 1 | T3 | 6 | ||||
true | 2656 | 1 | T3 | 4 | T8 | 2 | T12 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |