Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T20,T47

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16925416	4535	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16925416	192400	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16925416	6890427	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16925416	192437	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16925416	4535	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16925416	192400	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16925416	6890427	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16925416	192437	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	4535	0	0
T10	21807	26	0	0
T11	15089	0	0	0
T12	35556	1	0	0
T13	2395	0	0	0
T14	0	4	0	0
T16	4022	0	0	0
T20	34726	23	0	0
T36	0	4	0	0
T37	0	24	0	0
T38	0	30	0	0
T39	1458	3	0	0
T40	849	0	0	0
T41	15104	0	0	0
T47	1894	2	0	0
T80	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	192400	0	0
T10	21807	497	0	0
T11	15089	0	0	0
T12	35556	12	0	0
T13	2395	0	0	0
T14	0	112	0	0
T16	4022	0	0	0
T20	34726	940	0	0
T36	0	64	0	0
T37	0	567	0	0
T38	0	1334	0	0
T39	1458	205	0	0
T40	849	0	0	0
T41	15104	0	0	0
T47	1894	242	0	0
T80	0	15	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	6890427	0	0
T2	7308	5683	0	0
T3	5390	0	0	0
T4	1819	0	0	0
T5	668	0	0	0
T6	3101	2216	0	0
T7	2329	1522	0	0
T8	6218	0	0	0
T9	846	0	0	0
T10	21807	11970	0	0
T11	15089	0	0	0
T12	0	14824	0	0
T14	0	47903	0	0
T20	0	17282	0	0
T36	0	1954	0	0
T39	0	705	0	0
T47	0	235	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	192437	0	0
T10	21807	497	0	0
T11	15089	0	0	0
T12	35556	12	0	0
T13	2395	0	0	0
T14	0	112	0	0
T16	4022	0	0	0
T20	34726	938	0	0
T36	0	64	0	0
T37	0	567	0	0
T38	0	1331	0	0
T39	1458	205	0	0
T40	849	0	0	0
T41	15104	0	0	0
T47	1894	242	0	0
T80	0	15	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	4535	0	0
T10	21807	26	0	0
T11	15089	0	0	0
T12	35556	1	0	0
T13	2395	0	0	0
T14	0	4	0	0
T16	4022	0	0	0
T20	34726	23	0	0
T36	0	4	0	0
T37	0	24	0	0
T38	0	30	0	0
T39	1458	3	0	0
T40	849	0	0	0
T41	15104	0	0	0
T47	1894	2	0	0
T80	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	192400	0	0
T10	21807	497	0	0
T11	15089	0	0	0
T12	35556	12	0	0
T13	2395	0	0	0
T14	0	112	0	0
T16	4022	0	0	0
T20	34726	940	0	0
T36	0	64	0	0
T37	0	567	0	0
T38	0	1334	0	0
T39	1458	205	0	0
T40	849	0	0	0
T41	15104	0	0	0
T47	1894	242	0	0
T80	0	15	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	6890427	0	0
T2	7308	5683	0	0
T3	5390	0	0	0
T4	1819	0	0	0
T5	668	0	0	0
T6	3101	2216	0	0
T7	2329	1522	0	0
T8	6218	0	0	0
T9	846	0	0	0
T10	21807	11970	0	0
T11	15089	0	0	0
T12	0	14824	0	0
T14	0	47903	0	0
T20	0	17282	0	0
T36	0	1954	0	0
T39	0	705	0	0
T47	0	235	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	192437	0	0
T10	21807	497	0	0
T11	15089	0	0	0
T12	35556	12	0	0
T13	2395	0	0	0
T14	0	112	0	0
T16	4022	0	0	0
T20	34726	938	0	0
T36	0	64	0	0
T37	0	567	0	0
T38	0	1331	0	0
T39	1458	205	0	0
T40	849	0	0	0
T41	15104	0	0	0
T47	1894	242	0	0
T80	0	15	0	0