Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17590103	16187	0	0
intr_enable_rd_A	17590103	19069	0	0
reset_en_rd_A	17590103	2060	0	0
reset_en_regwen_rd_A	17590103	1804	0	0
wake_info_capture_dis_rd_A	17590103	1780	0	0
wakeup_en_rd_A	17590103	2816	0	0
wakeup_en_regwen_rd_A	17590103	1867	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17590103	16187	0	0
T21	277836	35	0	0
T22	0	15	0	0
T23	0	97	0	0
T33	0	15	0	0
T46	65316	0	0	0
T54	0	14	0	0
T71	0	29	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	64	0	0
T127	0	40	0	0
T128	1648	0	0	0
T129	59161	0	0	0
T130	3193	0	0	0
T131	1715	0	0	0
T132	23577	0	0	0
T133	6032	0	0	0
T134	3583	0	0	0
T135	5619	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17590103	19069	0	0
T3	5390	18	0	0
T4	1819	0	0	0
T5	668	0	0	0
T6	3101	22	0	0
T7	2329	0	0	0
T8	6218	0	0	0
T9	846	0	0	0
T10	21807	172	0	0
T11	15089	0	0	0
T38	0	171	0	0
T39	1458	0	0	0
T60	0	5	0	0
T81	0	66	0	0
T133	0	17	0	0
T135	0	22	0	0
T136	0	3	0	0
T137	0	57	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17590103	2060	0	0
T19	9053	0	0	0
T62	0	35	0	0
T64	0	24	0	0
T74	0	12	0	0
T105	0	97	0	0
T122	0	49	0	0
T123	0	14	0	0
T138	250791	5	0	0
T139	0	4	0	0
T140	0	3	0	0
T141	0	3	0	0
T142	2474	0	0	0
T143	772	0	0	0
T144	3032	0	0	0
T145	15261	0	0	0
T146	1632	0	0	0
T147	7422	0	0	0
T148	6469	0	0	0
T149	1874	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17590103	1804	0	0
T19	9053	0	0	0
T62	0	21	0	0
T64	0	18	0	0
T74	0	10	0	0
T105	0	87	0	0
T107	0	21	0	0
T122	0	58	0	0
T123	0	7	0	0
T138	250791	3	0	0
T139	0	3	0	0
T141	0	3	0	0
T142	2474	0	0	0
T143	772	0	0	0
T144	3032	0	0	0
T145	15261	0	0	0
T146	1632	0	0	0
T147	7422	0	0	0
T148	6469	0	0	0
T149	1874	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17590103	1780	0	0
T62	0	12	0	0
T64	0	16	0	0
T74	0	8	0	0
T105	0	94	0	0
T107	0	17	0	0
T122	0	47	0	0
T123	0	4	0	0
T139	569780	2	0	0
T140	0	7	0	0
T141	0	6	0	0
T150	1655	0	0	0
T151	3150	0	0	0
T152	187555	0	0	0
T153	1796	0	0	0
T154	55545	0	0	0
T155	2651	0	0	0
T156	15295	0	0	0
T157	5280	0	0	0
T158	2447	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17590103	2816	0	0
T19	9053	0	0	0
T62	0	38	0	0
T64	0	49	0	0
T74	0	26	0	0
T105	0	120	0	0
T107	0	2	0	0
T108	0	37	0	0
T122	0	69	0	0
T123	0	15	0	0
T138	250791	10	0	0
T139	0	1	0	0
T142	2474	0	0	0
T143	772	0	0	0
T144	3032	0	0	0
T145	15261	0	0	0
T146	1632	0	0	0
T147	7422	0	0	0
T148	6469	0	0	0
T149	1874	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17590103	1867	0	0
T53	0	4	0	0
T62	0	17	0	0
T64	0	12	0	0
T74	0	12	0	0
T105	0	135	0	0
T107	0	6	0	0
T108	0	5	0	0
T122	0	41	0	0
T123	0	7	0	0
T141	245293	1	0	0
T159	2638	0	0	0
T160	2024	0	0	0
T161	3131	0	0	0
T162	2780	0	0	0
T163	5849	0	0	0
T164	23372	0	0	0
T165	17259	0	0	0
T166	1472	0	0	0
T167	85531	0	0	0