Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	16925416	40089	0	0
RomAllowCheckGoodState_A	16925416	40139	0	0
RomBlockActiveState_A	16925416	31479	0	0
RomBlockCheckGoodState_A	16925416	371494	0	0
RomIntgChkDisFalse_A	16925416	16465317	0	0
RomIntgChkDisTrue_A	16925416	88733	0	0
RstreqChkEsctimeout_A	16925416	2869	0	0
RstreqChkFsmterm_A	16925416	120	0	0
RstreqChkGlbesc_A	16925416	2871	0	0
RstreqChkMainpd_A	16925416	729492	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	40089	0	0
T1	1247	6	0	0
T2	7308	8	0	0
T3	5390	8	0	0
T4	1819	4	0	0
T5	668	3	0	0
T6	3101	5	0	0
T7	2329	2	0	0
T8	6218	3	0	0
T9	846	3	0	0
T10	21807	91	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	40139	0	0
T1	1247	6	0	0
T2	7308	8	0	0
T3	5390	8	0	0
T4	1819	4	0	0
T5	668	3	0	0
T6	3101	5	0	0
T7	2329	2	0	0
T8	6218	3	0	0
T9	846	3	0	0
T10	21807	91	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	31479	0	0
T3	5390	1259	0	0
T4	1819	0	0	0
T5	668	0	0	0
T6	3101	0	0	0
T7	2329	0	0	0
T8	6218	0	0	0
T9	846	0	0	0
T10	21807	8	0	0
T11	15089	0	0	0
T35	0	226	0	0
T37	0	36	0	0
T39	1458	0	0	0
T133	0	1492	0	0
T169	0	260	0	0
T170	0	252	0	0
T171	0	361	0	0
T172	0	715	0	0
T173	0	710	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	371494	0	0
T3	5390	648	0	0
T4	1819	0	0	0
T5	668	0	0	0
T6	3101	0	0	0
T7	2329	0	0	0
T8	6218	0	0	0
T9	846	0	0	0
T10	21807	996	0	0
T11	15089	0	0	0
T14	0	115	0	0
T20	0	2285	0	0
T21	0	3327	0	0
T35	0	48	0	0
T36	0	161	0	0
T37	0	1273	0	0
T38	0	2271	0	0
T39	1458	0	0	0
T174	0	3999	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	16465317	0	0
T1	1247	816	0	0
T2	7308	7243	0	0
T3	5390	4593	0	0
T4	1819	1466	0	0
T5	668	485	0	0
T6	3101	3009	0	0
T7	2329	2237	0	0
T8	6218	6143	0	0
T9	846	681	0	0
T10	21807	21612	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	88733	0	0
T3	5390	736	0	0
T4	1819	0	0	0
T5	668	0	0	0
T6	3101	0	0	0
T7	2329	0	0	0
T8	6218	0	0	0
T9	846	0	0	0
T10	21807	118	0	0
T11	15089	0	0	0
T20	0	2361	0	0
T35	0	68	0	0
T39	1458	0	0	0
T133	0	553	0	0
T169	0	1003	0	0
T170	0	69	0	0
T171	0	970	0	0
T172	0	265	0	0
T173	0	422	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	2869	0	0
T3	5390	3	0	0
T4	1819	0	0	0
T5	668	1	0	0
T6	3101	0	0	0
T7	2329	0	0	0
T8	6218	0	0	0
T9	846	1	0	0
T10	21807	0	0	0
T11	15089	1	0	0
T12	0	8	0	0
T13	0	8	0	0
T35	0	2	0	0
T39	1458	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	120	0	0
T17	9053	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T24	0	40	0	0
T25	0	20	0	0
T26	1189	0	0	0
T27	11189	0	0	0
T28	15664	0	0	0
T29	1391	0	0	0
T30	791	0	0	0
T31	6710	0	0	0
T32	1356	0	0	0
T33	86175	0	0	0
T34	2826	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	2871	0	0
T3	5390	3	0	0
T4	1819	0	0	0
T5	668	1	0	0
T6	3101	0	0	0
T7	2329	0	0	0
T8	6218	0	0	0
T9	846	1	0	0
T10	21807	0	0	0
T11	15089	1	0	0
T12	0	8	0	0
T13	0	8	0	0
T35	0	2	0	0
T39	1458	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16925416	729492	0	0
T1	1247	21	0	0
T2	7308	0	0	0
T3	5390	1371	0	0
T4	1819	17	0	0
T5	668	0	0	0
T6	3101	0	0	0
T7	2329	0	0	0
T8	6218	0	0	0
T9	846	0	0	0
T10	21807	1555	0	0
T12	0	250	0	0
T13	0	220	0	0
T16	0	26	0	0
T20	0	3004	0	0
T35	0	90	0	0
T36	0	107	0	0