| T811 |
/workspace/coverage/default/43.pwrmgr_wakeup.567709122 |
|
|
Mar 05 01:42:53 PM PST 24 |
Mar 05 01:42:54 PM PST 24 |
504818700 ps |
| T812 |
/workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1086332201 |
|
|
Mar 05 01:43:47 PM PST 24 |
Mar 05 01:43:50 PM PST 24 |
942692837 ps |
| T813 |
/workspace/coverage/default/41.pwrmgr_aborted_low_power.1754455396 |
|
|
Mar 05 01:42:42 PM PST 24 |
Mar 05 01:42:43 PM PST 24 |
21614059 ps |
| T814 |
/workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.642760488 |
|
|
Mar 05 01:42:33 PM PST 24 |
Mar 05 01:42:35 PM PST 24 |
128894229 ps |
| T815 |
/workspace/coverage/default/5.pwrmgr_lowpower_invalid.914760881 |
|
|
Mar 05 01:37:02 PM PST 24 |
Mar 05 01:37:03 PM PST 24 |
283327864 ps |
| T816 |
/workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3782560249 |
|
|
Mar 05 01:39:59 PM PST 24 |
Mar 05 01:40:04 PM PST 24 |
56070900 ps |
| T817 |
/workspace/coverage/default/1.pwrmgr_wakeup.2602615570 |
|
|
Mar 05 01:36:10 PM PST 24 |
Mar 05 01:36:12 PM PST 24 |
221140264 ps |
| T818 |
/workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.256272563 |
|
|
Mar 05 01:43:45 PM PST 24 |
Mar 05 01:43:46 PM PST 24 |
172720901 ps |
| T819 |
/workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4293012776 |
|
|
Mar 05 01:37:24 PM PST 24 |
Mar 05 01:37:25 PM PST 24 |
84620411 ps |
| T820 |
/workspace/coverage/default/22.pwrmgr_glitch.1261299778 |
|
|
Mar 05 01:39:41 PM PST 24 |
Mar 05 01:39:42 PM PST 24 |
133175226 ps |
| T821 |
/workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2376688696 |
|
|
Mar 05 01:38:52 PM PST 24 |
Mar 05 01:38:53 PM PST 24 |
30278560 ps |
| T822 |
/workspace/coverage/default/13.pwrmgr_aborted_low_power.1940479672 |
|
|
Mar 05 01:38:19 PM PST 24 |
Mar 05 01:38:19 PM PST 24 |
59800831 ps |
| T823 |
/workspace/coverage/default/37.pwrmgr_reset_invalid.3809487557 |
|
|
Mar 05 01:42:07 PM PST 24 |
Mar 05 01:42:08 PM PST 24 |
114269975 ps |
| T824 |
/workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3017894423 |
|
|
Mar 05 01:42:06 PM PST 24 |
Mar 05 01:42:07 PM PST 24 |
251022315 ps |
| T825 |
/workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.176120214 |
|
|
Mar 05 01:39:32 PM PST 24 |
Mar 05 01:39:38 PM PST 24 |
838319038 ps |
| T826 |
/workspace/coverage/default/17.pwrmgr_reset_invalid.429044359 |
|
|
Mar 05 01:38:57 PM PST 24 |
Mar 05 01:38:58 PM PST 24 |
166202489 ps |
| T827 |
/workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.432430792 |
|
|
Mar 05 01:42:05 PM PST 24 |
Mar 05 01:42:06 PM PST 24 |
112746123 ps |
| T828 |
/workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.12226524 |
|
|
Mar 05 01:42:45 PM PST 24 |
Mar 05 01:42:46 PM PST 24 |
30071374 ps |
| T829 |
/workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2334235072 |
|
|
Mar 05 01:43:06 PM PST 24 |
Mar 05 01:43:10 PM PST 24 |
885541487 ps |
| T830 |
/workspace/coverage/default/3.pwrmgr_smoke.2312972706 |
|
|
Mar 05 01:36:32 PM PST 24 |
Mar 05 01:36:33 PM PST 24 |
68937911 ps |
| T831 |
/workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3728211080 |
|
|
Mar 05 01:39:08 PM PST 24 |
Mar 05 01:39:09 PM PST 24 |
97044006 ps |
| T832 |
/workspace/coverage/default/32.pwrmgr_reset_invalid.2845955956 |
|
|
Mar 05 01:41:18 PM PST 24 |
Mar 05 01:41:19 PM PST 24 |
346804419 ps |
| T833 |
/workspace/coverage/default/49.pwrmgr_wakeup_reset.441953185 |
|
|
Mar 05 01:43:45 PM PST 24 |
Mar 05 01:43:47 PM PST 24 |
261129231 ps |
| T834 |
/workspace/coverage/default/44.pwrmgr_smoke.28699252 |
|
|
Mar 05 01:43:00 PM PST 24 |
Mar 05 01:43:01 PM PST 24 |
36490383 ps |
| T835 |
/workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3101691415 |
|
|
Mar 05 01:39:24 PM PST 24 |
Mar 05 01:39:27 PM PST 24 |
157773745 ps |
| T836 |
/workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.160031064 |
|
|
Mar 05 01:35:42 PM PST 24 |
Mar 05 01:35:46 PM PST 24 |
747744207 ps |
| T837 |
/workspace/coverage/default/29.pwrmgr_global_esc.2401953449 |
|
|
Mar 05 01:40:55 PM PST 24 |
Mar 05 01:40:56 PM PST 24 |
88005560 ps |
| T838 |
/workspace/coverage/default/7.pwrmgr_wakeup_reset.889708558 |
|
|
Mar 05 01:37:16 PM PST 24 |
Mar 05 01:37:17 PM PST 24 |
97381696 ps |
| T839 |
/workspace/coverage/default/39.pwrmgr_smoke.940238899 |
|
|
Mar 05 01:42:23 PM PST 24 |
Mar 05 01:42:24 PM PST 24 |
54000064 ps |
| T840 |
/workspace/coverage/default/27.pwrmgr_aborted_low_power.1766187917 |
|
|
Mar 05 01:40:32 PM PST 24 |
Mar 05 01:40:32 PM PST 24 |
64338100 ps |
| T841 |
/workspace/coverage/default/14.pwrmgr_smoke.855709579 |
|
|
Mar 05 01:38:21 PM PST 24 |
Mar 05 01:38:22 PM PST 24 |
39278852 ps |
| T842 |
/workspace/coverage/default/4.pwrmgr_wakeup_reset.3695337496 |
|
|
Mar 05 01:36:43 PM PST 24 |
Mar 05 01:36:45 PM PST 24 |
369027019 ps |
| T843 |
/workspace/coverage/default/7.pwrmgr_glitch.828447558 |
|
|
Mar 05 01:37:17 PM PST 24 |
Mar 05 01:37:18 PM PST 24 |
65541621 ps |
| T844 |
/workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1450298326 |
|
|
Mar 05 01:37:38 PM PST 24 |
Mar 05 01:37:42 PM PST 24 |
715914781 ps |
| T845 |
/workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.4090525832 |
|
|
Mar 05 01:42:46 PM PST 24 |
Mar 05 01:42:47 PM PST 24 |
51610288 ps |
| T846 |
/workspace/coverage/default/46.pwrmgr_global_esc.721135295 |
|
|
Mar 05 01:43:25 PM PST 24 |
Mar 05 01:43:26 PM PST 24 |
33439515 ps |
| T847 |
/workspace/coverage/default/32.pwrmgr_escalation_timeout.202486356 |
|
|
Mar 05 01:41:18 PM PST 24 |
Mar 05 01:41:19 PM PST 24 |
162472507 ps |
| T848 |
/workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3929121264 |
|
|
Mar 05 01:40:55 PM PST 24 |
Mar 05 01:40:55 PM PST 24 |
93275816 ps |
| T849 |
/workspace/coverage/default/17.pwrmgr_smoke.792515711 |
|
|
Mar 05 01:38:48 PM PST 24 |
Mar 05 01:38:49 PM PST 24 |
30893828 ps |
| T850 |
/workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2095058608 |
|
|
Mar 05 01:40:43 PM PST 24 |
Mar 05 01:40:44 PM PST 24 |
37146341 ps |
| T851 |
/workspace/coverage/default/24.pwrmgr_smoke.199877 |
|
|
Mar 05 01:39:59 PM PST 24 |
Mar 05 01:40:05 PM PST 24 |
28822040 ps |
| T852 |
/workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.1014275859 |
|
|
Mar 05 01:38:57 PM PST 24 |
Mar 05 01:38:58 PM PST 24 |
413511498 ps |
| T853 |
/workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4272427439 |
|
|
Mar 05 01:38:50 PM PST 24 |
Mar 05 01:38:54 PM PST 24 |
956813534 ps |
| T854 |
/workspace/coverage/default/8.pwrmgr_wakeup.60130063 |
|
|
Mar 05 01:37:26 PM PST 24 |
Mar 05 01:37:26 PM PST 24 |
78496555 ps |
| T855 |
/workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1142578225 |
|
|
Mar 05 01:39:19 PM PST 24 |
Mar 05 01:39:22 PM PST 24 |
40867548 ps |
| T856 |
/workspace/coverage/default/38.pwrmgr_lowpower_invalid.2934866136 |
|
|
Mar 05 01:42:19 PM PST 24 |
Mar 05 01:42:20 PM PST 24 |
55638352 ps |
| T857 |
/workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.3208065020 |
|
|
Mar 05 01:42:18 PM PST 24 |
Mar 05 01:42:19 PM PST 24 |
71506949 ps |
| T858 |
/workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4260232840 |
|
|
Mar 05 01:39:53 PM PST 24 |
Mar 05 01:39:58 PM PST 24 |
862528976 ps |
| T859 |
/workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2895292871 |
|
|
Mar 05 01:39:59 PM PST 24 |
Mar 05 01:40:04 PM PST 24 |
92406329 ps |
| T860 |
/workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4116350083 |
|
|
Mar 05 01:39:01 PM PST 24 |
Mar 05 01:39:05 PM PST 24 |
904285623 ps |
| T861 |
/workspace/coverage/default/43.pwrmgr_global_esc.1173603337 |
|
|
Mar 05 01:43:03 PM PST 24 |
Mar 05 01:43:04 PM PST 24 |
52154762 ps |
| T862 |
/workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.3896964069 |
|
|
Mar 05 01:39:17 PM PST 24 |
Mar 05 01:39:20 PM PST 24 |
53210322 ps |
| T863 |
/workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2272862005 |
|
|
Mar 05 01:40:19 PM PST 24 |
Mar 05 01:40:20 PM PST 24 |
128639888 ps |
| T864 |
/workspace/coverage/default/41.pwrmgr_wakeup_reset.1724980014 |
|
|
Mar 05 01:42:39 PM PST 24 |
Mar 05 01:42:41 PM PST 24 |
285655425 ps |
| T865 |
/workspace/coverage/default/23.pwrmgr_smoke.313682396 |
|
|
Mar 05 01:39:56 PM PST 24 |
Mar 05 01:40:02 PM PST 24 |
54460695 ps |
| T75 |
/workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.2666892367 |
|
|
Mar 05 01:39:55 PM PST 24 |
Mar 05 01:40:29 PM PST 24 |
6613406718 ps |
| T866 |
/workspace/coverage/default/36.pwrmgr_stress_all.4265083267 |
|
|
Mar 05 01:41:59 PM PST 24 |
Mar 05 01:42:02 PM PST 24 |
1967675198 ps |
| T867 |
/workspace/coverage/default/3.pwrmgr_lowpower_invalid.118227439 |
|
|
Mar 05 01:36:40 PM PST 24 |
Mar 05 01:36:40 PM PST 24 |
48020149 ps |
| T868 |
/workspace/coverage/default/22.pwrmgr_reset_invalid.2059343267 |
|
|
Mar 05 01:40:02 PM PST 24 |
Mar 05 01:40:07 PM PST 24 |
101051491 ps |
| T869 |
/workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4130304289 |
|
|
Mar 05 01:43:35 PM PST 24 |
Mar 05 01:43:38 PM PST 24 |
905389806 ps |
| T870 |
/workspace/coverage/default/42.pwrmgr_smoke.3832123593 |
|
|
Mar 05 01:42:47 PM PST 24 |
Mar 05 01:42:48 PM PST 24 |
29297849 ps |
| T871 |
/workspace/coverage/default/29.pwrmgr_wakeup.1172631073 |
|
|
Mar 05 01:40:52 PM PST 24 |
Mar 05 01:40:53 PM PST 24 |
275179904 ps |
| T872 |
/workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.3764127894 |
|
|
Mar 05 01:39:05 PM PST 24 |
Mar 05 01:39:08 PM PST 24 |
72346536 ps |
| T873 |
/workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.405553301 |
|
|
Mar 05 01:39:23 PM PST 24 |
Mar 05 01:39:27 PM PST 24 |
103513058 ps |
| T874 |
/workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.2188558014 |
|
|
Mar 05 01:42:08 PM PST 24 |
Mar 05 01:42:10 PM PST 24 |
297969663 ps |
| T875 |
/workspace/coverage/default/33.pwrmgr_reset_invalid.1111936174 |
|
|
Mar 05 01:41:43 PM PST 24 |
Mar 05 01:41:45 PM PST 24 |
109367974 ps |
| T876 |
/workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.63084839 |
|
|
Mar 05 01:41:45 PM PST 24 |
Mar 05 01:41:47 PM PST 24 |
62796720 ps |
| T877 |
/workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.788583957 |
|
|
Mar 05 01:40:56 PM PST 24 |
Mar 05 01:40:57 PM PST 24 |
414918478 ps |
| T878 |
/workspace/coverage/default/25.pwrmgr_aborted_low_power.988160054 |
|
|
Mar 05 01:40:15 PM PST 24 |
Mar 05 01:40:16 PM PST 24 |
27879488 ps |
| T879 |
/workspace/coverage/default/32.pwrmgr_stress_all.77338324 |
|
|
Mar 05 01:41:28 PM PST 24 |
Mar 05 01:41:34 PM PST 24 |
1514423441 ps |
| T880 |
/workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.319909358 |
|
|
Mar 05 01:38:05 PM PST 24 |
Mar 05 01:38:10 PM PST 24 |
740337631 ps |
| T881 |
/workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.247967535 |
|
|
Mar 05 01:43:34 PM PST 24 |
Mar 05 01:43:34 PM PST 24 |
66853338 ps |
| T882 |
/workspace/coverage/default/26.pwrmgr_stress_all.3481009036 |
|
|
Mar 05 01:40:23 PM PST 24 |
Mar 05 01:40:27 PM PST 24 |
993414830 ps |
| T883 |
/workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.3946586477 |
|
|
Mar 05 01:41:30 PM PST 24 |
Mar 05 01:41:32 PM PST 24 |
244392292 ps |
| T884 |
/workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1209498499 |
|
|
Mar 05 01:41:01 PM PST 24 |
Mar 05 01:41:02 PM PST 24 |
73096084 ps |
| T885 |
/workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2756833253 |
|
|
Mar 05 01:40:48 PM PST 24 |
Mar 05 01:40:51 PM PST 24 |
1009720595 ps |
| T886 |
/workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.1074792285 |
|
|
Mar 05 01:38:47 PM PST 24 |
Mar 05 01:38:48 PM PST 24 |
54675698 ps |
| T887 |
/workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3329160019 |
|
|
Mar 05 01:37:36 PM PST 24 |
Mar 05 01:37:37 PM PST 24 |
115412233 ps |
| T888 |
/workspace/coverage/default/2.pwrmgr_reset_invalid.2319725965 |
|
|
Mar 05 01:36:24 PM PST 24 |
Mar 05 01:36:26 PM PST 24 |
108924271 ps |
| T889 |
/workspace/coverage/default/46.pwrmgr_lowpower_invalid.4271785080 |
|
|
Mar 05 01:43:34 PM PST 24 |
Mar 05 01:43:35 PM PST 24 |
38825611 ps |
| T890 |
/workspace/coverage/default/30.pwrmgr_stress_all.774443150 |
|
|
Mar 05 01:41:08 PM PST 24 |
Mar 05 01:41:10 PM PST 24 |
1073741256 ps |
| T891 |
/workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.1694171269 |
|
|
Mar 05 01:37:59 PM PST 24 |
Mar 05 01:38:00 PM PST 24 |
65831924 ps |
| T892 |
/workspace/coverage/default/20.pwrmgr_aborted_low_power.929557493 |
|
|
Mar 05 01:39:17 PM PST 24 |
Mar 05 01:39:20 PM PST 24 |
31183685 ps |
| T893 |
/workspace/coverage/default/31.pwrmgr_escalation_timeout.3043336349 |
|
|
Mar 05 01:41:06 PM PST 24 |
Mar 05 01:41:07 PM PST 24 |
167360861 ps |
| T894 |
/workspace/coverage/default/8.pwrmgr_glitch.1828319522 |
|
|
Mar 05 01:37:29 PM PST 24 |
Mar 05 01:37:30 PM PST 24 |
62916213 ps |
| T895 |
/workspace/coverage/default/6.pwrmgr_glitch.4289843583 |
|
|
Mar 05 01:37:14 PM PST 24 |
Mar 05 01:37:17 PM PST 24 |
63622411 ps |
| T896 |
/workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1889658551 |
|
|
Mar 05 01:37:15 PM PST 24 |
Mar 05 01:37:17 PM PST 24 |
122751699 ps |
| T897 |
/workspace/coverage/default/9.pwrmgr_aborted_low_power.3506164582 |
|
|
Mar 05 01:37:37 PM PST 24 |
Mar 05 01:37:38 PM PST 24 |
38213353 ps |
| T898 |
/workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2420154471 |
|
|
Mar 05 01:40:49 PM PST 24 |
Mar 05 01:40:50 PM PST 24 |
91826799 ps |
| T899 |
/workspace/coverage/default/27.pwrmgr_wakeup_reset.392656296 |
|
|
Mar 05 01:40:32 PM PST 24 |
Mar 05 01:40:33 PM PST 24 |
187387141 ps |
| T900 |
/workspace/coverage/default/1.pwrmgr_escalation_timeout.3694679095 |
|
|
Mar 05 01:36:10 PM PST 24 |
Mar 05 01:36:11 PM PST 24 |
1521178009 ps |
| T901 |
/workspace/coverage/default/15.pwrmgr_global_esc.1503161898 |
|
|
Mar 05 01:38:41 PM PST 24 |
Mar 05 01:38:41 PM PST 24 |
24812442 ps |
| T902 |
/workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1816897160 |
|
|
Mar 05 01:41:36 PM PST 24 |
Mar 05 01:41:37 PM PST 24 |
49477457 ps |
| T903 |
/workspace/coverage/default/22.pwrmgr_smoke.2332158595 |
|
|
Mar 05 01:39:42 PM PST 24 |
Mar 05 01:39:43 PM PST 24 |
39470572 ps |
| T904 |
/workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1301207723 |
|
|
Mar 05 01:40:56 PM PST 24 |
Mar 05 01:40:57 PM PST 24 |
33166353 ps |
| T905 |
/workspace/coverage/default/16.pwrmgr_reset_invalid.2186661931 |
|
|
Mar 05 01:38:47 PM PST 24 |
Mar 05 01:38:47 PM PST 24 |
174793738 ps |
| T906 |
/workspace/coverage/default/39.pwrmgr_aborted_low_power.1157785103 |
|
|
Mar 05 01:42:21 PM PST 24 |
Mar 05 01:42:22 PM PST 24 |
200661434 ps |
| T907 |
/workspace/coverage/default/34.pwrmgr_wakeup_reset.1557405233 |
|
|
Mar 05 01:41:36 PM PST 24 |
Mar 05 01:41:37 PM PST 24 |
151408268 ps |
| T908 |
/workspace/coverage/default/10.pwrmgr_reset.1270910395 |
|
|
Mar 05 01:37:44 PM PST 24 |
Mar 05 01:37:47 PM PST 24 |
39612103 ps |
| T909 |
/workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3689690631 |
|
|
Mar 05 01:43:49 PM PST 24 |
Mar 05 01:43:49 PM PST 24 |
30096073 ps |
| T910 |
/workspace/coverage/default/10.pwrmgr_wakeup.3429845908 |
|
|
Mar 05 01:37:51 PM PST 24 |
Mar 05 01:37:52 PM PST 24 |
177112901 ps |
| T911 |
/workspace/coverage/default/1.pwrmgr_lowpower_invalid.1788512884 |
|
|
Mar 05 01:36:14 PM PST 24 |
Mar 05 01:36:15 PM PST 24 |
75165554 ps |
| T912 |
/workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.604032185 |
|
|
Mar 05 01:42:22 PM PST 24 |
Mar 05 01:42:23 PM PST 24 |
177558877 ps |
| T913 |
/workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.3551416871 |
|
|
Mar 05 01:43:22 PM PST 24 |
Mar 05 01:43:23 PM PST 24 |
136043826 ps |
| T914 |
/workspace/coverage/default/33.pwrmgr_smoke.2932645705 |
|
|
Mar 05 01:41:28 PM PST 24 |
Mar 05 01:41:29 PM PST 24 |
31376783 ps |
| T915 |
/workspace/coverage/default/45.pwrmgr_reset_invalid.3392002844 |
|
|
Mar 05 01:43:26 PM PST 24 |
Mar 05 01:43:27 PM PST 24 |
126095130 ps |
| T916 |
/workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2542946517 |
|
|
Mar 05 01:41:44 PM PST 24 |
Mar 05 01:41:49 PM PST 24 |
956187643 ps |
| T917 |
/workspace/coverage/default/16.pwrmgr_reset.1742236964 |
|
|
Mar 05 01:38:39 PM PST 24 |
Mar 05 01:38:40 PM PST 24 |
103502916 ps |
| T918 |
/workspace/coverage/default/43.pwrmgr_escalation_timeout.4264504933 |
|
|
Mar 05 01:43:00 PM PST 24 |
Mar 05 01:43:01 PM PST 24 |
190153033 ps |
| T919 |
/workspace/coverage/default/11.pwrmgr_smoke.2344335533 |
|
|
Mar 05 01:37:50 PM PST 24 |
Mar 05 01:37:51 PM PST 24 |
95428643 ps |
| T920 |
/workspace/coverage/default/4.pwrmgr_wakeup.696373346 |
|
|
Mar 05 01:36:45 PM PST 24 |
Mar 05 01:36:46 PM PST 24 |
266008467 ps |
| T921 |
/workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.803596267 |
|
|
Mar 05 01:39:55 PM PST 24 |
Mar 05 01:40:01 PM PST 24 |
2150452286 ps |
| T922 |
/workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.1327369443 |
|
|
Mar 05 01:38:53 PM PST 24 |
Mar 05 01:39:02 PM PST 24 |
2346518287 ps |
| T923 |
/workspace/coverage/default/15.pwrmgr_escalation_timeout.1593855084 |
|
|
Mar 05 01:38:44 PM PST 24 |
Mar 05 01:38:46 PM PST 24 |
643680922 ps |
| T94 |
/workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1557185220 |
|
|
Mar 05 01:37:02 PM PST 24 |
Mar 05 01:37:12 PM PST 24 |
6577626881 ps |
| T924 |
/workspace/coverage/default/21.pwrmgr_reset.48970208 |
|
|
Mar 05 01:39:29 PM PST 24 |
Mar 05 01:39:30 PM PST 24 |
38579050 ps |
| T925 |
/workspace/coverage/default/2.pwrmgr_reset.2013719230 |
|
|
Mar 05 01:36:17 PM PST 24 |
Mar 05 01:36:18 PM PST 24 |
61516582 ps |
| T926 |
/workspace/coverage/default/23.pwrmgr_glitch.3164206426 |
|
|
Mar 05 01:39:58 PM PST 24 |
Mar 05 01:40:04 PM PST 24 |
56324048 ps |
| T927 |
/workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3062163282 |
|
|
Mar 05 01:40:52 PM PST 24 |
Mar 05 01:40:53 PM PST 24 |
28099988 ps |
| T928 |
/workspace/coverage/default/33.pwrmgr_escalation_timeout.3240543256 |
|
|
Mar 05 01:41:30 PM PST 24 |
Mar 05 01:41:31 PM PST 24 |
682094208 ps |
| T929 |
/workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2166221035 |
|
|
Mar 05 01:43:16 PM PST 24 |
Mar 05 01:43:18 PM PST 24 |
66732627 ps |
| T930 |
/workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3391980361 |
|
|
Mar 05 01:42:42 PM PST 24 |
Mar 05 01:42:44 PM PST 24 |
250263960 ps |
| T931 |
/workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1618187816 |
|
|
Mar 05 01:41:49 PM PST 24 |
Mar 05 01:41:50 PM PST 24 |
30333133 ps |
| T932 |
/workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3063584638 |
|
|
Mar 05 01:40:49 PM PST 24 |
Mar 05 01:40:53 PM PST 24 |
972256196 ps |
| T933 |
/workspace/coverage/default/2.pwrmgr_smoke.1229703317 |
|
|
Mar 05 01:36:13 PM PST 24 |
Mar 05 01:36:14 PM PST 24 |
101846001 ps |
| T934 |
/workspace/coverage/default/10.pwrmgr_glitch.3955785604 |
|
|
Mar 05 01:37:50 PM PST 24 |
Mar 05 01:37:52 PM PST 24 |
93005565 ps |
| T935 |
/workspace/coverage/default/32.pwrmgr_reset.3750492110 |
|
|
Mar 05 01:41:10 PM PST 24 |
Mar 05 01:41:11 PM PST 24 |
68919131 ps |
| T936 |
/workspace/coverage/default/4.pwrmgr_smoke.3272546185 |
|
|
Mar 05 01:36:43 PM PST 24 |
Mar 05 01:36:44 PM PST 24 |
80595372 ps |
| T937 |
/workspace/coverage/default/30.pwrmgr_glitch.1572455081 |
|
|
Mar 05 01:40:56 PM PST 24 |
Mar 05 01:40:57 PM PST 24 |
65926397 ps |
| T938 |
/workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.1885349498 |
|
|
Mar 05 01:38:24 PM PST 24 |
Mar 05 01:38:25 PM PST 24 |
155681219 ps |
| T939 |
/workspace/coverage/default/32.pwrmgr_wakeup_reset.747080809 |
|
|
Mar 05 01:41:09 PM PST 24 |
Mar 05 01:41:11 PM PST 24 |
52239184 ps |
| T940 |
/workspace/coverage/default/41.pwrmgr_escalation_timeout.4104366452 |
|
|
Mar 05 01:42:46 PM PST 24 |
Mar 05 01:42:47 PM PST 24 |
167326016 ps |
| T941 |
/workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.455767124 |
|
|
Mar 05 01:40:39 PM PST 24 |
Mar 05 01:40:40 PM PST 24 |
52272498 ps |
| T942 |
/workspace/coverage/default/23.pwrmgr_lowpower_invalid.432715528 |
|
|
Mar 05 01:39:56 PM PST 24 |
Mar 05 01:39:59 PM PST 24 |
52539618 ps |
| T943 |
/workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1485842649 |
|
|
Mar 05 01:35:48 PM PST 24 |
Mar 05 01:35:49 PM PST 24 |
153268357 ps |
| T944 |
/workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2356525703 |
|
|
Mar 05 01:42:05 PM PST 24 |
Mar 05 01:42:10 PM PST 24 |
856978028 ps |
| T945 |
/workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.4094541634 |
|
|
Mar 05 01:43:34 PM PST 24 |
Mar 05 01:43:35 PM PST 24 |
180291178 ps |
| T946 |
/workspace/coverage/default/43.pwrmgr_smoke.842702151 |
|
|
Mar 05 01:42:52 PM PST 24 |
Mar 05 01:42:53 PM PST 24 |
71424115 ps |
| T947 |
/workspace/coverage/default/41.pwrmgr_reset_invalid.544985877 |
|
|
Mar 05 01:42:48 PM PST 24 |
Mar 05 01:42:49 PM PST 24 |
117335672 ps |
| T948 |
/workspace/coverage/default/30.pwrmgr_reset.1333651311 |
|
|
Mar 05 01:40:57 PM PST 24 |
Mar 05 01:40:58 PM PST 24 |
91400603 ps |
| T949 |
/workspace/coverage/default/21.pwrmgr_stress_all.2332899257 |
|
|
Mar 05 01:39:40 PM PST 24 |
Mar 05 01:39:44 PM PST 24 |
2571475507 ps |
| T950 |
/workspace/coverage/default/47.pwrmgr_aborted_low_power.3301706050 |
|
|
Mar 05 01:43:30 PM PST 24 |
Mar 05 01:43:31 PM PST 24 |
60150346 ps |
| T951 |
/workspace/coverage/default/25.pwrmgr_smoke.2411229629 |
|
|
Mar 05 01:40:08 PM PST 24 |
Mar 05 01:40:09 PM PST 24 |
65938096 ps |
| T952 |
/workspace/coverage/default/25.pwrmgr_wakeup_reset.3064968704 |
|
|
Mar 05 01:40:13 PM PST 24 |
Mar 05 01:40:14 PM PST 24 |
900278557 ps |
| T953 |
/workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.464974416 |
|
|
Mar 05 01:39:58 PM PST 24 |
Mar 05 01:40:05 PM PST 24 |
1281524817 ps |
| T954 |
/workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.2516832761 |
|
|
Mar 05 01:36:30 PM PST 24 |
Mar 05 01:36:31 PM PST 24 |
310940541 ps |
| T955 |
/workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.349245941 |
|
|
Mar 05 01:40:19 PM PST 24 |
Mar 05 01:40:22 PM PST 24 |
872096875 ps |
| T956 |
/workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.627586657 |
|
|
Mar 05 01:38:45 PM PST 24 |
Mar 05 01:38:48 PM PST 24 |
940707716 ps |
| T957 |
/workspace/coverage/default/37.pwrmgr_stress_all.1009589153 |
|
|
Mar 05 01:42:08 PM PST 24 |
Mar 05 01:42:12 PM PST 24 |
1517464889 ps |
| T141 |
/workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2853664801 |
|
|
Mar 05 01:38:59 PM PST 24 |
Mar 05 01:39:13 PM PST 24 |
6218780669 ps |
| T159 |
/workspace/coverage/default/29.pwrmgr_aborted_low_power.3786668990 |
|
|
Mar 05 01:40:48 PM PST 24 |
Mar 05 01:40:49 PM PST 24 |
30078575 ps |
| T160 |
/workspace/coverage/default/25.pwrmgr_lowpower_invalid.1140115326 |
|
|
Mar 05 01:40:13 PM PST 24 |
Mar 05 01:40:14 PM PST 24 |
52750789 ps |
| T161 |
/workspace/coverage/default/13.pwrmgr_wakeup_reset.3870819615 |
|
|
Mar 05 01:38:12 PM PST 24 |
Mar 05 01:38:13 PM PST 24 |
95524878 ps |
| T162 |
/workspace/coverage/default/30.pwrmgr_global_esc.471074721 |
|
|
Mar 05 01:40:56 PM PST 24 |
Mar 05 01:40:56 PM PST 24 |
38426484 ps |
| T163 |
/workspace/coverage/default/43.pwrmgr_wakeup_reset.3733306695 |
|
|
Mar 05 01:42:54 PM PST 24 |
Mar 05 01:42:55 PM PST 24 |
277510300 ps |
| T164 |
/workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.563165790 |
|
|
Mar 05 01:42:14 PM PST 24 |
Mar 05 01:42:16 PM PST 24 |
1499760299 ps |
| T165 |
/workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.2991442092 |
|
|
Mar 05 01:40:41 PM PST 24 |
Mar 05 01:40:43 PM PST 24 |
260695650 ps |
| T166 |
/workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.2471677265 |
|
|
Mar 05 01:40:02 PM PST 24 |
Mar 05 01:40:06 PM PST 24 |
64041912 ps |
| T167 |
/workspace/coverage/default/6.pwrmgr_stress_all.1039782398 |
|
|
Mar 05 01:37:10 PM PST 24 |
Mar 05 01:37:15 PM PST 24 |
2212730220 ps |
| T958 |
/workspace/coverage/default/46.pwrmgr_wakeup_reset.324572855 |
|
|
Mar 05 01:43:26 PM PST 24 |
Mar 05 01:43:27 PM PST 24 |
152386689 ps |
| T959 |
/workspace/coverage/default/42.pwrmgr_wakeup.3587732749 |
|
|
Mar 05 01:42:47 PM PST 24 |
Mar 05 01:42:48 PM PST 24 |
232093284 ps |
| T960 |
/workspace/coverage/default/26.pwrmgr_global_esc.2412869981 |
|
|
Mar 05 01:40:20 PM PST 24 |
Mar 05 01:40:21 PM PST 24 |
99599623 ps |
| T961 |
/workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.521035690 |
|
|
Mar 05 01:38:03 PM PST 24 |
Mar 05 01:38:05 PM PST 24 |
166754041 ps |
| T962 |
/workspace/coverage/default/6.pwrmgr_global_esc.330052924 |
|
|
Mar 05 01:37:10 PM PST 24 |
Mar 05 01:37:10 PM PST 24 |
52249578 ps |
| T963 |
/workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1835959105 |
|
|
Mar 05 01:39:41 PM PST 24 |
Mar 05 01:39:44 PM PST 24 |
1440133648 ps |
| T964 |
/workspace/coverage/default/11.pwrmgr_escalation_timeout.1991560750 |
|
|
Mar 05 01:38:02 PM PST 24 |
Mar 05 01:38:03 PM PST 24 |
618221381 ps |
| T965 |
/workspace/coverage/default/7.pwrmgr_escalation_timeout.1407692287 |
|
|
Mar 05 01:37:18 PM PST 24 |
Mar 05 01:37:19 PM PST 24 |
161074472 ps |
| T966 |
/workspace/coverage/default/2.pwrmgr_global_esc.656349318 |
|
|
Mar 05 01:36:24 PM PST 24 |
Mar 05 01:36:25 PM PST 24 |
50755961 ps |
| T967 |
/workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2736405760 |
|
|
Mar 05 01:38:07 PM PST 24 |
Mar 05 01:38:11 PM PST 24 |
112917221 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.189625233 |
|
|
Mar 05 01:23:35 PM PST 24 |
Mar 05 01:23:39 PM PST 24 |
227384750 ps |
| T62 |
/workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1463390896 |
|
|
Mar 05 01:23:58 PM PST 24 |
Mar 05 01:24:00 PM PST 24 |
142954386 ps |
| T63 |
/workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2927527568 |
|
|
Mar 05 01:23:31 PM PST 24 |
Mar 05 01:23:33 PM PST 24 |
71976980 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2659882256 |
|
|
Mar 05 01:23:48 PM PST 24 |
Mar 05 01:23:49 PM PST 24 |
68213791 ps |
| T122 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3574195356 |
|
|
Mar 05 01:23:31 PM PST 24 |
Mar 05 01:23:33 PM PST 24 |
35277099 ps |
| T83 |
/workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2262681141 |
|
|
Mar 05 01:23:34 PM PST 24 |
Mar 05 01:23:36 PM PST 24 |
34175403 ps |
| T66 |
/workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1944339201 |
|
|
Mar 05 01:23:51 PM PST 24 |
Mar 05 01:23:52 PM PST 24 |
22266571 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1698881119 |
|
|
Mar 05 01:23:26 PM PST 24 |
Mar 05 01:23:27 PM PST 24 |
82172951 ps |
| T67 |
/workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.417825234 |
|
|
Mar 05 01:24:06 PM PST 24 |
Mar 05 01:24:07 PM PST 24 |
25996280 ps |
| T68 |
/workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2672894372 |
|
|
Mar 05 01:23:59 PM PST 24 |
Mar 05 01:24:00 PM PST 24 |
38151491 ps |
| T123 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1008369551 |
|
|
Mar 05 01:23:28 PM PST 24 |
Mar 05 01:23:29 PM PST 24 |
25087129 ps |
| T106 |
/workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3964022138 |
|
|
Mar 05 01:23:47 PM PST 24 |
Mar 05 01:23:47 PM PST 24 |
34849457 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2914078052 |
|
|
Mar 05 01:23:27 PM PST 24 |
Mar 05 01:23:28 PM PST 24 |
79394218 ps |
| T185 |
/workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1982670506 |
|
|
Mar 05 01:23:50 PM PST 24 |
Mar 05 01:23:50 PM PST 24 |
117959538 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3533674287 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:34 PM PST 24 |
110436293 ps |
| T186 |
/workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3756672977 |
|
|
Mar 05 01:24:01 PM PST 24 |
Mar 05 01:24:02 PM PST 24 |
36259572 ps |
| T52 |
/workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.4252156268 |
|
|
Mar 05 01:23:28 PM PST 24 |
Mar 05 01:23:30 PM PST 24 |
206525197 ps |
| T108 |
/workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.3126693576 |
|
|
Mar 05 01:23:51 PM PST 24 |
Mar 05 01:23:52 PM PST 24 |
23497352 ps |
| T187 |
/workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3024088867 |
|
|
Mar 05 01:23:55 PM PST 24 |
Mar 05 01:23:56 PM PST 24 |
20039337 ps |
| T53 |
/workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3220341377 |
|
|
Mar 05 01:23:34 PM PST 24 |
Mar 05 01:23:36 PM PST 24 |
53164259 ps |
| T968 |
/workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.3422849570 |
|
|
Mar 05 01:24:09 PM PST 24 |
Mar 05 01:24:10 PM PST 24 |
29007020 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3695966047 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:35 PM PST 24 |
61675453 ps |
| T188 |
/workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.2712166175 |
|
|
Mar 05 01:23:57 PM PST 24 |
Mar 05 01:23:57 PM PST 24 |
30935847 ps |
| T56 |
/workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.4013478740 |
|
|
Mar 05 01:24:02 PM PST 24 |
Mar 05 01:24:05 PM PST 24 |
245091426 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.704859288 |
|
|
Mar 05 01:23:34 PM PST 24 |
Mar 05 01:23:35 PM PST 24 |
55956883 ps |
| T969 |
/workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.970909249 |
|
|
Mar 05 01:23:43 PM PST 24 |
Mar 05 01:23:44 PM PST 24 |
27083070 ps |
| T57 |
/workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2626625080 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:36 PM PST 24 |
393307623 ps |
| T970 |
/workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.1286725339 |
|
|
Mar 05 01:24:10 PM PST 24 |
Mar 05 01:24:11 PM PST 24 |
22576992 ps |
| T110 |
/workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.1068528094 |
|
|
Mar 05 01:24:05 PM PST 24 |
Mar 05 01:24:07 PM PST 24 |
119908849 ps |
| T58 |
/workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.986948974 |
|
|
Mar 05 01:23:30 PM PST 24 |
Mar 05 01:23:33 PM PST 24 |
500054926 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.73999750 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:34 PM PST 24 |
23075220 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.4101278706 |
|
|
Mar 05 01:23:40 PM PST 24 |
Mar 05 01:23:41 PM PST 24 |
41451593 ps |
| T77 |
/workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1596107849 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:35 PM PST 24 |
308501233 ps |
| T111 |
/workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.2086965073 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:35 PM PST 24 |
39624370 ps |
| T72 |
/workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3468039553 |
|
|
Mar 05 01:23:44 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
123774738 ps |
| T175 |
/workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.147711273 |
|
|
Mar 05 01:24:05 PM PST 24 |
Mar 05 01:24:07 PM PST 24 |
490820221 ps |
| T112 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.374046619 |
|
|
Mar 05 01:23:34 PM PST 24 |
Mar 05 01:23:35 PM PST 24 |
32452663 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1530782581 |
|
|
Mar 05 01:23:27 PM PST 24 |
Mar 05 01:23:29 PM PST 24 |
336008826 ps |
| T113 |
/workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2056358336 |
|
|
Mar 05 01:23:47 PM PST 24 |
Mar 05 01:23:49 PM PST 24 |
29422908 ps |
| T70 |
/workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1021074141 |
|
|
Mar 05 01:23:44 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
249970664 ps |
| T972 |
/workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3548651687 |
|
|
Mar 05 01:24:07 PM PST 24 |
Mar 05 01:24:08 PM PST 24 |
95612601 ps |
| T120 |
/workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1956492863 |
|
|
Mar 05 01:23:57 PM PST 24 |
Mar 05 01:23:58 PM PST 24 |
42403558 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1283433170 |
|
|
Mar 05 01:23:40 PM PST 24 |
Mar 05 01:23:41 PM PST 24 |
48967142 ps |
| T114 |
/workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.816610988 |
|
|
Mar 05 01:23:50 PM PST 24 |
Mar 05 01:23:50 PM PST 24 |
35928014 ps |
| T974 |
/workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4289398181 |
|
|
Mar 05 01:23:48 PM PST 24 |
Mar 05 01:23:49 PM PST 24 |
84461853 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3152590746 |
|
|
Mar 05 01:23:43 PM PST 24 |
Mar 05 01:23:44 PM PST 24 |
19560392 ps |
| T176 |
/workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2971317497 |
|
|
Mar 05 01:23:37 PM PST 24 |
Mar 05 01:23:39 PM PST 24 |
616210328 ps |
| T976 |
/workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.570677067 |
|
|
Mar 05 01:23:46 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
127655345 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3065375317 |
|
|
Mar 05 01:23:56 PM PST 24 |
Mar 05 01:23:57 PM PST 24 |
49528845 ps |
| T977 |
/workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1179846037 |
|
|
Mar 05 01:24:02 PM PST 24 |
Mar 05 01:24:03 PM PST 24 |
41610807 ps |
| T73 |
/workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.44412160 |
|
|
Mar 05 01:23:34 PM PST 24 |
Mar 05 01:23:35 PM PST 24 |
56474767 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.4015292724 |
|
|
Mar 05 01:23:26 PM PST 24 |
Mar 05 01:23:29 PM PST 24 |
1271651709 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3255797659 |
|
|
Mar 05 01:23:45 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
102609979 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2110638241 |
|
|
Mar 05 01:23:28 PM PST 24 |
Mar 05 01:23:29 PM PST 24 |
48189153 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1179281869 |
|
|
Mar 05 01:23:27 PM PST 24 |
Mar 05 01:23:29 PM PST 24 |
1109382663 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.473139046 |
|
|
Mar 05 01:23:35 PM PST 24 |
Mar 05 01:23:36 PM PST 24 |
25376200 ps |
| T983 |
/workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.218475759 |
|
|
Mar 05 01:23:39 PM PST 24 |
Mar 05 01:23:40 PM PST 24 |
42682780 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2984152867 |
|
|
Mar 05 01:23:59 PM PST 24 |
Mar 05 01:24:02 PM PST 24 |
315901479 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.995341342 |
|
|
Mar 05 01:23:35 PM PST 24 |
Mar 05 01:23:37 PM PST 24 |
29651547 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3118570777 |
|
|
Mar 05 01:23:32 PM PST 24 |
Mar 05 01:23:33 PM PST 24 |
38585035 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.4177152607 |
|
|
Mar 05 01:23:28 PM PST 24 |
Mar 05 01:23:29 PM PST 24 |
159050669 ps |
| T988 |
/workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.277166331 |
|
|
Mar 05 01:23:45 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
20862458 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3386335901 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:35 PM PST 24 |
74394972 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.135152019 |
|
|
Mar 05 01:23:29 PM PST 24 |
Mar 05 01:23:30 PM PST 24 |
29877452 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1633216641 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:34 PM PST 24 |
105911633 ps |
| T992 |
/workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3186521240 |
|
|
Mar 05 01:23:36 PM PST 24 |
Mar 05 01:23:39 PM PST 24 |
167121236 ps |
| T78 |
/workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1829429545 |
|
|
Mar 05 01:23:28 PM PST 24 |
Mar 05 01:23:29 PM PST 24 |
215568436 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1607151193 |
|
|
Mar 05 01:23:42 PM PST 24 |
Mar 05 01:23:43 PM PST 24 |
584909989 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.4190227483 |
|
|
Mar 05 01:23:41 PM PST 24 |
Mar 05 01:23:43 PM PST 24 |
38598179 ps |
| T995 |
/workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.4164035487 |
|
|
Mar 05 01:23:44 PM PST 24 |
Mar 05 01:23:47 PM PST 24 |
35928276 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1917629111 |
|
|
Mar 05 01:23:45 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
77059124 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2356186233 |
|
|
Mar 05 01:23:33 PM PST 24 |
Mar 05 01:23:34 PM PST 24 |
34219352 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.259915055 |
|
|
Mar 05 01:23:59 PM PST 24 |
Mar 05 01:24:00 PM PST 24 |
21546383 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.148485376 |
|
|
Mar 05 01:23:34 PM PST 24 |
Mar 05 01:23:36 PM PST 24 |
81215054 ps |
| T1000 |
/workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2736808888 |
|
|
Mar 05 01:23:46 PM PST 24 |
Mar 05 01:23:48 PM PST 24 |
243637240 ps |
| T1001 |
/workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.1518446826 |
|
|
Mar 05 01:23:59 PM PST 24 |
Mar 05 01:24:00 PM PST 24 |
16920446 ps |
| T1002 |
/workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.2373363069 |
|
|
Mar 05 01:23:57 PM PST 24 |
Mar 05 01:23:57 PM PST 24 |
42817553 ps |
| T1003 |
/workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2206014681 |
|
|
Mar 05 01:23:45 PM PST 24 |
Mar 05 01:23:47 PM PST 24 |
201015566 ps |
| T1004 |
/workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.4274228957 |
|
|
Mar 05 01:24:02 PM PST 24 |
Mar 05 01:24:03 PM PST 24 |
43636648 ps |
| T1005 |
/workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1171137755 |
|
|
Mar 05 01:23:41 PM PST 24 |
Mar 05 01:23:43 PM PST 24 |
112145379 ps |
| T1006 |
/workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2829107447 |
|
|
Mar 05 01:23:30 PM PST 24 |
Mar 05 01:23:31 PM PST 24 |
54916571 ps |