Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22815

1

T1

10

T2

3

T3

2

auto[1]

21888

1

T1

10

T2

3

T4

6

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22848

1

T1

4

T2

3

T3

2

auto[1]

21855

1

T1

16

T2

3

T4

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21876

1

T1

10

T2

4

T4

4

auto[1]

22827

1

T1

10

T2

2

T3

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25541

1

T1

10

T2

4

T3

1

auto[1]

19162

1

T1

10

T2

2

T3

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21526

1

T1

10

T2

3

T4

4

auto[1]

23177

1

T1

10

T2

3

T3

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23054

1

T1

10

T2

5

T3

2

auto[1]

21649

1

T1

10

T2

1

T4

2

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

763

1

T8

1

T42

1

T43

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

563

1

T42

1

T43

1

T14

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

838

1

T8

1

T42

1

T43

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

624

1

T8

1

T42

1

T43

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

775

1

T1

1

T8

3

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

581

1

T1

1

T10

1

T42

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1231

1

T3

1

T7

1

T8

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1019

1

T3

1

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

788

1

T7

1

T9

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

564

1

T7

1

T10

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

729

1

T6

1

T8

2

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

545

1

T6

1

T8

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

812

1

T6

2

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

611

1

T6

2

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

790

1

T6

1

T7

1

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

603

1

T6

1

T7

1

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

791

1

T1

1

T2

1

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

596

1

T1

1

T2

1

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

802

1

T10

2

T43

1

T14

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

573

1

T10

2

T43

1

T14

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

771

1

T6

3

T8

1

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

583

1

T6

3

T10

1

T14

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

849

1

T8

2

T10

1

T42

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

640

1

T8

1

T10

1

T42

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

757

1

T6

1

T7

2

T8

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

550

1

T6

1

T7

2

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

775

1

T1

2

T7

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

591

1

T1

2

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

745

1

T1

1

T8

5

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

545

1

T1

1

T10

2

T14

12

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

804

1

T2

1

T6

2

T8

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

607

1

T6

2

T42

2

T14

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

764

1

T8

3

T14

11

T39

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

574

1

T8

2

T14

9

T39

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

802

1

T2

1

T8

1

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

611

1

T10

4

T43

1

T14

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

811

1

T1

1

T2

1

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

623

1

T1

1

T2

1

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

783

1

T7

1

T8

5

T10

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

608

1

T7

1

T10

3

T42

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

735

1

T6

2

T8

1

T10

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

553

1

T6

2

T10

2

T43

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

770

1

T7

1

T8

2

T14

14

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

570

1

T7

1

T8

1

T14

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

839

1

T42

3

T14

7

T26

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

615

1

T42

3

T14

6

T26

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

771

1

T7

1

T8

1

T10

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

583

1

T7

1

T10

4

T43

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

814

1

T8

2

T10

5

T43

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

586

1

T8

1

T10

5

T43

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

751

1

T1

1

T4

1

T8

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

568

1

T1

1

T4

1

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

794

1

T8

2

T10

1

T42

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

589

1

T10

1

T42

1

T14

12

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

799

1

T1

1

T7

1

T8

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

578

1

T1

1

T7

1

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

764

1

T1

1

T4

1

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

581

1

T1

1

T4

1

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

713

1

T8

1

T10

2

T14

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

521

1

T10

2

T14

4

T26

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

816

1

T7

1

T8

3

T10

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

623

1

T7

1

T8

1

T10

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

795

1

T1

1

T8

2

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

584

1

T1

1

T8

1

T10

1