Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	477577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239753

1

T1

252

T2

120

T3

103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	461711	1			T1	534		T2	200		T3	175
values[0x0]	127616	1			T1	233		T2	78		T3	54
values[0x1]	128003	1			T1	219		T2	93		T3	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	378290	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

339040

1

T1

399

T2

164

T3

144

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2238	1			T1	4		T2	4		T6	1
valid_sources[0x01]	2139	1			T1	3		T2	2		T3	1
valid_sources[0x02]	2298	1			T1	1		T2	1		T3	2
valid_sources[0x03]	2384	1			T1	4		T2	1		T3	1
valid_sources[0x04]	2202	1			T1	2		T2	1		T5	5
valid_sources[0x05]	2193	1			T1	2		T2	2		T9	1
valid_sources[0x06]	2238	1			T1	6		T2	3		T3	3
valid_sources[0x07]	2284	1			T1	3		T2	4		T6	1
valid_sources[0x08]	2281	1			T1	7		T2	2		T3	1
valid_sources[0x09]	2123	1			T1	7		T2	2		T3	2
valid_sources[0x0a]	2366	1			T1	4		T2	4		T5	27
valid_sources[0x0b]	2778	1			T1	5		T2	2		T6	2
valid_sources[0x0c]	8156	1			T1	4		T2	2		T15	2
valid_sources[0x0d]	2649	1			T1	4		T3	2		T6	2
valid_sources[0x0e]	3618	1			T1	5		T2	1		T6	1
valid_sources[0x0f]	2345	1			T1	3		T39	1		T66	1
valid_sources[0x10]	2958	1			T1	4		T2	2		T3	1
valid_sources[0x11]	2220	1			T1	4		T2	2		T15	1
valid_sources[0x12]	2250	1			T1	3		T2	1		T15	2
valid_sources[0x13]	2410	1			T1	5		T2	4		T5	12
valid_sources[0x14]	2160	1			T1	2		T3	4		T15	1
valid_sources[0x15]	2167	1			T1	4		T2	1		T3	2
valid_sources[0x16]	2225	1			T1	4		T2	2		T3	1
valid_sources[0x17]	2253	1			T1	3		T3	1		T161	4
valid_sources[0x18]	4053	1			T1	2		T2	1		T3	2
valid_sources[0x19]	2514	1			T1	5		T2	3		T3	3
valid_sources[0x1a]	2145	1			T1	5		T2	1		T3	1
valid_sources[0x1b]	5132	1			T1	2		T2	2		T6	2
valid_sources[0x1c]	4233	1			T1	3		T9	1		T39	1
valid_sources[0x1d]	2454	1			T1	3		T3	1		T6	2
valid_sources[0x1e]	2278	1			T1	2		T3	2		T39	1
valid_sources[0x1f]	2264	1			T1	4		T6	1		T39	1
valid_sources[0x20]	2547	1			T1	2		T4	1		T5	29
valid_sources[0x21]	4863	1			T1	6		T3	2		T6	2
valid_sources[0x22]	2608	1			T1	5		T5	1		T6	3
valid_sources[0x23]	2688	1			T1	4		T2	1		T3	1
valid_sources[0x24]	2232	1			T1	5		T2	2		T5	5
valid_sources[0x25]	2303	1			T1	5		T3	2		T6	1
valid_sources[0x26]	2604	1			T1	1		T2	1		T6	1
valid_sources[0x27]	2222	1			T1	7		T2	2		T3	1
valid_sources[0x28]	6207	1			T1	7		T2	1		T6	1
valid_sources[0x29]	2178	1			T1	2		T2	3		T3	1
valid_sources[0x2a]	2388	1			T1	4		T2	1		T3	5
valid_sources[0x2b]	2552	1			T1	2		T39	2		T14	2
valid_sources[0x2c]	3492	1			T1	3		T5	6		T9	1
valid_sources[0x2d]	2256	1			T1	2		T2	3		T15	1
valid_sources[0x2e]	2532	1			T1	2		T2	1		T6	1
valid_sources[0x2f]	2400	1			T1	3		T2	2		T3	2
valid_sources[0x30]	8178	1			T1	3		T2	4		T3	3
valid_sources[0x31]	2371	1			T1	2		T2	2		T3	3
valid_sources[0x32]	2156	1			T1	3		T2	4		T3	1
valid_sources[0x33]	2250	1			T1	3		T2	1		T3	1
valid_sources[0x34]	2460	1			T1	6		T3	3		T6	2
valid_sources[0x35]	2273	1			T1	7		T3	1		T6	1
valid_sources[0x36]	2447	1			T1	3		T2	4		T15	2
valid_sources[0x37]	3152	1			T1	3		T2	2		T6	3
valid_sources[0x38]	5139	1			T1	5		T3	1		T15	1
valid_sources[0x39]	2253	1			T1	3		T5	6		T66	2
valid_sources[0x3a]	2226	1			T1	9		T2	3		T3	1
valid_sources[0x3b]	3208	1			T1	2		T3	2		T15	2
valid_sources[0x3c]	3571	1			T2	1		T3	2		T6	3
valid_sources[0x3d]	2181	1			T1	4		T2	3		T39	3
valid_sources[0x3e]	3559	1			T1	5		T2	1		T3	2
valid_sources[0x3f]	2189	1			T1	2		T2	1		T3	1
valid_sources[0x40]	2084	1			T1	3		T2	1		T3	6
valid_sources[0x41]	2173	1			T1	3		T3	1		T9	2
valid_sources[0x42]	3079	1			T1	3		T3	1		T4	2
valid_sources[0x43]	2351	1			T1	3		T2	1		T3	1
valid_sources[0x44]	2557	1			T1	4		T3	1		T6	1
valid_sources[0x45]	2385	1			T1	4		T2	3		T3	3
valid_sources[0x46]	2269	1			T1	3		T6	1		T15	1
valid_sources[0x47]	2327	1			T1	4		T6	2		T14	1
valid_sources[0x48]	2321	1			T1	4		T2	1		T3	4
valid_sources[0x49]	2193	1			T1	6		T2	1		T3	2
valid_sources[0x4a]	2336	1			T1	2		T2	2		T3	2
valid_sources[0x4b]	2468	1			T1	3		T2	2		T39	4
valid_sources[0x4c]	2209	1			T1	2		T2	2		T6	4
valid_sources[0x4d]	2385	1			T1	9		T3	4		T4	1
valid_sources[0x4e]	2478	1			T1	2		T2	7		T3	1
valid_sources[0x4f]	2331	1			T1	2		T2	3		T3	1
valid_sources[0x50]	2670	1			T1	5		T39	3		T14	2
valid_sources[0x51]	2396	1			T1	2		T2	1		T6	5
valid_sources[0x52]	2149	1			T1	4		T3	3		T14	1
valid_sources[0x53]	2824	1			T1	4		T2	7		T3	1
valid_sources[0x54]	2212	1			T1	6		T2	3		T4	1
valid_sources[0x55]	6387	1			T1	2		T4	1		T39	1
valid_sources[0x56]	3039	1			T1	4		T3	3		T6	1
valid_sources[0x57]	2180	1			T1	2		T2	6		T3	1
valid_sources[0x58]	2531	1			T1	3		T4	1		T6	1
valid_sources[0x59]	2573	1			T1	4		T3	4		T39	4
valid_sources[0x5a]	2193	1			T1	2		T3	1		T6	1
valid_sources[0x5b]	2258	1			T2	3		T6	1		T39	2
valid_sources[0x5c]	2585	1			T1	6		T2	1		T6	2
valid_sources[0x5d]	2496	1			T1	2		T2	1		T3	1
valid_sources[0x5e]	2349	1			T1	5		T2	1		T3	1
valid_sources[0x5f]	2239	1			T1	5		T2	1		T3	3
valid_sources[0x60]	2457	1			T1	4		T3	1		T4	1
valid_sources[0x61]	2655	1			T1	3		T3	1		T15	1
valid_sources[0x62]	2172	1			T1	2		T3	1		T5	11
valid_sources[0x63]	2359	1			T1	2		T2	3		T3	3
valid_sources[0x64]	2118	1			T1	5		T2	2		T3	4
valid_sources[0x65]	2168	1			T1	5		T2	3		T3	1
valid_sources[0x66]	2317	1			T1	3		T2	6		T3	2
valid_sources[0x67]	2235	1			T1	7		T3	1		T15	2
valid_sources[0x68]	2381	1			T1	4		T2	1		T3	1
valid_sources[0x69]	2566	1			T1	5		T3	1		T9	4
valid_sources[0x6a]	3712	1			T1	4		T2	5		T3	1
valid_sources[0x6b]	2427	1			T1	2		T6	2		T39	2
valid_sources[0x6c]	2125	1			T2	2		T3	1		T66	1
valid_sources[0x6d]	2342	1			T1	6		T2	3		T3	4
valid_sources[0x6e]	2460	1			T1	5		T3	1		T4	1
valid_sources[0x6f]	2127	1			T1	2		T2	3		T3	1
valid_sources[0x70]	2293	1			T1	7		T5	8		T15	1
valid_sources[0x71]	2339	1			T1	6		T2	3		T3	1
valid_sources[0x72]	2438	1			T1	3		T2	2		T3	2
valid_sources[0x73]	6055	1			T1	4		T2	1		T4	1
valid_sources[0x74]	2240	1			T1	4		T3	1		T39	2
valid_sources[0x75]	2088	1			T1	6		T2	2		T3	1
valid_sources[0x76]	3268	1			T1	4		T2	1		T4	2
valid_sources[0x77]	2160	1			T1	5		T2	1		T15	1
valid_sources[0x78]	2420	1			T1	9		T2	1		T3	1
valid_sources[0x79]	2359	1			T1	1		T2	1		T3	1
valid_sources[0x7a]	2135	1			T1	1		T2	2		T3	1
valid_sources[0x7b]	2899	1			T1	3		T2	2		T3	2
valid_sources[0x7c]	2122	1			T4	2		T39	1		T66	1
valid_sources[0x7d]	3145	1			T1	1		T3	5		T15	1
valid_sources[0x7e]	2101	1			T1	3		T3	1		T6	1
valid_sources[0x7f]	2404	1			T1	3		T3	1		T5	12
valid_sources[0x80]	8929	1			T1	5		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

164674

1

T1

146

T2

68

T3

67

values[0x0]

all_enables

biggest_size

48276

1

T1

75

T2

29

T3

22

values[0x1]

all_enables

biggest_size

26803

1

T1

31

T2

23

T3

14