SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34876 | 1 | T1 | 281 | T82 | 306 | T142 | 399 | ||||
others[1] | 34990 | 1 | T1 | 315 | T8 | 2 | T27 | 1 | ||||
others[2] | 35156 | 1 | T1 | 315 | T8 | 1 | T27 | 1 | ||||
others[3] | 58433 | 1 | T1 | 496 | T27 | 1 | T41 | 1 | ||||
false | 14767 | 1 | T1 | 50 | T5 | 38 | T8 | 1 | ||||
true | 23382 | 1 | T1 | 52 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34976 | 1 | T1 | 300 | T82 | 313 | T142 | 423 | ||||
others[1] | 35008 | 1 | T1 | 301 | T41 | 1 | T82 | 312 | ||||
others[2] | 35209 | 1 | T1 | 295 | T8 | 1 | T82 | 269 | ||||
others[3] | 58263 | 1 | T1 | 498 | T8 | 1 | T41 | 1 | ||||
false | 9983 | 1 | T1 | 50 | T5 | 19 | T8 | 2 | ||||
true | 18663 | 1 | T1 | 52 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 571 | 1 | T6 | 7 | T161 | 3 | T66 | 5 | ||||
others[1] | 604 | 1 | T5 | 1 | T6 | 5 | T14 | 1 | ||||
others[2] | 578 | 1 | T6 | 4 | T161 | 7 | T66 | 7 | ||||
others[3] | 970 | 1 | T6 | 12 | T8 | 2 | T14 | 1 | ||||
false | 10778 | 1 | T1 | 2 | T2 | 1 | T3 | 1 | ||||
true | 3061 | 1 | T8 | 1 | T14 | 8 | T161 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |