Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T39,T17

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	19585473	4908	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	19585473	214419	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	19585473	7912802	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	19585473	214414	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	19585473	4908	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	19585473	214419	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	19585473	7912802	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	19585473	214414	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	4908	0	0
T1	22991	18	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	9	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	1	0	0
T10	1161	1	0	0
T17	0	9	0	0
T24	0	29	0	0
T25	0	41	0	0
T39	0	3	0	0
T40	0	1	0	0
T82	0	21	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	214419	0	0
T1	22991	398	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	378	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	11	0	0
T10	1161	14	0	0
T17	0	241	0	0
T24	0	1664	0	0
T25	0	1582	0	0
T39	0	316	0	0
T40	0	103	0	0
T82	0	601	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	7912802	0	0
T1	22991	10102	0	0
T2	7507	4035	0	0
T3	13232	5488	0	0
T4	2528	1109	0	0
T5	19763	8338	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	1674	0	0
T10	1161	895	0	0
T15	0	1006	0	0
T39	0	4144	0	0
T83	0	143	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	214414	0	0
T1	22991	398	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	380	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	11	0	0
T10	1161	14	0	0
T17	0	241	0	0
T24	0	1667	0	0
T25	0	1578	0	0
T39	0	316	0	0
T40	0	103	0	0
T82	0	601	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	4908	0	0
T1	22991	18	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	9	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	1	0	0
T10	1161	1	0	0
T17	0	9	0	0
T24	0	29	0	0
T25	0	41	0	0
T39	0	3	0	0
T40	0	1	0	0
T82	0	21	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	214419	0	0
T1	22991	398	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	378	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	11	0	0
T10	1161	14	0	0
T17	0	241	0	0
T24	0	1664	0	0
T25	0	1582	0	0
T39	0	316	0	0
T40	0	103	0	0
T82	0	601	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	7912802	0	0
T1	22991	10102	0	0
T2	7507	4035	0	0
T3	13232	5488	0	0
T4	2528	1109	0	0
T5	19763	8338	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	1674	0	0
T10	1161	895	0	0
T15	0	1006	0	0
T39	0	4144	0	0
T83	0	143	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	214414	0	0
T1	22991	398	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	380	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	11	0	0
T10	1161	14	0	0
T17	0	241	0	0
T24	0	1667	0	0
T25	0	1578	0	0
T39	0	316	0	0
T40	0	103	0	0
T82	0	601	0	0