Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	20183403	14684	0	0
intr_enable_rd_A	20183403	21121	0	0
reset_en_rd_A	20183403	1868	0	0
reset_en_regwen_rd_A	20183403	1354	0	0
wake_info_capture_dis_rd_A	20183403	1412	0	0
wakeup_en_rd_A	20183403	2759	0	0
wakeup_en_regwen_rd_A	20183403	1416	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20183403	14684	0	0
T24	257459	17	0	0
T25	168337	43	0	0
T26	0	117	0	0
T46	1727	0	0	0
T47	2091	0	0	0
T48	5699	0	0	0
T49	3123	0	0	0
T57	0	25	0	0
T58	0	14	0	0
T82	25510	0	0	0
T84	0	15	0	0
T85	0	95	0	0
T100	0	3	0	0
T123	0	28	0	0
T124	0	4	0	0
T125	15507	0	0	0
T126	15683	0	0	0
T127	5840	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20183403	21121	0	0
T3	13232	11	0	0
T4	2528	26	0	0
T5	19763	0	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	0	0	0
T9	2655	10	0	0
T10	1161	0	0	0
T11	1011	0	0	0
T12	15042	0	0	0
T16	0	56	0	0
T46	0	21	0	0
T48	0	17	0	0
T66	0	65	0	0
T91	0	173	0	0
T128	0	70	0	0
T129	0	24	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20183403	1868	0	0
T59	0	114	0	0
T64	0	7	0	0
T68	0	9	0	0
T69	0	6	0	0
T71	0	20	0	0
T118	0	13	0	0
T119	0	26	0	0
T124	130022	1	0	0
T130	0	6	0	0
T131	0	18	0	0
T132	11780	0	0	0
T133	2897	0	0	0
T134	3413	0	0	0
T135	970	0	0	0
T136	3342	0	0	0
T137	19067	0	0	0
T138	6883	0	0	0
T139	3002	0	0	0
T140	1812	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20183403	1354	0	0
T59	0	69	0	0
T64	0	16	0	0
T68	0	45	0	0
T69	0	7	0	0
T71	0	14	0	0
T118	0	7	0	0
T119	0	21	0	0
T124	130022	1	0	0
T130	0	10	0	0
T131	0	3	0	0
T132	11780	0	0	0
T133	2897	0	0	0
T134	3413	0	0	0
T135	970	0	0	0
T136	3342	0	0	0
T137	19067	0	0	0
T138	6883	0	0	0
T139	3002	0	0	0
T140	1812	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20183403	1412	0	0
T58	452108	4	0	0
T59	0	85	0	0
T64	0	19	0	0
T68	0	18	0	0
T98	0	5	0	0
T118	0	8	0	0
T119	0	23	0	0
T124	130022	2	0	0
T130	0	10	0	0
T131	0	11	0	0
T132	11780	0	0	0
T133	2897	0	0	0
T134	3413	0	0	0
T135	970	0	0	0
T136	3342	0	0	0
T137	19067	0	0	0
T138	6883	0	0	0
T139	3002	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20183403	2759	0	0
T58	452108	8	0	0
T59	0	288	0	0
T61	0	283	0	0
T64	0	4	0	0
T68	0	21	0	0
T69	0	2	0	0
T71	0	11	0	0
T118	0	21	0	0
T119	0	13	0	0
T124	130022	0	0	0
T130	0	10	0	0
T132	11780	0	0	0
T133	2897	0	0	0
T134	3413	0	0	0
T135	970	0	0	0
T136	3342	0	0	0
T137	19067	0	0	0
T138	6883	0	0	0
T139	3002	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20183403	1416	0	0
T58	452108	5	0	0
T59	0	82	0	0
T64	0	13	0	0
T68	0	31	0	0
T71	0	6	0	0
T118	0	5	0	0
T119	0	47	0	0
T124	130022	9	0	0
T130	0	4	0	0
T132	11780	0	0	0
T133	2897	0	0	0
T134	3413	0	0	0
T135	970	0	0	0
T136	3342	0	0	0
T137	19067	0	0	0
T138	6883	0	0	0
T139	3002	0	0	0
T141	0	6	0	0