Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	19585473	41110	0	0
IoStatusRise_A	19585473	45761	0	0
MainStatusFall_A	19585473	41110	0	0
MainStatusRise_A	19585473	45762	0	0
UsbStatusFall_A	19585473	31404	0	0
UsbStatusRise_A	19585473	35309	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	41110	0	0
T1	22991	85	0	0
T2	7507	18	0	0
T3	13232	12	0	0
T4	2528	4	0	0
T5	19763	49	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	5	0	0
T9	2655	2	0	0
T10	1161	2	0	0
T11	0	1	0	0
T12	0	2	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	45761	0	0
T1	22991	87	0	0
T2	7507	19	0	0
T3	13232	13	0	0
T4	2528	5	0	0
T5	19763	55	0	0
T6	6227	1	0	0
T7	1437	5	0	0
T8	2214	6	0	0
T9	2655	3	0	0
T10	1161	3	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	41110	0	0
T1	22991	85	0	0
T2	7507	18	0	0
T3	13232	12	0	0
T4	2528	4	0	0
T5	19763	49	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	5	0	0
T9	2655	2	0	0
T10	1161	2	0	0
T11	0	1	0	0
T12	0	2	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	45762	0	0
T1	22991	87	0	0
T2	7507	19	0	0
T3	13232	13	0	0
T4	2528	5	0	0
T5	19763	55	0	0
T6	6227	1	0	0
T7	1437	5	0	0
T8	2214	6	0	0
T9	2655	3	0	0
T10	1161	3	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	31404	0	0
T1	22991	62	0	0
T2	7507	12	0	0
T3	13232	8	0	0
T4	2528	3	0	0
T5	19763	28	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	5	0	0
T9	2655	2	0	0
T10	1161	2	0	0
T11	0	1	0	0
T12	0	2	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	35309	0	0
T1	22991	64	0	0
T2	7507	13	0	0
T3	13232	8	0	0
T4	2528	3	0	0
T5	19763	33	0	0
T6	6227	1	0	0
T7	1437	5	0	0
T8	2214	6	0	0
T9	2655	3	0	0
T10	1161	3	0	0