Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	19585473	45367	0	0
RomAllowCheckGoodState_A	19585473	45419	0	0
RomBlockActiveState_A	19585473	26361	0	0
RomBlockCheckGoodState_A	19585473	375539	0	0
RomIntgChkDisFalse_A	19585473	19053943	0	0
RomIntgChkDisTrue_A	19585473	112199	0	0
RstreqChkEsctimeout_A	19585473	3426	0	0
RstreqChkFsmterm_A	19585473	180	0	0
RstreqChkGlbesc_A	19585473	3426	0	0
RstreqChkMainpd_A	19585473	821161	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	45367	0	0
T1	22991	87	0	0
T2	7507	19	0	0
T3	13232	13	0	0
T4	2528	5	0	0
T5	19763	55	0	0
T6	6227	1	0	0
T7	1437	5	0	0
T8	2214	6	0	0
T9	2655	3	0	0
T10	1161	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	45419	0	0
T1	22991	87	0	0
T2	7507	19	0	0
T3	13232	13	0	0
T4	2528	5	0	0
T5	19763	55	0	0
T6	6227	1	0	0
T7	1437	5	0	0
T8	2214	6	0	0
T9	2655	3	0	0
T10	1161	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	26361	0	0
T8	2214	292	0	0
T9	2655	0	0	0
T10	1161	0	0	0
T11	1011	0	0	0
T12	15042	0	0	0
T15	1842	0	0	0
T18	3864	0	0	0
T23	1323	0	0	0
T27	0	1247	0	0
T39	11030	0	0	0
T41	0	440	0	0
T48	0	1353	0	0
T83	1358	0	0	0
T91	0	17	0	0
T92	0	13	0	0
T142	0	4	0	0
T143	0	159	0	0
T144	0	238	0	0
T145	0	734	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	375539	0	0
T1	22991	1313	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	436	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	54	0	0
T9	2655	0	0	0
T10	1161	0	0	0
T17	0	458	0	0
T24	0	1215	0	0
T25	0	2045	0	0
T27	0	641	0	0
T39	0	205	0	0
T40	0	92	0	0
T41	0	342	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	19053943	0	0
T1	22991	22787	0	0
T2	7507	7419	0	0
T3	13232	13152	0	0
T4	2528	2473	0	0
T5	19763	19267	0	0
T6	6227	6128	0	0
T7	1437	1074	0	0
T8	2214	1938	0	0
T9	2655	2572	0	0
T10	1161	1095	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	112199	0	0
T1	22991	95	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	0	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	211	0	0
T9	2655	0	0	0
T10	1161	0	0	0
T27	0	1452	0	0
T41	0	555	0	0
T48	0	616	0	0
T82	0	375	0	0
T91	0	603	0	0
T95	0	716	0	0
T143	0	1345	0	0
T144	0	37	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	3426	0	0
T5	19763	2	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	1	0	0
T9	2655	0	0	0
T10	1161	0	0	0
T11	1011	1	0	0
T12	15042	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	1842	0	0	0
T18	3864	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	180	0	0
T20	22480	20	0	0
T21	0	40	0	0
T22	0	40	0	0
T28	0	40	0	0
T29	0	40	0	0
T30	2445	0	0	0
T31	4791	0	0	0
T32	1479	0	0	0
T33	1692	0	0	0
T34	86152	0	0	0
T35	553	0	0	0
T36	30257	0	0	0
T37	65644	0	0	0
T38	1884	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	3426	0	0
T5	19763	2	0	0
T6	6227	0	0	0
T7	1437	0	0	0
T8	2214	1	0	0
T9	2655	0	0	0
T10	1161	0	0	0
T11	1011	1	0	0
T12	15042	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	1842	0	0	0
T18	3864	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19585473	821161	0	0
T1	22991	1505	0	0
T2	7507	0	0	0
T3	13232	0	0	0
T4	2528	0	0	0
T5	19763	1009	0	0
T6	6227	0	0	0
T7	1437	22	0	0
T8	2214	43	0	0
T9	2655	0	0	0
T10	1161	0	0	0
T14	0	43	0	0
T18	0	22	0	0
T19	0	11	0	0
T23	0	23	0	0
T39	0	462	0	0
T40	0	415	0	0