Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

60628

1

T1

215

T2

41

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	105057	1			T1	405		T2	58		T3	4
values[0x0]	50507	1			T1	214		T2	19		T3	10
values[0x1]	50922	1			T1	238		T2	14		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	114595	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

91891

1

T1

357

T2

45

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1502	1			T1	857		T7	5		T9	1
valid_sources[0x01]	675	1			T7	1		T9	2		T11	2
valid_sources[0x02]	663	1			T2	2		T9	1		T28	5
valid_sources[0x03]	698	1			T9	3		T27	2		T28	2
valid_sources[0x04]	1256	1			T2	2		T7	2		T27	2
valid_sources[0x05]	757	1			T9	2		T11	3		T28	3
valid_sources[0x06]	783	1			T7	4		T9	3		T11	2
valid_sources[0x07]	953	1			T7	1		T9	2		T27	3
valid_sources[0x08]	509	1			T9	1		T11	8		T27	5
valid_sources[0x09]	607	1			T9	1		T27	3		T28	5
valid_sources[0x0a]	916	1			T9	1		T11	1		T28	2
valid_sources[0x0b]	619	1			T11	2		T27	9		T28	4
valid_sources[0x0c]	603	1			T7	1		T9	2		T11	1
valid_sources[0x0d]	1117	1			T9	1		T11	3		T28	4
valid_sources[0x0e]	657	1			T2	1		T7	1		T9	1
valid_sources[0x0f]	875	1			T9	2		T11	5		T27	7
valid_sources[0x10]	536	1			T9	4		T27	3		T28	5
valid_sources[0x11]	609	1			T13	1		T27	3		T28	4
valid_sources[0x12]	539	1			T7	2		T9	1		T27	2
valid_sources[0x13]	580	1			T27	8		T28	3		T29	4
valid_sources[0x14]	556	1			T2	1		T11	1		T28	4
valid_sources[0x15]	997	1			T27	6		T28	5		T41	3
valid_sources[0x16]	595	1			T27	3		T28	2		T41	3
valid_sources[0x17]	566	1			T7	5		T9	2		T11	7
valid_sources[0x18]	581	1			T3	1		T7	1		T28	4
valid_sources[0x19]	914	1			T7	1		T9	3		T11	1
valid_sources[0x1a]	669	1			T8	6		T9	1		T11	2
valid_sources[0x1b]	659	1			T27	10		T28	3		T41	3
valid_sources[0x1c]	532	1			T3	2		T9	1		T27	6
valid_sources[0x1d]	721	1			T2	1		T9	1		T11	2
valid_sources[0x1e]	1693	1			T2	2		T9	1		T28	4
valid_sources[0x1f]	564	1			T7	2		T9	1		T28	1
valid_sources[0x20]	682	1			T27	2		T28	5		T14	1
valid_sources[0x21]	2321	1			T9	1		T27	14		T28	3
valid_sources[0x22]	583	1			T2	1		T7	1		T9	1
valid_sources[0x23]	774	1			T2	1		T3	1		T27	7
valid_sources[0x24]	499	1			T7	1		T11	1		T28	3
valid_sources[0x25]	1432	1			T9	1		T11	1		T27	11
valid_sources[0x26]	663	1			T7	2		T27	5		T28	4
valid_sources[0x27]	1815	1			T3	1		T9	4		T27	4
valid_sources[0x28]	722	1			T8	1		T9	2		T28	4
valid_sources[0x29]	512	1			T11	2		T27	1		T28	2
valid_sources[0x2a]	1592	1			T2	1		T9	1		T27	3
valid_sources[0x2b]	956	1			T2	1		T7	1		T11	1
valid_sources[0x2c]	736	1			T9	4		T11	3		T27	5
valid_sources[0x2d]	639	1			T9	1		T27	9		T28	3
valid_sources[0x2e]	629	1			T7	1		T8	10		T9	1
valid_sources[0x2f]	625	1			T7	2		T9	2		T11	3
valid_sources[0x30]	622	1			T9	1		T27	1		T28	5
valid_sources[0x31]	773	1			T27	6		T28	8		T41	4
valid_sources[0x32]	819	1			T28	5		T41	6		T42	1
valid_sources[0x33]	749	1			T7	2		T27	1		T28	1
valid_sources[0x34]	774	1			T9	2		T27	3		T28	3
valid_sources[0x35]	1801	1			T7	1		T9	3		T11	5
valid_sources[0x36]	551	1			T2	1		T7	4		T28	1
valid_sources[0x37]	2940	1			T2	3		T27	5		T28	5
valid_sources[0x38]	570	1			T7	1		T28	7		T41	2
valid_sources[0x39]	729	1			T9	1		T27	1		T28	2
valid_sources[0x3a]	513	1			T2	1		T11	4		T27	1
valid_sources[0x3b]	543	1			T9	2		T27	4		T28	3
valid_sources[0x3c]	569	1			T2	2		T7	1		T9	1
valid_sources[0x3d]	527	1			T9	1		T28	6		T41	6
valid_sources[0x3e]	629	1			T7	2		T9	3		T27	1
valid_sources[0x3f]	661	1			T7	1		T9	1		T27	2
valid_sources[0x40]	1094	1			T9	2		T27	8		T28	2
valid_sources[0x41]	777	1			T27	1		T28	3		T41	1
valid_sources[0x42]	596	1			T11	1		T27	3		T28	4
valid_sources[0x43]	646	1			T9	2		T27	5		T28	3
valid_sources[0x44]	572	1			T9	1		T11	1		T28	4
valid_sources[0x45]	1847	1			T7	1		T9	3		T28	3
valid_sources[0x46]	655	1			T7	2		T9	1		T27	1
valid_sources[0x47]	715	1			T2	1		T3	1		T9	1
valid_sources[0x48]	586	1			T2	1		T9	2		T11	2
valid_sources[0x49]	751	1			T9	3		T28	5		T41	2
valid_sources[0x4a]	546	1			T9	2		T28	5		T41	4
valid_sources[0x4b]	526	1			T9	2		T27	4		T28	4
valid_sources[0x4c]	755	1			T9	2		T11	7		T27	7
valid_sources[0x4d]	634	1			T2	3		T9	1		T27	8
valid_sources[0x4e]	798	1			T9	1		T11	3		T27	15
valid_sources[0x4f]	946	1			T27	2		T28	7		T41	1
valid_sources[0x50]	1457	1			T9	1		T27	9		T28	4
valid_sources[0x51]	1439	1			T9	1		T11	2		T28	1
valid_sources[0x52]	518	1			T7	2		T11	1		T27	5
valid_sources[0x53]	641	1			T7	2		T9	1		T27	9
valid_sources[0x54]	539	1			T9	1		T27	3		T28	1
valid_sources[0x55]	619	1			T7	1		T9	3		T28	3
valid_sources[0x56]	730	1			T27	6		T28	4		T25	14
valid_sources[0x57]	819	1			T9	1		T27	8		T28	3
valid_sources[0x58]	632	1			T27	1		T28	1		T41	3
valid_sources[0x59]	586	1			T2	1		T27	4		T28	1
valid_sources[0x5a]	1028	1			T7	2		T11	3		T27	8
valid_sources[0x5b]	624	1			T27	8		T28	2		T41	1
valid_sources[0x5c]	1326	1			T7	2		T9	1		T11	2
valid_sources[0x5d]	880	1			T2	1		T7	2		T9	1
valid_sources[0x5e]	958	1			T7	3		T11	3		T27	6
valid_sources[0x5f]	787	1			T9	2		T11	1		T27	4
valid_sources[0x60]	596	1			T9	1		T27	2		T28	6
valid_sources[0x61]	662	1			T27	9		T28	1		T41	4
valid_sources[0x62]	701	1			T3	1		T9	1		T11	1
valid_sources[0x63]	573	1			T11	1		T27	2		T28	1
valid_sources[0x64]	694	1			T2	1		T27	6		T28	3
valid_sources[0x65]	977	1			T9	1		T27	6		T28	5
valid_sources[0x66]	605	1			T7	2		T28	2		T41	2
valid_sources[0x67]	726	1			T9	1		T27	3		T28	1
valid_sources[0x68]	744	1			T9	1		T27	3		T28	4
valid_sources[0x69]	623	1			T2	1		T7	1		T9	2
valid_sources[0x6a]	593	1			T9	2		T27	2		T28	1
valid_sources[0x6b]	831	1			T2	1		T3	1		T9	2
valid_sources[0x6c]	611	1			T9	1		T27	2		T28	4
valid_sources[0x6d]	718	1			T9	1		T27	1		T28	2
valid_sources[0x6e]	659	1			T2	1		T27	7		T28	4
valid_sources[0x6f]	556	1			T2	2		T7	1		T11	3
valid_sources[0x70]	786	1			T2	1		T9	1		T11	4
valid_sources[0x71]	674	1			T11	1		T28	4		T41	4
valid_sources[0x72]	644	1			T7	3		T9	1		T27	7
valid_sources[0x73]	893	1			T7	1		T9	1		T11	3
valid_sources[0x74]	608	1			T7	1		T28	3		T41	7
valid_sources[0x75]	573	1			T2	1		T7	1		T9	2
valid_sources[0x76]	707	1			T3	1		T7	1		T11	4
valid_sources[0x77]	517	1			T2	1		T7	2		T9	1
valid_sources[0x78]	767	1			T2	1		T9	2		T11	2
valid_sources[0x79]	585	1			T9	1		T27	2		T28	5
valid_sources[0x7a]	637	1			T2	1		T9	1		T28	1
valid_sources[0x7b]	595	1			T41	3		T25	7		T42	1
valid_sources[0x7c]	520	1			T7	1		T9	2		T11	1
valid_sources[0x7d]	885	1			T11	2		T28	4		T16	4
valid_sources[0x7e]	752	1			T2	2		T7	2		T11	4
valid_sources[0x7f]	468	1			T9	2		T27	2		T28	8
valid_sources[0x80]	707	1			T27	9		T28	4		T41	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27295

1

T1

88

T2

33

T3

3

values[0x0]

all_enables

biggest_size

20715

1

T1

85

T2

6

T3

6

values[0x1]

all_enables

biggest_size

12618

1

T1

42

T2

2

T7

8