SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35244 | 1 | T1 | 315 | T27 | 401 | T28 | 409 | ||||
others[1] | 35059 | 1 | T1 | 292 | T27 | 408 | T28 | 410 | ||||
others[2] | 34833 | 1 | T1 | 277 | T27 | 370 | T28 | 384 | ||||
others[3] | 58592 | 1 | T1 | 519 | T27 | 684 | T28 | 673 | ||||
false | 6893 | 1 | T1 | 50 | T27 | 50 | T28 | 50 | ||||
true | 12437 | 1 | T1 | 52 | T2 | 12 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34765 | 1 | T1 | 297 | T27 | 390 | T28 | 400 | ||||
others[1] | 34989 | 1 | T1 | 305 | T27 | 403 | T28 | 413 | ||||
others[2] | 34913 | 1 | T1 | 299 | T27 | 377 | T28 | 383 | ||||
others[3] | 58706 | 1 | T1 | 500 | T27 | 692 | T28 | 654 | ||||
false | 6035 | 1 | T1 | 50 | T27 | 50 | T28 | 50 | ||||
true | 11638 | 1 | T1 | 52 | T2 | 12 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 358 | 1 | T8 | 1 | T29 | 3 | T18 | 2 | ||||
others[1] | 368 | 1 | T8 | 1 | T29 | 2 | T18 | 2 | ||||
others[2] | 377 | 1 | T8 | 2 | T29 | 5 | T18 | 2 | ||||
others[3] | 612 | 1 | T29 | 15 | T18 | 5 | T45 | 2 | ||||
false | 4534 | 1 | T1 | 2 | T2 | 22 | T3 | 5 | ||||
true | 965 | 1 | T2 | 10 | T8 | 6 | T29 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |