Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T27

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	6958150	2784	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	6958150	114806	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	6958150	2425622	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	6958150	114808	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	6958150	2784	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	6958150	114806	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	6958150	2425622	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	6958150	114808	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	2784	0	0
T1	22781	21	0	0
T2	6266	0	0	0
T3	1448	1	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	24	0	0
T25	0	17	0	0
T26	0	18	0	0
T27	0	21	0	0
T28	0	21	0	0
T41	0	20	0	0
T42	0	4	0	0
T77	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	114806	0	0
T1	22781	475	0	0
T2	6266	0	0	0
T3	1448	100	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	855	0	0
T25	0	406	0	0
T26	0	326	0	0
T27	0	470	0	0
T28	0	520	0	0
T41	0	384	0	0
T42	0	359	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	2425622	0	0
T1	22781	10030	0	0
T2	6266	0	0	0
T3	1448	505	0	0
T7	4930	3622	0	0
T8	3067	0	0	0
T9	6130	3966	0	0
T10	2664	0	0	0
T11	6045	3052	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T16	0	1509	0	0
T17	0	720	0	0
T27	0	8868	0	0
T28	0	10403	0	0
T41	0	4357	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	114808	0	0
T1	22781	477	0	0
T2	6266	0	0	0
T3	1448	100	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	855	0	0
T25	0	406	0	0
T26	0	326	0	0
T27	0	470	0	0
T28	0	520	0	0
T41	0	384	0	0
T42	0	359	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	2784	0	0
T1	22781	21	0	0
T2	6266	0	0	0
T3	1448	1	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	24	0	0
T25	0	17	0	0
T26	0	18	0	0
T27	0	21	0	0
T28	0	21	0	0
T41	0	20	0	0
T42	0	4	0	0
T77	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	114806	0	0
T1	22781	475	0	0
T2	6266	0	0	0
T3	1448	100	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	855	0	0
T25	0	406	0	0
T26	0	326	0	0
T27	0	470	0	0
T28	0	520	0	0
T41	0	384	0	0
T42	0	359	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	2425622	0	0
T1	22781	10030	0	0
T2	6266	0	0	0
T3	1448	505	0	0
T7	4930	3622	0	0
T8	3067	0	0	0
T9	6130	3966	0	0
T10	2664	0	0	0
T11	6045	3052	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T16	0	1509	0	0
T17	0	720	0	0
T27	0	8868	0	0
T28	0	10403	0	0
T41	0	4357	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	114808	0	0
T1	22781	477	0	0
T2	6266	0	0	0
T3	1448	100	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	855	0	0
T25	0	406	0	0
T26	0	326	0	0
T27	0	470	0	0
T28	0	520	0	0
T41	0	384	0	0
T42	0	359	0	0
T77	0	13	0	0