Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	7531952	15611	0	0
intr_enable_rd_A	7531952	11902	0	0
reset_en_rd_A	7531952	1340	0	0
reset_en_regwen_rd_A	7531952	1108	0	0
wake_info_capture_dis_rd_A	7531952	1140	0	0
wakeup_en_rd_A	7531952	2199	0	0
wakeup_en_regwen_rd_A	7531952	981	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7531952	15611	0	0
T22	116443	10	0	0
T23	0	891	0	0
T24	0	227	0	0
T55	0	2	0	0
T56	0	879	0	0
T57	0	6	0	0
T59	0	194	0	0
T67	0	863	0	0
T74	0	22	0	0
T81	0	59	0	0
T82	3401	0	0	0
T83	15036	0	0	0
T84	3152	0	0	0
T85	1343	0	0	0
T86	6326	0	0	0
T87	3499	0	0	0
T88	860	0	0	0
T89	17174	0	0	0
T90	15532	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7531952	11902	0	0
T20	797	0	0	0
T45	3484	16	0	0
T46	810	0	0	0
T48	0	194	0	0
T77	2551	5	0	0
T78	10723	0	0	0
T80	0	169	0	0
T112	3960	17	0	0
T113	4385	27	0	0
T114	0	13	0	0
T115	0	23	0	0
T116	0	5	0	0
T117	0	56	0	0
T118	1969	0	0	0
T119	5988	0	0	0
T120	792	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7531952	1340	0	0
T65	2880	10	0	0
T74	1535	16	0	0
T91	8712	27	0	0
T92	2641	14	0	0
T94	30504	448	0	0
T96	2544	30	0	0
T98	1605	14	0	0
T108	2785	45	0	0
T110	2314	23	0	0
T121	15412	74	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7531952	1108	0	0
T65	2880	35	0	0
T74	1535	9	0	0
T91	8712	10	0	0
T92	2641	10	0	0
T94	30504	437	0	0
T96	2544	59	0	0
T98	1605	2	0	0
T108	2785	9	0	0
T110	2314	30	0	0
T121	15412	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7531952	1140	0	0
T65	2880	18	0	0
T74	1535	10	0	0
T92	2641	7	0	0
T94	30504	459	0	0
T96	2544	65	0	0
T98	1605	11	0	0
T108	2785	14	0	0
T110	2314	49	0	0
T121	15412	41	0	0
T122	4424	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7531952	2199	0	0
T65	2880	10	0	0
T74	1535	32	0	0
T91	8712	7	0	0
T92	2641	3	0	0
T94	30504	436	0	0
T96	2544	43	0	0
T98	1605	32	0	0
T108	2785	23	0	0
T110	2314	23	0	0
T121	15412	167	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7531952	981	0	0
T65	2880	44	0	0
T74	1535	10	0	0
T91	8712	15	0	0
T92	2641	6	0	0
T94	30504	341	0	0
T96	2544	49	0	0
T98	1605	8	0	0
T108	2785	34	0	0
T110	2314	27	0	0
T121	15412	48	0	0