Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	6958150	15197	0	0
IoStatusRise_A	6958150	16862	0	0
MainStatusFall_A	6958150	15197	0	0
MainStatusRise_A	6958150	16862	0	0
UsbStatusFall_A	6958150	9681	0	0
UsbStatusRise_A	6958150	11168	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	15197	0	0
T1	22781	87	0	0
T2	6266	18	0	0
T3	1448	4	0	0
T7	4930	12	0	0
T8	3067	18	0	0
T9	6130	19	0	0
T10	2664	0	0	0
T11	6045	20	0	0
T12	15526	1	0	0
T13	2177	0	0	0
T27	0	89	0	0
T28	0	83	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	16862	0	0
T1	22781	89	0	0
T2	6266	19	0	0
T3	1448	5	0	0
T7	4930	13	0	0
T8	3067	20	0	0
T9	6130	20	0	0
T10	2664	4	0	0
T11	6045	21	0	0
T12	15526	2	0	0
T13	2177	6	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	15197	0	0
T1	22781	87	0	0
T2	6266	18	0	0
T3	1448	4	0	0
T7	4930	12	0	0
T8	3067	18	0	0
T9	6130	19	0	0
T10	2664	0	0	0
T11	6045	20	0	0
T12	15526	1	0	0
T13	2177	0	0	0
T27	0	89	0	0
T28	0	83	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	16862	0	0
T1	22781	89	0	0
T2	6266	19	0	0
T3	1448	5	0	0
T7	4930	13	0	0
T8	3067	20	0	0
T9	6130	20	0	0
T10	2664	4	0	0
T11	6045	21	0	0
T12	15526	2	0	0
T13	2177	6	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	9681	0	0
T1	22781	37	0	0
T2	6266	18	0	0
T3	1448	4	0	0
T7	4930	9	0	0
T8	3067	18	0	0
T9	6130	13	0	0
T10	2664	0	0	0
T11	6045	12	0	0
T12	15526	1	0	0
T13	2177	0	0	0
T27	0	37	0	0
T28	0	31	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	11168	0	0
T1	22781	39	0	0
T2	6266	19	0	0
T3	1448	5	0	0
T7	4930	9	0	0
T8	3067	20	0	0
T9	6130	13	0	0
T10	2664	4	0	0
T11	6045	12	0	0
T12	15526	2	0	0
T13	2177	6	0	0