Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	6958150	16491	0	0
RomAllowCheckGoodState_A	6958150	16541	0	0
RomBlockActiveState_A	6958150	32515	0	0
RomBlockCheckGoodState_A	6958150	278376	0	0
RomIntgChkDisFalse_A	6958150	6632420	0	0
RomIntgChkDisTrue_A	6958150	135457	0	0
RstreqChkEsctimeout_A	6958150	1182	0	0
RstreqChkFsmterm_A	6958150	120	0	0
RstreqChkGlbesc_A	6958150	1183	0	0
RstreqChkMainpd_A	6958150	423711	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	16491	0	0
T1	22781	89	0	0
T2	6266	12	0	0
T3	1448	5	0	0
T7	4930	13	0	0
T8	3067	13	0	0
T9	6130	20	0	0
T10	2664	4	0	0
T11	6045	21	0	0
T12	15526	2	0	0
T13	2177	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	16541	0	0
T1	22781	89	0	0
T2	6266	13	0	0
T3	1448	5	0	0
T7	4930	13	0	0
T8	3067	14	0	0
T9	6130	20	0	0
T10	2664	4	0	0
T11	6045	21	0	0
T12	15526	2	0	0
T13	2177	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	32515	0	0
T14	15915	0	0	0
T15	614	0	0	0
T16	1967	0	0	0
T17	961	0	0	0
T19	948	0	0	0
T25	0	12	0	0
T27	20400	20	0	0
T28	22622	0	0	0
T41	10331	0	0	0
T43	15596	0	0	0
T45	0	776	0	0
T47	1139	0	0	0
T78	0	3	0	0
T82	0	679	0	0
T89	0	15	0	0
T123	0	1070	0	0
T124	0	921	0	0
T125	0	1035	0	0
T126	0	13	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	278376	0	0
T1	22781	1388	0	0
T2	6266	0	0	0
T3	1448	0	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	1423	0	0
T25	0	1283	0	0
T26	0	611	0	0
T27	0	1075	0	0
T28	0	1331	0	0
T41	0	715	0	0
T42	0	322	0	0
T45	0	525	0	0
T78	0	769	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	6632420	0	0
T1	22781	22072	0	0
T2	6266	5381	0	0
T3	1448	1034	0	0
T7	4930	4859	0	0
T8	3067	2110	0	0
T9	6130	6044	0	0
T10	2664	2339	0	0
T11	6045	5976	0	0
T12	15526	15468	0	0
T13	2177	1726	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	135457	0	0
T1	22781	547	0	0
T2	6266	0	0	0
T3	1448	0	0	0
T7	4930	0	0	0
T8	3067	0	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T25	0	529	0	0
T26	0	103	0	0
T45	0	120	0	0
T78	0	119	0	0
T82	0	281	0	0
T123	0	397	0	0
T124	0	95	0	0
T127	0	857	0	0
T128	0	586	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	1182	0	0
T2	6266	6	0	0
T3	1448	0	0	0
T7	4930	0	0	0
T8	3067	7	0	0
T9	6130	0	0	0
T10	2664	3	0	0
T11	6045	0	0	0
T12	15526	1	0	0
T13	2177	5	0	0
T14	0	1	0	0
T15	0	1	0	0
T27	20400	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	120	0	0
T4	9319	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	2161	0	0	0
T33	1565	0	0	0
T34	37209	0	0	0
T35	41920	0	0	0
T36	1092	0	0	0
T37	3253	0	0	0
T38	58526	0	0	0
T39	57002	0	0	0
T40	4412	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	1183	0	0
T2	6266	6	0	0
T3	1448	0	0	0
T7	4930	0	0	0
T8	3067	7	0	0
T9	6130	0	0	0
T10	2664	3	0	0
T11	6045	0	0	0
T12	15526	1	0	0
T13	2177	5	0	0
T14	0	1	0	0
T15	0	1	0	0
T27	20400	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6958150	423711	0	0
T1	22781	1207	0	0
T2	6266	58	0	0
T3	1448	0	0	0
T7	4930	0	0	0
T8	3067	135	0	0
T9	6130	0	0	0
T10	2664	0	0	0
T11	6045	0	0	0
T12	15526	0	0	0
T13	2177	0	0	0
T18	0	3408	0	0
T19	0	11	0	0
T25	0	1372	0	0
T27	0	1304	0	0
T28	0	1849	0	0
T41	0	964	0	0
T42	0	1386	0	0