Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

71146

1

T4

39

T5

5

T6

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	123253	1			T1	1		T2	1		T3	1
values[0x0]	61257	1			T4	40		T5	3		T6	24
values[0x1]	61697	1			T4	52		T5	7		T6	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	137705	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

108502

1

T2

1

T3

1

T4

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	784	1			T27	5		T29	1		T22	1
valid_sources[0x01]	861	1			T27	6		T13	1		T29	1
valid_sources[0x02]	695	1			T27	3		T146	1		T45	1
valid_sources[0x03]	923	1			T27	1		T22	1		T45	3
valid_sources[0x04]	746	1			T6	3		T27	6		T22	2
valid_sources[0x05]	1025	1			T45	1		T63	1		T15	6
valid_sources[0x06]	1551	1			T27	4		T29	3		T22	1
valid_sources[0x07]	1075	1			T6	2		T27	5		T29	1
valid_sources[0x08]	957	1			T43	3		T27	5		T22	1
valid_sources[0x09]	925	1			T43	2		T27	6		T22	1
valid_sources[0x0a]	813	1			T5	1		T27	3		T29	1
valid_sources[0x0b]	789	1			T6	2		T27	8		T29	2
valid_sources[0x0c]	897	1			T43	3		T27	3		T29	2
valid_sources[0x0d]	1685	1			T27	5		T29	1		T22	1
valid_sources[0x0e]	767	1			T6	4		T43	4		T27	2
valid_sources[0x0f]	729	1			T5	2		T43	2		T27	1
valid_sources[0x10]	934	1			T27	2		T29	1		T22	1
valid_sources[0x11]	732	1			T27	2		T61	1		T144	1
valid_sources[0x12]	846	1			T6	4		T27	8		T29	3
valid_sources[0x13]	811	1			T5	3		T43	4		T27	1
valid_sources[0x14]	1034	1			T43	3		T27	6		T42	2
valid_sources[0x15]	694	1			T2	1		T27	5		T29	1
valid_sources[0x16]	955	1			T27	8		T13	1		T22	1
valid_sources[0x17]	830	1			T6	1		T43	7		T27	4
valid_sources[0x18]	1140	1			T4	3		T5	1		T43	3
valid_sources[0x19]	1045	1			T4	1		T43	2		T27	4
valid_sources[0x1a]	653	1			T27	3		T29	1		T22	1
valid_sources[0x1b]	4704	1			T27	11		T29	2		T22	2
valid_sources[0x1c]	1165	1			T43	1		T27	2		T29	1
valid_sources[0x1d]	785	1			T43	2		T27	2		T28	1
valid_sources[0x1e]	1665	1			T5	2		T27	2		T29	4
valid_sources[0x1f]	657	1			T27	2		T22	1		T63	3
valid_sources[0x20]	825	1			T6	4		T27	2		T29	1
valid_sources[0x21]	925	1			T4	4		T43	7		T27	2
valid_sources[0x22]	759	1			T4	7		T6	1		T27	2
valid_sources[0x23]	1229	1			T5	1		T29	1		T22	1
valid_sources[0x24]	745	1			T6	6		T27	1		T29	1
valid_sources[0x25]	822	1			T43	2		T27	6		T13	1
valid_sources[0x26]	860	1			T6	3		T27	2		T22	1
valid_sources[0x27]	664	1			T6	2		T27	2		T29	5
valid_sources[0x28]	698	1			T27	2		T13	1		T22	1
valid_sources[0x29]	780	1			T4	6		T6	1		T27	9
valid_sources[0x2a]	873	1			T6	1		T13	1		T22	2
valid_sources[0x2b]	780	1			T27	3		T13	1		T22	1
valid_sources[0x2c]	767	1			T27	4		T13	1		T29	1
valid_sources[0x2d]	773	1			T43	1		T27	2		T22	3
valid_sources[0x2e]	822	1			T6	2		T27	8		T13	1
valid_sources[0x2f]	1665	1			T5	2		T43	1		T27	1
valid_sources[0x30]	801	1			T43	2		T27	2		T42	2
valid_sources[0x31]	978	1			T10	1		T27	3		T29	1
valid_sources[0x32]	844	1			T27	10		T13	1		T29	2
valid_sources[0x33]	1964	1			T4	8		T27	8		T13	1
valid_sources[0x34]	1613	1			T27	1		T22	1		T63	1
valid_sources[0x35]	909	1			T27	3		T13	1		T29	1
valid_sources[0x36]	1006	1			T27	4		T41	55		T42	1
valid_sources[0x37]	914	1			T4	7		T6	7		T43	1
valid_sources[0x38]	893	1			T27	2		T29	3		T28	2
valid_sources[0x39]	1100	1			T43	1		T27	2		T29	1
valid_sources[0x3a]	1632	1			T27	4		T29	2		T45	1
valid_sources[0x3b]	958	1			T43	3		T27	3		T29	3
valid_sources[0x3c]	819	1			T4	14		T7	1		T27	1
valid_sources[0x3d]	892	1			T4	2		T43	1		T27	3
valid_sources[0x3e]	737	1			T27	3		T13	1		T29	1
valid_sources[0x3f]	1149	1			T27	1		T119	2		T77	1
valid_sources[0x40]	818	1			T6	7		T27	1		T22	1
valid_sources[0x41]	723	1			T6	1		T10	6		T43	1
valid_sources[0x42]	999	1			T27	1		T13	1		T63	1
valid_sources[0x43]	1875	1			T43	1		T27	3		T29	1
valid_sources[0x44]	650	1			T27	2		T61	1		T143	1
valid_sources[0x45]	989	1			T27	2		T42	2		T63	1
valid_sources[0x46]	744	1			T43	1		T22	2		T42	2
valid_sources[0x47]	775	1			T27	4		T29	1		T22	2
valid_sources[0x48]	1035	1			T27	1		T22	2		T28	1
valid_sources[0x49]	840	1			T5	1		T6	8		T43	4
valid_sources[0x4a]	800	1			T4	1		T43	2		T27	1
valid_sources[0x4b]	752	1			T4	7		T43	5		T27	2
valid_sources[0x4c]	879	1			T27	3		T45	1		T119	5
valid_sources[0x4d]	879	1			T43	2		T27	4		T22	1
valid_sources[0x4e]	764	1			T28	1		T42	1		T45	2
valid_sources[0x4f]	747	1			T43	2		T27	3		T42	1
valid_sources[0x50]	856	1			T27	10		T42	2		T45	1
valid_sources[0x51]	807	1			T13	1		T29	4		T45	7
valid_sources[0x52]	631	1			T43	6		T27	9		T29	2
valid_sources[0x53]	735	1			T43	2		T27	3		T22	1
valid_sources[0x54]	780	1			T27	6		T29	2		T22	3
valid_sources[0x55]	859	1			T27	5		T42	1		T143	1
valid_sources[0x56]	744	1			T43	2		T27	4		T29	2
valid_sources[0x57]	1004	1			T27	2		T29	1		T22	2
valid_sources[0x58]	1012	1			T4	1		T27	5		T29	3
valid_sources[0x59]	861	1			T27	3		T22	2		T146	1
valid_sources[0x5a]	866	1			T27	3		T29	1		T143	1
valid_sources[0x5b]	1040	1			T6	3		T27	2		T29	2
valid_sources[0x5c]	713	1			T27	7		T144	1		T64	1
valid_sources[0x5d]	790	1			T27	4		T22	2		T28	1
valid_sources[0x5e]	599	1			T43	3		T27	3		T29	3
valid_sources[0x5f]	1581	1			T6	3		T27	4		T22	1
valid_sources[0x60]	734	1			T3	1		T4	1		T27	1
valid_sources[0x61]	775	1			T29	2		T45	1		T63	1
valid_sources[0x62]	761	1			T4	4		T5	1		T43	1
valid_sources[0x63]	762	1			T4	12		T27	2		T29	2
valid_sources[0x64]	1842	1			T27	2		T22	1		T42	3
valid_sources[0x65]	695	1			T27	3		T22	1		T42	4
valid_sources[0x66]	899	1			T43	2		T27	1		T29	2
valid_sources[0x67]	677	1			T27	3		T29	4		T22	3
valid_sources[0x68]	1839	1			T27	1		T29	1		T22	2
valid_sources[0x69]	1023	1			T43	2		T27	5		T29	1
valid_sources[0x6a]	955	1			T27	1		T29	1		T22	1
valid_sources[0x6b]	949	1			T4	2		T6	3		T43	9
valid_sources[0x6c]	612	1			T43	1		T27	4		T13	1
valid_sources[0x6d]	1127	1			T27	7		T29	1		T63	2
valid_sources[0x6e]	750	1			T27	1		T29	1		T22	1
valid_sources[0x6f]	737	1			T29	1		T22	2		T143	4
valid_sources[0x70]	759	1			T27	2		T22	1		T146	10
valid_sources[0x71]	707	1			T4	1		T27	8		T13	1
valid_sources[0x72]	1013	1			T4	11		T27	5		T42	2
valid_sources[0x73]	1271	1			T10	16		T27	1		T13	1
valid_sources[0x74]	746	1			T8	14		T27	4		T22	2
valid_sources[0x75]	777	1			T43	7		T27	4		T29	2
valid_sources[0x76]	727	1			T29	1		T63	2		T143	1
valid_sources[0x77]	885	1			T4	7		T43	2		T27	7
valid_sources[0x78]	866	1			T27	4		T29	1		T22	1
valid_sources[0x79]	790	1			T4	3		T43	1		T27	9
valid_sources[0x7a]	773	1			T4	2		T10	6		T29	1
valid_sources[0x7b]	1104	1			T27	3		T29	2		T45	1
valid_sources[0x7c]	809	1			T5	2		T10	13		T27	6
valid_sources[0x7d]	728	1			T4	1		T27	10		T29	2
valid_sources[0x7e]	887	1			T43	9		T27	3		T22	3
valid_sources[0x7f]	795	1			T27	4		T29	1		T63	1
valid_sources[0x80]	845	1			T9	107		T43	6		T29	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31130

1

T4

20

T5

5

T6

8

values[0x0]

all_enables

biggest_size

24877

1

T4

11

T6

11

T8

5

values[0x1]

all_enables

biggest_size

15139

1

T4

8

T6

8

T8

2