SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35197 | 1 | T12 | 1 | T26 | 263 | T27 | 321 | ||||
others[1] | 35056 | 1 | T26 | 300 | T27 | 280 | T52 | 397 | ||||
others[2] | 34908 | 1 | T12 | 1 | T26 | 308 | T27 | 289 | ||||
others[3] | 58411 | 1 | T26 | 498 | T27 | 507 | T52 | 688 | ||||
false | 8074 | 1 | T4 | 20 | T6 | 10 | T9 | 10 | ||||
true | 13974 | 1 | T1 | 4 | T2 | 6 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35181 | 1 | T26 | 329 | T27 | 327 | T52 | 392 | ||||
others[1] | 35361 | 1 | T26 | 303 | T27 | 302 | T52 | 416 | ||||
others[2] | 34572 | 1 | T12 | 1 | T26 | 273 | T27 | 287 | ||||
others[3] | 58258 | 1 | T26 | 492 | T27 | 495 | T46 | 1 | ||||
false | 6624 | 1 | T4 | 10 | T6 | 5 | T9 | 5 | ||||
true | 12602 | 1 | T1 | 4 | T2 | 6 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 412 | 1 | T12 | 1 | T13 | 1 | T29 | 5 | ||||
others[1] | 381 | 1 | T13 | 1 | T29 | 10 | T22 | 3 | ||||
others[2] | 383 | 1 | T12 | 1 | T29 | 2 | T22 | 6 | ||||
others[3] | 643 | 1 | T12 | 1 | T29 | 6 | T22 | 6 | ||||
false | 5346 | 1 | T1 | 4 | T2 | 6 | T3 | 1 | ||||
true | 1277 | 1 | T12 | 2 | T13 | 7 | T29 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |