Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T9,T26

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	7885844	3000	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	7885844	121131	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	7885844	2702157	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	7885844	121150	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	7885844	3000	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	7885844	121131	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	7885844	2702157	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	7885844	121150	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	3000	0	0
T4	5120	4	0	0
T5	1240	1	0	0
T6	3000	4	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	4	0	0
T10	2087	0	0	0
T12	1628	0	0	0
T15	0	7	0	0
T16	0	8	0	0
T26	17432	21	0	0
T27	0	22	0	0
T43	9462	0	0	0
T52	0	19	0	0
T77	0	9	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	121131	0	0
T4	5120	96	0	0
T5	1240	9	0	0
T6	3000	149	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	478	0	0
T10	2087	0	0	0
T12	1628	0	0	0
T15	0	539	0	0
T16	0	250	0	0
T26	17432	630	0	0
T27	0	1713	0	0
T43	9462	0	0	0
T52	0	292	0	0
T77	0	175	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	2702157	0	0
T4	5120	1977	0	0
T5	1240	1013	0	0
T6	3000	2494	0	0
T7	1448	0	0	0
T8	3218	763	0	0
T9	6728	4512	0	0
T10	2087	788	0	0
T12	1628	0	0	0
T26	17432	7684	0	0
T27	0	26566	0	0
T43	9462	4770	0	0
T63	0	287	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	121150	0	0
T4	5120	96	0	0
T5	1240	9	0	0
T6	3000	149	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	478	0	0
T10	2087	0	0	0
T12	1628	0	0	0
T15	0	539	0	0
T16	0	250	0	0
T26	17432	630	0	0
T27	0	1713	0	0
T43	9462	0	0	0
T52	0	292	0	0
T77	0	175	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	3000	0	0
T4	5120	4	0	0
T5	1240	1	0	0
T6	3000	4	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	4	0	0
T10	2087	0	0	0
T12	1628	0	0	0
T15	0	7	0	0
T16	0	8	0	0
T26	17432	21	0	0
T27	0	22	0	0
T43	9462	0	0	0
T52	0	19	0	0
T77	0	9	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	121131	0	0
T4	5120	96	0	0
T5	1240	9	0	0
T6	3000	149	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	478	0	0
T10	2087	0	0	0
T12	1628	0	0	0
T15	0	539	0	0
T16	0	250	0	0
T26	17432	630	0	0
T27	0	1713	0	0
T43	9462	0	0	0
T52	0	292	0	0
T77	0	175	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	2702157	0	0
T4	5120	1977	0	0
T5	1240	1013	0	0
T6	3000	2494	0	0
T7	1448	0	0	0
T8	3218	763	0	0
T9	6728	4512	0	0
T10	2087	788	0	0
T12	1628	0	0	0
T26	17432	7684	0	0
T27	0	26566	0	0
T43	9462	4770	0	0
T63	0	287	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	121150	0	0
T4	5120	96	0	0
T5	1240	9	0	0
T6	3000	149	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	478	0	0
T10	2087	0	0	0
T12	1628	0	0	0
T15	0	539	0	0
T16	0	250	0	0
T26	17432	630	0	0
T27	0	1713	0	0
T43	9462	0	0	0
T52	0	292	0	0
T77	0	175	0	0