Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8491630	14330	0	0
intr_enable_rd_A	8491630	13634	0	0
reset_en_rd_A	8491630	1585	0	0
reset_en_regwen_rd_A	8491630	1510	0	0
wake_info_capture_dis_rd_A	8491630	1465	0	0
wakeup_en_rd_A	8491630	1998	0	0
wakeup_en_regwen_rd_A	8491630	1358	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8491630	14330	0	0
T23	186117	5	0	0
T24	168108	9	0	0
T25	0	4	0	0
T53	0	10	0	0
T54	0	350	0	0
T56	0	34	0	0
T59	0	159	0	0
T70	0	7	0	0
T84	0	12	0	0
T85	1043	0	0	0
T86	4229	0	0	0
T87	831	0	0	0
T88	1108	0	0	0
T89	991	0	0	0
T90	1390	0	0	0
T91	1090	0	0	0
T92	2705	0	0	0
T118	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8491630	13634	0	0
T6	3000	33	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	0	0	0
T10	2087	0	0	0
T12	1628	0	0	0
T15	0	120	0	0
T17	2581	0	0	0
T22	0	81	0	0
T26	17432	0	0	0
T27	53644	0	0	0
T29	0	105	0	0
T43	9462	0	0	0
T52	0	159	0	0
T78	0	50	0	0
T119	0	42	0	0
T120	0	79	0	0
T121	0	29	0	0
T122	0	9	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8491630	1585	0	0
T56	4049	11	0	0
T60	9517	7	0	0
T66	10301	27	0	0
T73	11440	11	0	0
T76	10262	14	0	0
T95	1698	2	0	0
T96	1275	1	0	0
T98	1120	9	0	0
T115	2979	20	0	0
T123	2526	9	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8491630	1510	0	0
T60	9517	27	0	0
T66	10301	25	0	0
T73	11440	11	0	0
T76	10262	11	0	0
T95	1698	3	0	0
T98	1120	1	0	0
T101	15319	213	0	0
T115	2979	31	0	0
T123	2526	7	0	0
T124	15185	52	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8491630	1465	0	0
T60	9517	22	0	0
T66	10301	19	0	0
T73	11440	4	0	0
T76	10262	21	0	0
T95	1698	3	0	0
T96	1275	4	0	0
T101	15319	228	0	0
T115	2979	1	0	0
T123	2526	16	0	0
T124	15185	22	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8491630	1998	0	0
T56	4049	22	0	0
T60	9517	23	0	0
T66	10301	21	0	0
T73	11440	4	0	0
T76	10262	9	0	0
T95	1698	13	0	0
T98	1120	6	0	0
T115	2979	31	0	0
T123	2526	5	0	0
T124	15185	33	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8491630	1358	0	0
T56	4049	9	0	0
T60	9517	12	0	0
T66	10301	8	0	0
T73	11440	8	0	0
T76	10262	8	0	0
T95	1698	4	0	0
T98	1120	2	0	0
T115	2979	19	0	0
T123	2526	7	0	0
T124	15185	22	0	0