Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	7885844	20408	0	0
RomAllowCheckGoodState_A	7885844	20457	0	0
RomBlockActiveState_A	7885844	30579	0	0
RomBlockCheckGoodState_A	7885844	296122	0	0
RomIntgChkDisFalse_A	7885844	7554588	0	0
RomIntgChkDisTrue_A	7885844	109791	0	0
RstreqChkEsctimeout_A	7885844	1498	0	0
RstreqChkFsmterm_A	7885844	140	0	0
RstreqChkGlbesc_A	7885844	1498	0	0
RstreqChkMainpd_A	7885844	436662	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	20408	0	0
T1	1081	4	0	0
T2	3609	6	0	0
T3	15746	6	0	0
T4	5120	19	0	0
T5	1240	3	0	0
T6	3000	10	0	0
T7	1448	3	0	0
T8	3218	3	0	0
T9	6728	10	0	0
T10	2087	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	20457	0	0
T1	1081	4	0	0
T2	3609	6	0	0
T3	15746	6	0	0
T4	5120	19	0	0
T5	1240	3	0	0
T6	3000	10	0	0
T7	1448	3	0	0
T8	3218	3	0	0
T9	6728	10	0	0
T10	2087	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	30579	0	0
T11	15621	0	0	0
T12	1628	248	0	0
T13	2423	0	0	0
T17	2581	0	0	0
T22	6539	0	0	0
T26	17432	0	0	0
T27	53644	0	0	0
T28	7146	0	0	0
T29	4379	0	0	0
T44	722	0	0	0
T46	0	465	0	0
T52	0	1	0	0
T79	0	5	0	0
T82	0	3	0	0
T92	0	396	0	0
T122	0	359	0	0
T125	0	1131	0	0
T126	0	2	0	0
T127	0	1550	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	296122	0	0
T4	5120	230	0	0
T5	1240	0	0	0
T6	3000	115	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	115	0	0
T10	2087	0	0	0
T12	1628	93	0	0
T15	0	206	0	0
T16	0	367	0	0
T26	17432	1345	0	0
T27	0	4056	0	0
T43	9462	0	0	0
T64	0	92	0	0
T77	0	459	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	7554588	0	0
T1	1081	749	0	0
T2	3609	3180	0	0
T3	15746	15693	0	0
T4	5120	5026	0	0
T5	1240	1156	0	0
T6	3000	2854	0	0
T7	1448	1254	0	0
T8	3218	3151	0	0
T9	6728	6590	0	0
T10	2087	1991	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	109791	0	0
T11	15621	0	0	0
T12	1628	727	0	0
T13	2423	0	0	0
T17	2581	0	0	0
T22	6539	0	0	0
T26	17432	468	0	0
T27	53644	1038	0	0
T28	7146	0	0	0
T29	4379	0	0	0
T44	722	0	0	0
T46	0	1000	0	0
T79	0	350	0	0
T92	0	191	0	0
T122	0	204	0	0
T125	0	1196	0	0
T127	0	2027	0	0
T128	0	280	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	1498	0	0
T2	3609	5	0	0
T3	15746	1	0	0
T4	5120	0	0	0
T5	1240	0	0	0
T6	3000	0	0	0
T7	1448	1	0	0
T8	3218	0	0	0
T9	6728	0	0	0
T10	2087	0	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	5	0	0
T28	0	7	0	0
T41	0	10	0	0
T42	0	3	0	0
T43	9462	0	0	0
T44	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	140	0	0
T19	22921	20	0	0
T20	0	40	0	0
T21	0	40	0	0
T30	0	20	0	0
T31	0	20	0	0
T32	1988	0	0	0
T33	2204	0	0	0
T34	1455	0	0	0
T35	3279	0	0	0
T36	2349	0	0	0
T37	652	0	0	0
T38	3072	0	0	0
T39	800	0	0	0
T40	6752	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	1498	0	0
T2	3609	5	0	0
T3	15746	1	0	0
T4	5120	0	0	0
T5	1240	0	0	0
T6	3000	0	0	0
T7	1448	1	0	0
T8	3218	0	0	0
T9	6728	0	0	0
T10	2087	0	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	5	0	0
T28	0	7	0	0
T41	0	10	0	0
T42	0	3	0	0
T43	9462	0	0	0
T44	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7885844	436662	0	0
T1	1081	18	0	0
T2	3609	0	0	0
T3	15746	0	0	0
T4	5120	412	0	0
T5	1240	0	0	0
T6	3000	384	0	0
T7	1448	0	0	0
T8	3218	0	0	0
T9	6728	947	0	0
T10	2087	0	0	0
T12	0	75	0	0
T13	0	57	0	0
T17	0	11	0	0
T26	0	2047	0	0
T27	0	6042	0	0
T28	0	92	0	0