| T811 |
/workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1924432137 |
|
|
Mar 17 01:44:52 PM PDT 24 |
Mar 17 01:44:56 PM PDT 24 |
929884776 ps |
| T132 |
/workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1624309617 |
|
|
Mar 17 01:44:12 PM PDT 24 |
Mar 17 01:44:13 PM PDT 24 |
68049028 ps |
| T812 |
/workspace/coverage/default/34.pwrmgr_escalation_timeout.3111557841 |
|
|
Mar 17 01:45:43 PM PDT 24 |
Mar 17 01:45:44 PM PDT 24 |
562727746 ps |
| T813 |
/workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.356972633 |
|
|
Mar 17 01:45:57 PM PDT 24 |
Mar 17 01:46:00 PM PDT 24 |
851200249 ps |
| T814 |
/workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.207502722 |
|
|
Mar 17 01:44:14 PM PDT 24 |
Mar 17 01:44:15 PM PDT 24 |
54093691 ps |
| T815 |
/workspace/coverage/default/42.pwrmgr_reset_invalid.3291356890 |
|
|
Mar 17 01:45:49 PM PDT 24 |
Mar 17 01:45:50 PM PDT 24 |
104748104 ps |
| T816 |
/workspace/coverage/default/5.pwrmgr_escalation_timeout.3513213803 |
|
|
Mar 17 01:44:21 PM PDT 24 |
Mar 17 01:44:22 PM PDT 24 |
169528595 ps |
| T817 |
/workspace/coverage/default/4.pwrmgr_reset.3423801475 |
|
|
Mar 17 01:44:13 PM PDT 24 |
Mar 17 01:44:13 PM PDT 24 |
45446325 ps |
| T818 |
/workspace/coverage/default/36.pwrmgr_reset_invalid.2637270069 |
|
|
Mar 17 01:45:49 PM PDT 24 |
Mar 17 01:45:50 PM PDT 24 |
104524367 ps |
| T819 |
/workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1364712328 |
|
|
Mar 17 01:45:46 PM PDT 24 |
Mar 17 01:45:49 PM PDT 24 |
811063958 ps |
| T820 |
/workspace/coverage/default/9.pwrmgr_aborted_low_power.1337975517 |
|
|
Mar 17 01:44:35 PM PDT 24 |
Mar 17 01:44:36 PM PDT 24 |
27233121 ps |
| T821 |
/workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.2633035521 |
|
|
Mar 17 01:46:11 PM PDT 24 |
Mar 17 01:46:13 PM PDT 24 |
58578194 ps |
| T822 |
/workspace/coverage/default/9.pwrmgr_wakeup_reset.2099421192 |
|
|
Mar 17 01:44:32 PM PDT 24 |
Mar 17 01:44:33 PM PDT 24 |
299994703 ps |
| T823 |
/workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.2593972596 |
|
|
Mar 17 01:45:56 PM PDT 24 |
Mar 17 01:45:57 PM PDT 24 |
201875450 ps |
| T824 |
/workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3312399515 |
|
|
Mar 17 01:45:26 PM PDT 24 |
Mar 17 01:45:28 PM PDT 24 |
1121196887 ps |
| T825 |
/workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.1726015308 |
|
|
Mar 17 01:45:55 PM PDT 24 |
Mar 17 01:45:56 PM PDT 24 |
149486176 ps |
| T826 |
/workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.868985815 |
|
|
Mar 17 01:44:12 PM PDT 24 |
Mar 17 01:44:15 PM PDT 24 |
841541189 ps |
| T827 |
/workspace/coverage/default/18.pwrmgr_lowpower_invalid.728654914 |
|
|
Mar 17 01:44:55 PM PDT 24 |
Mar 17 01:44:57 PM PDT 24 |
53943458 ps |
| T828 |
/workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.837331122 |
|
|
Mar 17 01:45:45 PM PDT 24 |
Mar 17 01:45:48 PM PDT 24 |
1354428503 ps |
| T829 |
/workspace/coverage/default/31.pwrmgr_glitch.4094439070 |
|
|
Mar 17 01:45:45 PM PDT 24 |
Mar 17 01:45:46 PM PDT 24 |
25414525 ps |
| T830 |
/workspace/coverage/default/44.pwrmgr_wakeup.1657280064 |
|
|
Mar 17 01:46:04 PM PDT 24 |
Mar 17 01:46:05 PM PDT 24 |
88917914 ps |
| T831 |
/workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.3683092038 |
|
|
Mar 17 01:44:04 PM PDT 24 |
Mar 17 01:44:05 PM PDT 24 |
81192461 ps |
| T832 |
/workspace/coverage/default/17.pwrmgr_reset_invalid.2421358735 |
|
|
Mar 17 01:44:50 PM PDT 24 |
Mar 17 01:44:51 PM PDT 24 |
140551101 ps |
| T833 |
/workspace/coverage/default/3.pwrmgr_global_esc.582670874 |
|
|
Mar 17 01:44:12 PM PDT 24 |
Mar 17 01:44:13 PM PDT 24 |
44143274 ps |
| T834 |
/workspace/coverage/default/30.pwrmgr_escalation_timeout.2388724858 |
|
|
Mar 17 01:45:27 PM PDT 24 |
Mar 17 01:45:28 PM PDT 24 |
164882670 ps |
| T835 |
/workspace/coverage/default/33.pwrmgr_global_esc.2954014342 |
|
|
Mar 17 01:45:47 PM PDT 24 |
Mar 17 01:45:48 PM PDT 24 |
32012327 ps |
| T836 |
/workspace/coverage/default/7.pwrmgr_wakeup_reset.2892403947 |
|
|
Mar 17 01:44:20 PM PDT 24 |
Mar 17 01:44:21 PM PDT 24 |
301310578 ps |
| T837 |
/workspace/coverage/default/43.pwrmgr_reset_invalid.1429026595 |
|
|
Mar 17 01:45:52 PM PDT 24 |
Mar 17 01:45:53 PM PDT 24 |
160355034 ps |
| T838 |
/workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1798659931 |
|
|
Mar 17 01:45:12 PM PDT 24 |
Mar 17 01:45:13 PM PDT 24 |
104484290 ps |
| T839 |
/workspace/coverage/default/6.pwrmgr_global_esc.3109495249 |
|
|
Mar 17 01:44:24 PM PDT 24 |
Mar 17 01:44:25 PM PDT 24 |
25414986 ps |
| T840 |
/workspace/coverage/default/40.pwrmgr_stress_all.3425024206 |
|
|
Mar 17 01:45:51 PM PDT 24 |
Mar 17 01:45:52 PM PDT 24 |
130633590 ps |
| T841 |
/workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2212733692 |
|
|
Mar 17 01:45:26 PM PDT 24 |
Mar 17 01:45:29 PM PDT 24 |
1057983434 ps |
| T842 |
/workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1055393852 |
|
|
Mar 17 01:45:52 PM PDT 24 |
Mar 17 01:45:53 PM PDT 24 |
574333354 ps |
| T843 |
/workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1158328374 |
|
|
Mar 17 01:44:31 PM PDT 24 |
Mar 17 01:44:32 PM PDT 24 |
255264448 ps |
| T844 |
/workspace/coverage/default/24.pwrmgr_wakeup_reset.2062617139 |
|
|
Mar 17 01:45:04 PM PDT 24 |
Mar 17 01:45:06 PM PDT 24 |
210651104 ps |
| T845 |
/workspace/coverage/default/48.pwrmgr_smoke.4253428280 |
|
|
Mar 17 01:46:20 PM PDT 24 |
Mar 17 01:46:22 PM PDT 24 |
28899784 ps |
| T846 |
/workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2511348218 |
|
|
Mar 17 01:44:34 PM PDT 24 |
Mar 17 01:44:35 PM PDT 24 |
111351419 ps |
| T847 |
/workspace/coverage/default/40.pwrmgr_smoke.2916996596 |
|
|
Mar 17 01:45:50 PM PDT 24 |
Mar 17 01:45:51 PM PDT 24 |
31532157 ps |
| T848 |
/workspace/coverage/default/45.pwrmgr_smoke.646592577 |
|
|
Mar 17 01:45:54 PM PDT 24 |
Mar 17 01:45:55 PM PDT 24 |
30085210 ps |
| T849 |
/workspace/coverage/default/14.pwrmgr_wakeup.3840938116 |
|
|
Mar 17 01:44:50 PM PDT 24 |
Mar 17 01:44:51 PM PDT 24 |
130773280 ps |
| T850 |
/workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.810394048 |
|
|
Mar 17 01:44:14 PM PDT 24 |
Mar 17 01:44:16 PM PDT 24 |
154260054 ps |
| T851 |
/workspace/coverage/default/35.pwrmgr_smoke.1398174961 |
|
|
Mar 17 01:45:47 PM PDT 24 |
Mar 17 01:45:48 PM PDT 24 |
29728115 ps |
| T852 |
/workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.1683913538 |
|
|
Mar 17 01:44:37 PM PDT 24 |
Mar 17 01:44:38 PM PDT 24 |
240713823 ps |
| T853 |
/workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3580261233 |
|
|
Mar 17 01:44:11 PM PDT 24 |
Mar 17 01:44:12 PM PDT 24 |
48858220 ps |
| T854 |
/workspace/coverage/default/37.pwrmgr_smoke.748924667 |
|
|
Mar 17 01:45:40 PM PDT 24 |
Mar 17 01:45:41 PM PDT 24 |
74981454 ps |
| T855 |
/workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2315227620 |
|
|
Mar 17 01:45:53 PM PDT 24 |
Mar 17 01:45:56 PM PDT 24 |
1030105244 ps |
| T856 |
/workspace/coverage/default/41.pwrmgr_glitch.83076283 |
|
|
Mar 17 01:45:53 PM PDT 24 |
Mar 17 01:45:53 PM PDT 24 |
103306893 ps |
| T857 |
/workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.2576820132 |
|
|
Mar 17 01:46:27 PM PDT 24 |
Mar 17 01:46:28 PM PDT 24 |
146303266 ps |
| T858 |
/workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2015415138 |
|
|
Mar 17 01:44:50 PM PDT 24 |
Mar 17 01:44:53 PM PDT 24 |
1766521343 ps |
| T859 |
/workspace/coverage/default/49.pwrmgr_smoke.1970083287 |
|
|
Mar 17 01:46:35 PM PDT 24 |
Mar 17 01:46:35 PM PDT 24 |
57304832 ps |
| T860 |
/workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2294731282 |
|
|
Mar 17 01:45:43 PM PDT 24 |
Mar 17 01:45:44 PM PDT 24 |
82916626 ps |
| T861 |
/workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1910079860 |
|
|
Mar 17 01:44:34 PM PDT 24 |
Mar 17 01:44:37 PM PDT 24 |
840148844 ps |
| T862 |
/workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1593800855 |
|
|
Mar 17 01:45:50 PM PDT 24 |
Mar 17 01:45:53 PM PDT 24 |
1474988551 ps |
| T863 |
/workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.622169133 |
|
|
Mar 17 01:46:02 PM PDT 24 |
Mar 17 01:46:04 PM PDT 24 |
2230075538 ps |
| T864 |
/workspace/coverage/default/1.pwrmgr_lowpower_invalid.3216638027 |
|
|
Mar 17 01:44:12 PM PDT 24 |
Mar 17 01:44:13 PM PDT 24 |
50371210 ps |
| T865 |
/workspace/coverage/default/25.pwrmgr_smoke.529944816 |
|
|
Mar 17 01:45:14 PM PDT 24 |
Mar 17 01:45:15 PM PDT 24 |
38150143 ps |
| T866 |
/workspace/coverage/default/41.pwrmgr_wakeup_reset.52174443 |
|
|
Mar 17 01:45:49 PM PDT 24 |
Mar 17 01:45:50 PM PDT 24 |
69468057 ps |
| T867 |
/workspace/coverage/default/36.pwrmgr_escalation_timeout.2026575322 |
|
|
Mar 17 01:45:47 PM PDT 24 |
Mar 17 01:45:49 PM PDT 24 |
165830724 ps |
| T868 |
/workspace/coverage/default/22.pwrmgr_glitch.2994334201 |
|
|
Mar 17 01:45:12 PM PDT 24 |
Mar 17 01:45:13 PM PDT 24 |
47521997 ps |
| T869 |
/workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.994799326 |
|
|
Mar 17 01:45:34 PM PDT 24 |
Mar 17 01:45:35 PM PDT 24 |
477090942 ps |
| T870 |
/workspace/coverage/default/23.pwrmgr_aborted_low_power.2208933450 |
|
|
Mar 17 01:44:58 PM PDT 24 |
Mar 17 01:44:59 PM PDT 24 |
74121090 ps |
| T871 |
/workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3425772789 |
|
|
Mar 17 01:45:42 PM PDT 24 |
Mar 17 01:45:43 PM PDT 24 |
45621731 ps |
| T872 |
/workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3248532854 |
|
|
Mar 17 01:45:44 PM PDT 24 |
Mar 17 01:45:47 PM PDT 24 |
960861622 ps |
| T873 |
/workspace/coverage/default/10.pwrmgr_escalation_timeout.4080432568 |
|
|
Mar 17 01:44:35 PM PDT 24 |
Mar 17 01:44:36 PM PDT 24 |
612031082 ps |
| T874 |
/workspace/coverage/default/5.pwrmgr_reset_invalid.3154223914 |
|
|
Mar 17 01:44:19 PM PDT 24 |
Mar 17 01:44:20 PM PDT 24 |
195264561 ps |
| T875 |
/workspace/coverage/default/37.pwrmgr_escalation_timeout.3303509581 |
|
|
Mar 17 01:45:48 PM PDT 24 |
Mar 17 01:45:49 PM PDT 24 |
162775164 ps |
| T876 |
/workspace/coverage/default/45.pwrmgr_lowpower_invalid.4213106914 |
|
|
Mar 17 01:46:07 PM PDT 24 |
Mar 17 01:46:08 PM PDT 24 |
91231541 ps |
| T877 |
/workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1705487606 |
|
|
Mar 17 01:45:50 PM PDT 24 |
Mar 17 01:45:53 PM PDT 24 |
911280254 ps |
| T878 |
/workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3435210523 |
|
|
Mar 17 01:45:03 PM PDT 24 |
Mar 17 01:45:04 PM PDT 24 |
78182806 ps |
| T879 |
/workspace/coverage/default/31.pwrmgr_lowpower_invalid.1724642319 |
|
|
Mar 17 01:45:50 PM PDT 24 |
Mar 17 01:45:50 PM PDT 24 |
48106084 ps |
| T880 |
/workspace/coverage/default/1.pwrmgr_wakeup.1559812861 |
|
|
Mar 17 01:44:10 PM PDT 24 |
Mar 17 01:44:11 PM PDT 24 |
285648140 ps |
| T881 |
/workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.1498117103 |
|
|
Mar 17 01:45:20 PM PDT 24 |
Mar 17 01:45:21 PM PDT 24 |
52566817 ps |
| T882 |
/workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.4191918776 |
|
|
Mar 17 01:45:53 PM PDT 24 |
Mar 17 01:45:54 PM PDT 24 |
290844708 ps |
| T883 |
/workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.2874049354 |
|
|
Mar 17 01:44:35 PM PDT 24 |
Mar 17 01:44:36 PM PDT 24 |
314409208 ps |
| T884 |
/workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.4041879340 |
|
|
Mar 17 01:45:09 PM PDT 24 |
Mar 17 01:45:10 PM PDT 24 |
85009403 ps |
| T885 |
/workspace/coverage/default/26.pwrmgr_escalation_timeout.2404851053 |
|
|
Mar 17 01:45:14 PM PDT 24 |
Mar 17 01:45:15 PM PDT 24 |
322658134 ps |
| T886 |
/workspace/coverage/default/36.pwrmgr_aborted_low_power.491953428 |
|
|
Mar 17 01:45:58 PM PDT 24 |
Mar 17 01:45:58 PM PDT 24 |
64488027 ps |
| T887 |
/workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1423809880 |
|
|
Mar 17 01:44:21 PM PDT 24 |
Mar 17 01:44:24 PM PDT 24 |
837738328 ps |
| T888 |
/workspace/coverage/default/8.pwrmgr_reset_invalid.2162799224 |
|
|
Mar 17 01:44:33 PM PDT 24 |
Mar 17 01:44:34 PM PDT 24 |
127960576 ps |
| T889 |
/workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1473999105 |
|
|
Mar 17 01:44:19 PM PDT 24 |
Mar 17 01:44:20 PM PDT 24 |
58340940 ps |
| T890 |
/workspace/coverage/default/12.pwrmgr_reset_invalid.3141293276 |
|
|
Mar 17 01:44:53 PM PDT 24 |
Mar 17 01:44:55 PM PDT 24 |
96216285 ps |
| T891 |
/workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.3360509909 |
|
|
Mar 17 01:44:09 PM PDT 24 |
Mar 17 01:44:10 PM PDT 24 |
291457039 ps |
| T892 |
/workspace/coverage/default/12.pwrmgr_wakeup.14986326 |
|
|
Mar 17 01:44:41 PM PDT 24 |
Mar 17 01:44:43 PM PDT 24 |
344165078 ps |
| T893 |
/workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.2246859697 |
|
|
Mar 17 01:44:56 PM PDT 24 |
Mar 17 01:44:58 PM PDT 24 |
123354361 ps |
| T894 |
/workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3011092365 |
|
|
Mar 17 01:45:35 PM PDT 24 |
Mar 17 01:45:38 PM PDT 24 |
854148364 ps |
| T895 |
/workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1992327282 |
|
|
Mar 17 01:44:17 PM PDT 24 |
Mar 17 01:44:17 PM PDT 24 |
33676463 ps |
| T896 |
/workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1470966904 |
|
|
Mar 17 01:45:24 PM PDT 24 |
Mar 17 01:45:25 PM PDT 24 |
66763010 ps |
| T897 |
/workspace/coverage/default/38.pwrmgr_glitch.2425815469 |
|
|
Mar 17 01:45:52 PM PDT 24 |
Mar 17 01:45:53 PM PDT 24 |
49931667 ps |
| T898 |
/workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3552415753 |
|
|
Mar 17 01:44:57 PM PDT 24 |
Mar 17 01:45:01 PM PDT 24 |
827307840 ps |
| T67 |
/workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.409849433 |
|
|
Mar 17 01:24:03 PM PDT 24 |
Mar 17 01:24:04 PM PDT 24 |
31129420 ps |
| T62 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.894386340 |
|
|
Mar 17 01:23:54 PM PDT 24 |
Mar 17 01:23:57 PM PDT 24 |
683066415 ps |
| T53 |
/workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2798855234 |
|
|
Mar 17 01:24:44 PM PDT 24 |
Mar 17 01:24:46 PM PDT 24 |
200903780 ps |
| T68 |
/workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3088431597 |
|
|
Mar 17 01:24:56 PM PDT 24 |
Mar 17 01:24:57 PM PDT 24 |
20078527 ps |
| T69 |
/workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1613833501 |
|
|
Mar 17 01:24:51 PM PDT 24 |
Mar 17 01:24:52 PM PDT 24 |
17801890 ps |
| T54 |
/workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1286112884 |
|
|
Mar 17 01:24:30 PM PDT 24 |
Mar 17 01:24:31 PM PDT 24 |
29848625 ps |
| T71 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.402853987 |
|
|
Mar 17 01:23:36 PM PDT 24 |
Mar 17 01:23:37 PM PDT 24 |
40366373 ps |
| T56 |
/workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.397188307 |
|
|
Mar 17 01:24:17 PM PDT 24 |
Mar 17 01:24:18 PM PDT 24 |
51615342 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1792253297 |
|
|
Mar 17 01:23:54 PM PDT 24 |
Mar 17 01:23:55 PM PDT 24 |
115742194 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1916639602 |
|
|
Mar 17 01:23:44 PM PDT 24 |
Mar 17 01:23:45 PM PDT 24 |
53949035 ps |
| T70 |
/workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1621309321 |
|
|
Mar 17 01:24:48 PM PDT 24 |
Mar 17 01:24:49 PM PDT 24 |
36560883 ps |
| T139 |
/workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3882989067 |
|
|
Mar 17 01:24:46 PM PDT 24 |
Mar 17 01:24:46 PM PDT 24 |
45218464 ps |
| T136 |
/workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1571247064 |
|
|
Mar 17 01:24:21 PM PDT 24 |
Mar 17 01:24:22 PM PDT 24 |
43165290 ps |
| T117 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2306057526 |
|
|
Mar 17 01:24:03 PM PDT 24 |
Mar 17 01:24:04 PM PDT 24 |
48058239 ps |
| T899 |
/workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3353035051 |
|
|
Mar 17 01:24:43 PM PDT 24 |
Mar 17 01:24:44 PM PDT 24 |
89255325 ps |
| T137 |
/workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3624997936 |
|
|
Mar 17 01:24:55 PM PDT 24 |
Mar 17 01:24:56 PM PDT 24 |
38097198 ps |
| T84 |
/workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2167488210 |
|
|
Mar 17 01:24:29 PM PDT 24 |
Mar 17 01:24:29 PM PDT 24 |
47146284 ps |
| T138 |
/workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1906693070 |
|
|
Mar 17 01:24:57 PM PDT 24 |
Mar 17 01:24:58 PM PDT 24 |
20288547 ps |
| T93 |
/workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3366408183 |
|
|
Mar 17 01:24:32 PM PDT 24 |
Mar 17 01:24:32 PM PDT 24 |
18594351 ps |
| T900 |
/workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.4235179050 |
|
|
Mar 17 01:24:55 PM PDT 24 |
Mar 17 01:24:56 PM PDT 24 |
45055684 ps |
| T94 |
/workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2040326674 |
|
|
Mar 17 01:24:18 PM PDT 24 |
Mar 17 01:24:19 PM PDT 24 |
30524632 ps |
| T65 |
/workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.661240415 |
|
|
Mar 17 01:24:46 PM PDT 24 |
Mar 17 01:24:47 PM PDT 24 |
197347242 ps |
| T111 |
/workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2262212448 |
|
|
Mar 17 01:24:15 PM PDT 24 |
Mar 17 01:24:15 PM PDT 24 |
286469159 ps |
| T901 |
/workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2023557610 |
|
|
Mar 17 01:24:35 PM PDT 24 |
Mar 17 01:24:36 PM PDT 24 |
21932948 ps |
| T55 |
/workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2383818209 |
|
|
Mar 17 01:24:34 PM PDT 24 |
Mar 17 01:24:36 PM PDT 24 |
124903680 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3676510630 |
|
|
Mar 17 01:23:44 PM PDT 24 |
Mar 17 01:23:45 PM PDT 24 |
77747677 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3747296441 |
|
|
Mar 17 01:23:43 PM PDT 24 |
Mar 17 01:23:45 PM PDT 24 |
200720181 ps |
| T902 |
/workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.1939968848 |
|
|
Mar 17 01:24:50 PM PDT 24 |
Mar 17 01:24:51 PM PDT 24 |
55241546 ps |
| T903 |
/workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.3068794386 |
|
|
Mar 17 01:25:00 PM PDT 24 |
Mar 17 01:25:00 PM PDT 24 |
49948141 ps |
| T904 |
/workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3583178916 |
|
|
Mar 17 01:24:03 PM PDT 24 |
Mar 17 01:24:04 PM PDT 24 |
28201639 ps |
| T112 |
/workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1514991882 |
|
|
Mar 17 01:24:44 PM PDT 24 |
Mar 17 01:24:45 PM PDT 24 |
82450009 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1606455593 |
|
|
Mar 17 01:24:42 PM PDT 24 |
Mar 17 01:24:45 PM PDT 24 |
246014861 ps |
| T113 |
/workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2681139278 |
|
|
Mar 17 01:24:51 PM PDT 24 |
Mar 17 01:24:52 PM PDT 24 |
68607958 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2782739928 |
|
|
Mar 17 01:23:40 PM PDT 24 |
Mar 17 01:23:41 PM PDT 24 |
44880629 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.344017531 |
|
|
Mar 17 01:23:25 PM PDT 24 |
Mar 17 01:23:27 PM PDT 24 |
107880174 ps |
| T115 |
/workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.334356824 |
|
|
Mar 17 01:24:38 PM PDT 24 |
Mar 17 01:24:40 PM PDT 24 |
33685550 ps |
| T116 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3225724307 |
|
|
Mar 17 01:23:30 PM PDT 24 |
Mar 17 01:23:31 PM PDT 24 |
27064838 ps |
| T96 |
/workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3838677093 |
|
|
Mar 17 01:24:35 PM PDT 24 |
Mar 17 01:24:36 PM PDT 24 |
55688888 ps |
| T141 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4250783670 |
|
|
Mar 17 01:23:49 PM PDT 24 |
Mar 17 01:23:51 PM PDT 24 |
623947695 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1519300549 |
|
|
Mar 17 01:23:35 PM PDT 24 |
Mar 17 01:23:37 PM PDT 24 |
82722317 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1271098124 |
|
|
Mar 17 01:24:34 PM PDT 24 |
Mar 17 01:24:35 PM PDT 24 |
58829348 ps |
| T140 |
/workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2601630658 |
|
|
Mar 17 01:24:15 PM PDT 24 |
Mar 17 01:24:16 PM PDT 24 |
20433188 ps |
| T905 |
/workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1403640921 |
|
|
Mar 17 01:24:49 PM PDT 24 |
Mar 17 01:24:50 PM PDT 24 |
17140949 ps |
| T906 |
/workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2156354907 |
|
|
Mar 17 01:24:54 PM PDT 24 |
Mar 17 01:24:54 PM PDT 24 |
54056352 ps |
| T142 |
/workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.394237634 |
|
|
Mar 17 01:24:57 PM PDT 24 |
Mar 17 01:24:58 PM PDT 24 |
62569862 ps |
| T98 |
/workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1350709552 |
|
|
Mar 17 01:24:37 PM PDT 24 |
Mar 17 01:24:38 PM PDT 24 |
42636218 ps |
| T907 |
/workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2731877467 |
|
|
Mar 17 01:23:25 PM PDT 24 |
Mar 17 01:23:26 PM PDT 24 |
45392624 ps |
| T75 |
/workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.829328176 |
|
|
Mar 17 01:24:30 PM PDT 24 |
Mar 17 01:24:31 PM PDT 24 |
56682359 ps |
| T908 |
/workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1921563757 |
|
|
Mar 17 01:24:02 PM PDT 24 |
Mar 17 01:24:03 PM PDT 24 |
395973572 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3265095210 |
|
|
Mar 17 01:24:04 PM PDT 24 |
Mar 17 01:24:06 PM PDT 24 |
861136468 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3525963841 |
|
|
Mar 17 01:24:04 PM PDT 24 |
Mar 17 01:24:05 PM PDT 24 |
16752623 ps |
| T909 |
/workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.19186175 |
|
|
Mar 17 01:24:55 PM PDT 24 |
Mar 17 01:24:56 PM PDT 24 |
45712130 ps |
| T910 |
/workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2205522315 |
|
|
Mar 17 01:23:36 PM PDT 24 |
Mar 17 01:23:38 PM PDT 24 |
46325065 ps |
| T123 |
/workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3808413258 |
|
|
Mar 17 01:24:43 PM PDT 24 |
Mar 17 01:24:44 PM PDT 24 |
27434502 ps |
| T57 |
/workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.639073063 |
|
|
Mar 17 01:24:43 PM PDT 24 |
Mar 17 01:24:45 PM PDT 24 |
108456163 ps |
| T911 |
/workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2062826865 |
|
|
Mar 17 01:24:34 PM PDT 24 |
Mar 17 01:24:35 PM PDT 24 |
50009626 ps |
| T912 |
/workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1911767925 |
|
|
Mar 17 01:24:11 PM PDT 24 |
Mar 17 01:24:13 PM PDT 24 |
48702288 ps |
| T913 |
/workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1942474722 |
|
|
Mar 17 01:24:05 PM PDT 24 |
Mar 17 01:24:06 PM PDT 24 |
141881544 ps |
| T914 |
/workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3609117274 |
|
|
Mar 17 01:24:55 PM PDT 24 |
Mar 17 01:24:56 PM PDT 24 |
17930371 ps |
| T124 |
/workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.408174015 |
|
|
Mar 17 01:24:35 PM PDT 24 |
Mar 17 01:24:38 PM PDT 24 |
1268586591 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1091781979 |
|
|
Mar 17 01:23:54 PM PDT 24 |
Mar 17 01:23:55 PM PDT 24 |
54146567 ps |
| T915 |
/workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.629540619 |
|
|
Mar 17 01:25:00 PM PDT 24 |
Mar 17 01:25:01 PM PDT 24 |
23717824 ps |
| T58 |
/workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.976061452 |
|
|
Mar 17 01:24:03 PM PDT 24 |
Mar 17 01:24:05 PM PDT 24 |
2096127163 ps |
| T916 |
/workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4105131803 |
|
|
Mar 17 01:24:34 PM PDT 24 |
Mar 17 01:24:34 PM PDT 24 |
36287291 ps |
| T129 |
/workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2300083758 |
|
|
Mar 17 01:23:40 PM PDT 24 |
Mar 17 01:23:41 PM PDT 24 |
144198287 ps |
| T917 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3717154103 |
|
|
Mar 17 01:23:54 PM PDT 24 |
Mar 17 01:23:55 PM PDT 24 |
127987825 ps |
| T918 |
/workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1466213254 |
|
|
Mar 17 01:25:01 PM PDT 24 |
Mar 17 01:25:02 PM PDT 24 |
26919430 ps |
| T919 |
/workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.267446462 |
|
|
Mar 17 01:24:58 PM PDT 24 |
Mar 17 01:24:59 PM PDT 24 |
34733313 ps |
| T920 |
/workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2880325456 |
|
|
Mar 17 01:24:59 PM PDT 24 |
Mar 17 01:24:59 PM PDT 24 |
19624759 ps |
| T921 |
/workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.4085726923 |
|
|
Mar 17 01:23:54 PM PDT 24 |
Mar 17 01:23:55 PM PDT 24 |
20351247 ps |
| T922 |
/workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1495915830 |
|
|
Mar 17 01:24:28 PM PDT 24 |
Mar 17 01:24:28 PM PDT 24 |
104657913 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.481899975 |
|
|
Mar 17 01:23:36 PM PDT 24 |
Mar 17 01:23:38 PM PDT 24 |
769461169 ps |
| T923 |
/workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1196512572 |
|
|
Mar 17 01:23:30 PM PDT 24 |
Mar 17 01:23:31 PM PDT 24 |
172162263 ps |
| T102 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.932497209 |
|
|
Mar 17 01:24:06 PM PDT 24 |
Mar 17 01:24:07 PM PDT 24 |
167611768 ps |
| T924 |
/workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.110855898 |
|
|
Mar 17 01:24:15 PM PDT 24 |
Mar 17 01:24:17 PM PDT 24 |
44936798 ps |
| T925 |
/workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3935849222 |
|
|
Mar 17 01:24:04 PM PDT 24 |
Mar 17 01:24:05 PM PDT 24 |
37731804 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.764334642 |
|
|
Mar 17 01:23:51 PM PDT 24 |
Mar 17 01:23:52 PM PDT 24 |
159562682 ps |
| T926 |
/workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2469691788 |
|
|
Mar 17 01:24:32 PM PDT 24 |
Mar 17 01:24:32 PM PDT 24 |
355249347 ps |
| T927 |
/workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.857438142 |
|
|
Mar 17 01:24:14 PM PDT 24 |
Mar 17 01:24:16 PM PDT 24 |
85127603 ps |
| T928 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1616936926 |
|
|
Mar 17 01:24:05 PM PDT 24 |
Mar 17 01:24:06 PM PDT 24 |
58811381 ps |
| T104 |
/workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1797963774 |
|
|
Mar 17 01:24:44 PM PDT 24 |
Mar 17 01:24:45 PM PDT 24 |
51547160 ps |
| T929 |
/workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1070053803 |
|
|
Mar 17 01:24:56 PM PDT 24 |
Mar 17 01:24:57 PM PDT 24 |
41011970 ps |
| T105 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3827828658 |
|
|
Mar 17 01:23:47 PM PDT 24 |
Mar 17 01:23:48 PM PDT 24 |
18173620 ps |
| T130 |
/workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.728573954 |
|
|
Mar 17 01:24:14 PM PDT 24 |
Mar 17 01:24:16 PM PDT 24 |
114516625 ps |
| T930 |
/workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.662095366 |
|
|
Mar 17 01:24:34 PM PDT 24 |
Mar 17 01:24:36 PM PDT 24 |
110299520 ps |
| T931 |
/workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.758774266 |
|
|
Mar 17 01:24:15 PM PDT 24 |
Mar 17 01:24:16 PM PDT 24 |
61643478 ps |
| T932 |
/workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.991872982 |
|
|
Mar 17 01:24:15 PM PDT 24 |
Mar 17 01:24:16 PM PDT 24 |
131658496 ps |
| T933 |
/workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.946724847 |
|
|
Mar 17 01:24:39 PM PDT 24 |
Mar 17 01:24:40 PM PDT 24 |
248199662 ps |
| T934 |
/workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1089447544 |
|
|
Mar 17 01:24:10 PM PDT 24 |
Mar 17 01:24:12 PM PDT 24 |
41336223 ps |
| T935 |
/workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1134579613 |
|
|
Mar 17 01:23:35 PM PDT 24 |
Mar 17 01:23:37 PM PDT 24 |
96399840 ps |
| T936 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2871176474 |
|
|
Mar 17 01:23:53 PM PDT 24 |
Mar 17 01:23:54 PM PDT 24 |
67783317 ps |
| T937 |
/workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.4207469202 |
|
|
Mar 17 01:24:44 PM PDT 24 |
Mar 17 01:24:45 PM PDT 24 |
140221262 ps |
| T938 |
/workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.1151195381 |
|
|
Mar 17 01:24:10 PM PDT 24 |
Mar 17 01:24:10 PM PDT 24 |
21416666 ps |
| T939 |
/workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1888792493 |
|
|
Mar 17 01:24:56 PM PDT 24 |
Mar 17 01:24:57 PM PDT 24 |
32172387 ps |
| T940 |
/workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.4245756452 |
|
|
Mar 17 01:24:49 PM PDT 24 |
Mar 17 01:24:50 PM PDT 24 |
53951519 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1811723074 |
|
|
Mar 17 01:24:09 PM PDT 24 |
Mar 17 01:24:10 PM PDT 24 |
50587617 ps |
| T942 |
/workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1669437683 |
|
|
Mar 17 01:24:12 PM PDT 24 |
Mar 17 01:24:14 PM PDT 24 |
120926512 ps |
| T943 |
/workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1178141264 |
|
|
Mar 17 01:24:29 PM PDT 24 |
Mar 17 01:24:31 PM PDT 24 |
113123088 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.2404394771 |
|
|
Mar 17 01:24:39 PM PDT 24 |
Mar 17 01:24:41 PM PDT 24 |
181076651 ps |
| T106 |
/workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3395590970 |
|
|
Mar 17 01:24:42 PM PDT 24 |
Mar 17 01:24:43 PM PDT 24 |
19592820 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3798970542 |
|
|
Mar 17 01:23:48 PM PDT 24 |
Mar 17 01:23:50 PM PDT 24 |
469187957 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.127490481 |
|
|
Mar 17 01:23:24 PM PDT 24 |
Mar 17 01:23:25 PM PDT 24 |
29954663 ps |
| T946 |
/workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1372679347 |
|
|
Mar 17 01:24:40 PM PDT 24 |
Mar 17 01:24:41 PM PDT 24 |
66847184 ps |
| T947 |
/workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3917273538 |
|
|
Mar 17 01:24:48 PM PDT 24 |
Mar 17 01:24:49 PM PDT 24 |
18531794 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2481840185 |
|
|
Mar 17 01:23:41 PM PDT 24 |
Mar 17 01:23:42 PM PDT 24 |
33569180 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3461292772 |
|
|
Mar 17 01:24:28 PM PDT 24 |
Mar 17 01:24:31 PM PDT 24 |
773998321 ps |
| T950 |
/workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3716598114 |
|
|
Mar 17 01:24:11 PM PDT 24 |
Mar 17 01:24:13 PM PDT 24 |
41367642 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.20659598 |
|
|
Mar 17 01:23:36 PM PDT 24 |
Mar 17 01:23:37 PM PDT 24 |
22826399 ps |
| T952 |
/workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1278913070 |
|
|
Mar 17 01:24:24 PM PDT 24 |
Mar 17 01:24:24 PM PDT 24 |
21441459 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.58498531 |
|
|
Mar 17 01:24:45 PM PDT 24 |
Mar 17 01:24:46 PM PDT 24 |
20058405 ps |
| T954 |
/workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3467818559 |
|
|
Mar 17 01:24:54 PM PDT 24 |
Mar 17 01:24:55 PM PDT 24 |
29438546 ps |
| T955 |
/workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1137654955 |
|
|
Mar 17 01:24:58 PM PDT 24 |
Mar 17 01:24:59 PM PDT 24 |
16853937 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1063036811 |
|
|
Mar 17 01:23:55 PM PDT 24 |
Mar 17 01:23:56 PM PDT 24 |
221472609 ps |
| T957 |
/workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3789828498 |
|
|
Mar 17 01:24:39 PM PDT 24 |
Mar 17 01:24:41 PM PDT 24 |
364063572 ps |
| T72 |
/workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2206747218 |
|
|
Mar 17 01:24:41 PM PDT 24 |
Mar 17 01:24:43 PM PDT 24 |
191093347 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2996569368 |
|
|
Mar 17 01:23:50 PM PDT 24 |
Mar 17 01:23:51 PM PDT 24 |
64265495 ps |
| T959 |
/workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3645955398 |
|
|
Mar 17 01:24:50 PM PDT 24 |
Mar 17 01:24:51 PM PDT 24 |
20728228 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.849227080 |
|
|
Mar 17 01:24:11 PM PDT 24 |
Mar 17 01:24:12 PM PDT 24 |
47608643 ps |
| T961 |
/workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3244605137 |
|
|
Mar 17 01:24:52 PM PDT 24 |
Mar 17 01:24:53 PM PDT 24 |
183360573 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.149358394 |
|
|
Mar 17 01:23:49 PM PDT 24 |
Mar 17 01:23:50 PM PDT 24 |
59820011 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.4002741600 |
|
|
Mar 17 01:24:24 PM PDT 24 |
Mar 17 01:24:25 PM PDT 24 |
207058553 ps |
| T964 |
/workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3646143834 |
|
|
Mar 17 01:25:03 PM PDT 24 |
Mar 17 01:25:04 PM PDT 24 |
51597364 ps |
| T965 |
/workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.406600038 |
|
|
Mar 17 01:24:59 PM PDT 24 |
Mar 17 01:25:00 PM PDT 24 |
82492091 ps |
| T966 |
/workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.119040301 |
|
|
Mar 17 01:24:43 PM PDT 24 |
Mar 17 01:24:45 PM PDT 24 |
344269733 ps |
| T967 |
/workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4206507305 |
|
|
Mar 17 01:24:43 PM PDT 24 |
Mar 17 01:24:44 PM PDT 24 |
50508864 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1408252727 |
|
|
Mar 17 01:23:30 PM PDT 24 |
Mar 17 01:23:32 PM PDT 24 |
48693167 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2137921007 |
|
|
Mar 17 01:24:08 PM PDT 24 |
Mar 17 01:24:10 PM PDT 24 |
147949900 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1534225779 |
|
|
Mar 17 01:24:03 PM PDT 24 |
Mar 17 01:24:05 PM PDT 24 |
178279823 ps |
| T970 |
/workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.797978859 |
|
|
Mar 17 01:24:54 PM PDT 24 |
Mar 17 01:24:55 PM PDT 24 |
41787701 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1687125469 |
|
|
Mar 17 01:24:30 PM PDT 24 |
Mar 17 01:24:31 PM PDT 24 |
41595359 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1501214307 |
|
|
Mar 17 01:24:05 PM PDT 24 |
Mar 17 01:24:08 PM PDT 24 |
599368336 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3136127142 |
|
|
Mar 17 01:24:51 PM PDT 24 |
Mar 17 01:24:51 PM PDT 24 |
17457818 ps |
| T974 |
/workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3783327841 |
|
|
Mar 17 01:24:50 PM PDT 24 |
Mar 17 01:24:51 PM PDT 24 |
61962058 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1556717432 |
|
|
Mar 17 01:24:03 PM PDT 24 |
Mar 17 01:24:04 PM PDT 24 |
45109854 ps |
| T108 |
/workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3876519021 |
|
|
Mar 17 01:24:22 PM PDT 24 |
Mar 17 01:24:23 PM PDT 24 |
22391242 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1725668980 |
|
|
Mar 17 01:24:17 PM PDT 24 |
Mar 17 01:24:18 PM PDT 24 |
583133457 ps |
| T977 |
/workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.882152280 |
|
|
Mar 17 01:24:22 PM PDT 24 |
Mar 17 01:24:24 PM PDT 24 |
81260684 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.82491919 |
|
|
Mar 17 01:24:28 PM PDT 24 |
Mar 17 01:24:29 PM PDT 24 |
909022987 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1944426514 |
|
|
Mar 17 01:24:24 PM PDT 24 |
Mar 17 01:24:25 PM PDT 24 |
44957923 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2979227338 |
|
|
Mar 17 01:24:06 PM PDT 24 |
Mar 17 01:24:07 PM PDT 24 |
71902852 ps |
| T981 |
/workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.607379306 |
|
|
Mar 17 01:24:15 PM PDT 24 |
Mar 17 01:24:17 PM PDT 24 |
271146302 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4020127031 |
|
|
Mar 17 01:23:36 PM PDT 24 |
Mar 17 01:23:37 PM PDT 24 |
21459318 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.54508691 |
|
|
Mar 17 01:24:16 PM PDT 24 |
Mar 17 01:24:18 PM PDT 24 |
366383098 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3744512678 |
|
|
Mar 17 01:24:08 PM PDT 24 |
Mar 17 01:24:09 PM PDT 24 |
45949455 ps |
| T985 |
/workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1006605898 |
|
|
Mar 17 01:24:49 PM PDT 24 |
Mar 17 01:24:51 PM PDT 24 |
149923906 ps |
| T986 |
/workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2417506704 |
|
|
Mar 17 01:24:35 PM PDT 24 |
Mar 17 01:24:36 PM PDT 24 |
21962536 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1100794922 |
|
|
Mar 17 01:23:41 PM PDT 24 |
Mar 17 01:23:42 PM PDT 24 |
172815882 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2464436342 |
|
|
Mar 17 01:23:25 PM PDT 24 |
Mar 17 01:23:26 PM PDT 24 |
106038959 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2487134819 |
|
|
Mar 17 01:23:30 PM PDT 24 |
Mar 17 01:23:31 PM PDT 24 |
125562578 ps |
| T989 |
/workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2852270305 |
|
|
Mar 17 01:24:42 PM PDT 24 |
Mar 17 01:24:43 PM PDT 24 |
156146458 ps |
| T990 |
/workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2550334646 |
|
|
Mar 17 01:24:11 PM PDT 24 |
Mar 17 01:24:12 PM PDT 24 |
43482636 ps |
| T991 |
/workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3422805732 |
|
|
Mar 17 01:24:55 PM PDT 24 |
Mar 17 01:24:55 PM PDT 24 |
55273498 ps |
| T992 |
/workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3941600378 |
|
|
Mar 17 01:24:28 PM PDT 24 |
Mar 17 01:24:29 PM PDT 24 |
62781206 ps |
| T993 |
/workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1290770151 |
|
|
Mar 17 01:24:59 PM PDT 24 |
Mar 17 01:24:59 PM PDT 24 |
24864802 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3393138599 |
|
|
Mar 17 01:24:27 PM PDT 24 |
Mar 17 01:24:28 PM PDT 24 |
100116979 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3897938820 |
|
|
Mar 17 01:24:15 PM PDT 24 |
Mar 17 01:24:16 PM PDT 24 |
44656986 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2228691810 |
|
|
Mar 17 01:24:09 PM PDT 24 |
Mar 17 01:24:10 PM PDT 24 |
218022691 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1581493597 |
|
|
Mar 17 01:24:22 PM PDT 24 |
Mar 17 01:24:23 PM PDT 24 |
50080232 ps |
| T998 |
/workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.890989901 |
|
|
Mar 17 01:24:50 PM PDT 24 |
Mar 17 01:24:51 PM PDT 24 |
31196461 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2720202535 |
|
|
Mar 17 01:24:49 PM PDT 24 |
Mar 17 01:24:50 PM PDT 24 |
42098889 ps |
| T1000 |
/workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1820966008 |
|
|
Mar 17 01:24:09 PM PDT 24 |
Mar 17 01:24:10 PM PDT 24 |
96999024 ps |