Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.90	98.23	96.43	99.44	96.00	96.37	100.00	98.85

Total test records in report: 1004

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1157254280			Mar 17 01:24:55 PM PDT 24	Mar 17 01:24:56 PM PDT 24	17707482 ps
T1002	/workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3699840727			Mar 17 01:24:39 PM PDT 24	Mar 17 01:24:41 PM PDT 24	43420156 ps
T1003	/workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4190559718			Mar 17 01:24:50 PM PDT 24	Mar 17 01:24:51 PM PDT 24	213757527 ps
T1004	/workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.4283517082			Mar 17 01:24:22 PM PDT 24	Mar 17 01:24:24 PM PDT 24	145743380 ps

Test location	/workspace/coverage/default/49.pwrmgr_wakeup_reset.966212656
Short name	T4
Test name
Test status
Simulation time	285397194 ps
CPU time	0.91 seconds
Started	Mar 17 01:46:15 PM PDT 24
Finished	Mar 17 01:46:16 PM PDT 24
Peak memory	199464 kb
Host	smart-c4412308-602b-4eec-b55a-618bae09020c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966212656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.966212656
Directory	/workspace/49.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/4.pwrmgr_reset_invalid.1782496196
Short name	T41
Test name
Test status
Simulation time	272612916 ps
CPU time	0.77 seconds
Started	Mar 17 01:44:14 PM PDT 24
Finished	Mar 17 01:44:15 PM PDT 24
Peak memory	208984 kb
Host	smart-34d5de20-f03a-4447-808d-6e2a7789ada7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782496196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1782496196
Directory	/workspace/4.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.227934522
Short name	T27
Test name
Test status
Simulation time	759726023 ps
CPU time	3.08 seconds
Started	Mar 17 01:45:11 PM PDT 24
Finished	Mar 17 01:45:14 PM PDT 24
Peak memory	200556 kb
Host	smart-142fa05e-0452-4ddd-ab6f-f3b297a06d51
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227934522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.227934522
Directory	/workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.1859776064
Short name	T23
Test name
Test status
Simulation time	40417728521 ps
CPU time	18.03 seconds
Started	Mar 17 01:44:16 PM PDT 24
Finished	Mar 17 01:44:34 PM PDT 24
Peak memory	200724 kb
Host	smart-666944d9-000f-4fac-80a2-6fc4da19b185
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859776064 -assert nopos tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.1859776064
Directory	/workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.pwrmgr_sec_cm.839211901
Short name	T21
Test name
Test status
Simulation time	604594923 ps
CPU time	1.88 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	217076 kb
Host	smart-ed3ee2f9-1a9e-451e-a7ea-dd48ed9ab232
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839211901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.839211901
Directory	/workspace/1.pwrmgr_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2798855234
Short name	T53
Test name
Test status
Simulation time	200903780 ps
CPU time	1.74 seconds
Started	Mar 17 01:24:44 PM PDT 24
Finished	Mar 17 01:24:46 PM PDT 24
Peak memory	195124 kb
Host	smart-0fa28517-e4fd-489e-88a5-735237e937a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798855234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er r.2798855234
Directory	/workspace/17.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/47.pwrmgr_lowpower_invalid.1905710844
Short name	T49
Test name
Test status
Simulation time	72766374 ps
CPU time	0.72 seconds
Started	Mar 17 01:46:23 PM PDT 24
Finished	Mar 17 01:46:24 PM PDT 24
Peak memory	200780 kb
Host	smart-62943427-71a0-43ae-ae9b-7ab92450c801
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905710844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval id.1905710844
Directory	/workspace/47.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.3921139068
Short name	T43
Test name
Test status
Simulation time	280699178 ps
CPU time	1.16 seconds
Started	Mar 17 01:45:17 PM PDT 24
Finished	Mar 17 01:45:19 PM PDT 24
Peak memory	200264 kb
Host	smart-45570e80-7b5b-46a7-9686-ef803e03e8d0
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921139068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_ cm_ctrl_config_regwen.3921139068
Directory	/workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3747296441
Short name	T60
Test name
Test status
Simulation time	200720181 ps
CPU time	1.96 seconds
Started	Mar 17 01:23:43 PM PDT 24
Finished	Mar 17 01:23:45 PM PDT 24
Peak memory	196480 kb
Host	smart-90676fb6-6013-43d7-abc1-dc0dd7d33175
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747296441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3747296441
Directory	/workspace/2.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2215075446
Short name	T52
Test name
Test status
Simulation time	2531586176 ps
CPU time	2.02 seconds
Started	Mar 17 01:45:21 PM PDT 24
Finished	Mar 17 01:45:23 PM PDT 24
Peak memory	200612 kb
Host	smart-450d3dbe-103e-489c-b6e2-5bc6add930a7
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215075446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2215075446
Directory	/workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1571247064
Short name	T136
Test name
Test status
Simulation time	43165290 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:21 PM PDT 24
Finished	Mar 17 01:24:22 PM PDT 24
Peak memory	194976 kb
Host	smart-c0107a60-767c-405b-87bc-52da5c1394aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571247064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1571247064
Directory	/workspace/8.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.402853987
Short name	T71
Test name
Test status
Simulation time	40366373 ps
CPU time	0.65 seconds
Started	Mar 17 01:23:36 PM PDT 24
Finished	Mar 17 01:23:37 PM PDT 24
Peak memory	198312 kb
Host	smart-aa6fef57-3a6a-4be2-b387-d5746e518ef8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402853987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.402853987
Directory	/workspace/1.pwrmgr_csr_hw_reset/latest

Test location	/workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.505426118
Short name	T125
Test name
Test status
Simulation time	54913227 ps
CPU time	0.89 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	199344 kb
Host	smart-c1672202-bec3-431b-a0a3-ab70b3e53ce5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505426118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disab le_rom_integrity_check.505426118
Directory	/workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/11.pwrmgr_escalation_timeout.872355311
Short name	T3
Test name
Test status
Simulation time	166197801 ps
CPU time	0.99 seconds
Started	Mar 17 01:44:47 PM PDT 24
Finished	Mar 17 01:44:48 PM PDT 24
Peak memory	197536 kb
Host	smart-06b0040f-4af5-4509-91fc-708dbe0fa196
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872355311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.872355311
Directory	/workspace/11.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.764334642
Short name	T103
Test name
Test status
Simulation time	159562682 ps
CPU time	1.02 seconds
Started	Mar 17 01:23:51 PM PDT 24
Finished	Mar 17 01:23:52 PM PDT 24
Peak memory	198576 kb
Host	smart-afbbd2e2-ac19-4962-80b8-f1cbb5b9db29
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764334642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.764334642
Directory	/workspace/2.pwrmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.639073063
Short name	T57
Test name
Test status
Simulation time	108456163 ps
CPU time	1.18 seconds
Started	Mar 17 01:24:43 PM PDT 24
Finished	Mar 17 01:24:45 PM PDT 24
Peak memory	200108 kb
Host	smart-f787fafc-d6ef-424f-82bb-a303aa638ad0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639073063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err .639073063
Directory	/workspace/18.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.735858372
Short name	T12
Test name
Test status
Simulation time	65241633 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198508 kb
Host	smart-2b4d9326-c440-4bc9-bda8-d0b2d4967e6b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735858372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa ble_rom_integrity_check.735858372
Directory	/workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3225724307
Short name	T116
Test name
Test status
Simulation time	27064838 ps
CPU time	0.61 seconds
Started	Mar 17 01:23:30 PM PDT 24
Finished	Mar 17 01:23:31 PM PDT 24
Peak memory	197252 kb
Host	smart-75913528-c3a0-4279-a8b3-152973e72e2e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225724307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3225724307
Directory	/workspace/0.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2464436342
Short name	T988
Test name
Test status
Simulation time	106038959 ps
CPU time	1.2 seconds
Started	Mar 17 01:23:25 PM PDT 24
Finished	Mar 17 01:23:26 PM PDT 24
Peak memory	195148 kb
Host	smart-98bb6e6c-91a3-4fd9-b935-5b41beca304e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464436342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err .2464436342
Directory	/workspace/0.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2023557610
Short name	T901
Test name
Test status
Simulation time	21932948 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:35 PM PDT 24
Finished	Mar 17 01:24:36 PM PDT 24
Peak memory	194924 kb
Host	smart-adbe4b60-e344-4609-8f92-7dcd57610b38
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023557610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2023557610
Directory	/workspace/13.pwrmgr_intr_test/latest

Test location	/workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3203171906
Short name	T278
Test name
Test status
Simulation time	1261086191 ps
CPU time	2.41 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	200544 kb
Host	smart-bd6696d0-3618-4942-a86a-d03076917af4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203171906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3203171906
Directory	/workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.3139958965
Short name	T133
Test name
Test status
Simulation time	83152581 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:40 PM PDT 24
Finished	Mar 17 01:44:41 PM PDT 24
Peak memory	197892 kb
Host	smart-7b0db7ff-9566-43fe-b50a-8a0d1116721d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139958965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis able_rom_integrity_check.3139958965
Directory	/workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1519300549
Short name	T74
Test name
Test status
Simulation time	82722317 ps
CPU time	1.7 seconds
Started	Mar 17 01:23:35 PM PDT 24
Finished	Mar 17 01:23:37 PM PDT 24
Peak memory	197196 kb
Host	smart-19fd4b5f-3544-49c1-b529-438a219d3a20
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519300549 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1519300549
Directory	/workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/1.pwrmgr_glitch.1708640699
Short name	T191
Test name
Test status
Simulation time	79511146 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:06 PM PDT 24
Finished	Mar 17 01:44:07 PM PDT 24
Peak memory	197464 kb
Host	smart-2c40e866-3ad7-4bba-9c57-878e1bdd301c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708640699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1708640699
Directory	/workspace/1.pwrmgr_glitch/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2487134819
Short name	T109
Test name
Test status
Simulation time	125562578 ps
CPU time	1 seconds
Started	Mar 17 01:23:30 PM PDT 24
Finished	Mar 17 01:23:31 PM PDT 24
Peak memory	194996 kb
Host	smart-9ad788b6-9f6a-43d0-b562-3cfeb3714b3a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487134819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2 487134819
Directory	/workspace/0.pwrmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1408252727
Short name	T968
Test name
Test status
Simulation time	48693167 ps
CPU time	1.68 seconds
Started	Mar 17 01:23:30 PM PDT 24
Finished	Mar 17 01:23:32 PM PDT 24
Peak memory	195056 kb
Host	smart-c8441b29-ae66-4ced-aef5-c1743dafa242
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408252727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.1 408252727
Directory	/workspace/0.pwrmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.127490481
Short name	T107
Test name
Test status
Simulation time	29954663 ps
CPU time	0.62 seconds
Started	Mar 17 01:23:24 PM PDT 24
Finished	Mar 17 01:23:25 PM PDT 24
Peak memory	195028 kb
Host	smart-bbe931d9-0af9-473f-a711-8efe470d9bf1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127490481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.127490481
Directory	/workspace/0.pwrmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2731877467
Short name	T907
Test name
Test status
Simulation time	45392624 ps
CPU time	0.62 seconds
Started	Mar 17 01:23:25 PM PDT 24
Finished	Mar 17 01:23:26 PM PDT 24
Peak memory	194996 kb
Host	smart-3d69864a-2de5-4b45-b5a3-7edf410059fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731877467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2731877467
Directory	/workspace/0.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1196512572
Short name	T923
Test name
Test status
Simulation time	172162263 ps
CPU time	0.77 seconds
Started	Mar 17 01:23:30 PM PDT 24
Finished	Mar 17 01:23:31 PM PDT 24
Peak memory	197280 kb
Host	smart-a277384b-802b-4259-bdd7-531d5cd0e270
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196512572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa me_csr_outstanding.1196512572
Directory	/workspace/0.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.344017531
Short name	T76
Test name
Test status
Simulation time	107880174 ps
CPU time	2.19 seconds
Started	Mar 17 01:23:25 PM PDT 24
Finished	Mar 17 01:23:27 PM PDT 24
Peak memory	196280 kb
Host	smart-95419aaf-1235-44af-8fa9-779d37349115
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344017531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.344017531
Directory	/workspace/0.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1100794922
Short name	T987
Test name
Test status
Simulation time	172815882 ps
CPU time	1 seconds
Started	Mar 17 01:23:41 PM PDT 24
Finished	Mar 17 01:23:42 PM PDT 24
Peak memory	198672 kb
Host	smart-0408ebe5-4569-4852-98e0-589b907c7047
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100794922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1 100794922
Directory	/workspace/1.pwrmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.481899975
Short name	T101
Test name
Test status
Simulation time	769461169 ps
CPU time	2.02 seconds
Started	Mar 17 01:23:36 PM PDT 24
Finished	Mar 17 01:23:38 PM PDT 24
Peak memory	195116 kb
Host	smart-028bd12e-bb5c-4ce9-b35c-e1474dc85fa0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481899975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.481899975
Directory	/workspace/1.pwrmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1916639602
Short name	T59
Test name
Test status
Simulation time	53949035 ps
CPU time	1.09 seconds
Started	Mar 17 01:23:44 PM PDT 24
Finished	Mar 17 01:23:45 PM PDT 24
Peak memory	196136 kb
Host	smart-633e00b9-758a-4c73-b8a8-f967ea5223fa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916639602 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1916639602
Directory	/workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4020127031
Short name	T982
Test name
Test status
Simulation time	21459318 ps
CPU time	0.61 seconds
Started	Mar 17 01:23:36 PM PDT 24
Finished	Mar 17 01:23:37 PM PDT 24
Peak memory	195052 kb
Host	smart-32ea98e2-eeec-416e-9e1a-9f22642eae0f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020127031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.4020127031
Directory	/workspace/1.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.20659598
Short name	T951
Test name
Test status
Simulation time	22826399 ps
CPU time	0.61 seconds
Started	Mar 17 01:23:36 PM PDT 24
Finished	Mar 17 01:23:37 PM PDT 24
Peak memory	195016 kb
Host	smart-0b75b003-a933-4eb3-9c4c-7d328c16f65b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.20659598
Directory	/workspace/1.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2782739928
Short name	T114
Test name
Test status
Simulation time	44880629 ps
CPU time	0.92 seconds
Started	Mar 17 01:23:40 PM PDT 24
Finished	Mar 17 01:23:41 PM PDT 24
Peak memory	195012 kb
Host	smart-6fb31b59-b723-4094-9e7d-29efcf33b8d5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782739928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa me_csr_outstanding.2782739928
Directory	/workspace/1.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2205522315
Short name	T910
Test name
Test status
Simulation time	46325065 ps
CPU time	2.27 seconds
Started	Mar 17 01:23:36 PM PDT 24
Finished	Mar 17 01:23:38 PM PDT 24
Peak memory	196512 kb
Host	smart-aedbf755-97da-40d2-b301-721ec5eddb95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205522315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2205522315
Directory	/workspace/1.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1134579613
Short name	T935
Test name
Test status
Simulation time	96399840 ps
CPU time	1.1 seconds
Started	Mar 17 01:23:35 PM PDT 24
Finished	Mar 17 01:23:37 PM PDT 24
Peak memory	199944 kb
Host	smart-922a0af1-7643-443b-ba60-6a8a4b896f2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134579613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err .1134579613
Directory	/workspace/1.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.882152280
Short name	T977
Test name
Test status
Simulation time	81260684 ps
CPU time	0.97 seconds
Started	Mar 17 01:24:22 PM PDT 24
Finished	Mar 17 01:24:24 PM PDT 24
Peak memory	195112 kb
Host	smart-238a0720-836c-4a66-92de-37b27f1b9aed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882152280 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.882152280
Directory	/workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3876519021
Short name	T108
Test name
Test status
Simulation time	22391242 ps
CPU time	0.66 seconds
Started	Mar 17 01:24:22 PM PDT 24
Finished	Mar 17 01:24:23 PM PDT 24
Peak memory	195120 kb
Host	smart-c0e763f0-f021-421c-a0a8-acad92361a50
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876519021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3876519021
Directory	/workspace/10.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1278913070
Short name	T952
Test name
Test status
Simulation time	21441459 ps
CPU time	0.64 seconds
Started	Mar 17 01:24:24 PM PDT 24
Finished	Mar 17 01:24:24 PM PDT 24
Peak memory	194952 kb
Host	smart-7a02eb5d-0ce1-4af4-9280-29af8bd2c779
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278913070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.1278913070
Directory	/workspace/10.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1944426514
Short name	T979
Test name
Test status
Simulation time	44957923 ps
CPU time	0.93 seconds
Started	Mar 17 01:24:24 PM PDT 24
Finished	Mar 17 01:24:25 PM PDT 24
Peak memory	199700 kb
Host	smart-7aa392ef-8a54-43e6-a853-c51a79087e49
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944426514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s ame_csr_outstanding.1944426514
Directory	/workspace/10.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.857438142
Short name	T927
Test name
Test status
Simulation time	85127603 ps
CPU time	1.95 seconds
Started	Mar 17 01:24:14 PM PDT 24
Finished	Mar 17 01:24:16 PM PDT 24
Peak memory	196316 kb
Host	smart-c36e93cb-4828-4e58-a1f5-105b50d1393c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857438142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.857438142
Directory	/workspace/10.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.4002741600
Short name	T963
Test name
Test status
Simulation time	207058553 ps
CPU time	1.02 seconds
Started	Mar 17 01:24:24 PM PDT 24
Finished	Mar 17 01:24:25 PM PDT 24
Peak memory	200076 kb
Host	smart-3482ac1e-8161-4343-ac96-a7710499f36c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002741600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er r.4002741600
Directory	/workspace/10.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2167488210
Short name	T84
Test name
Test status
Simulation time	47146284 ps
CPU time	0.72 seconds
Started	Mar 17 01:24:29 PM PDT 24
Finished	Mar 17 01:24:29 PM PDT 24
Peak memory	195096 kb
Host	smart-aa01e1dc-7002-4462-b044-f26e8b2e6a23
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167488210 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.2167488210
Directory	/workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3941600378
Short name	T992
Test name
Test status
Simulation time	62781206 ps
CPU time	0.64 seconds
Started	Mar 17 01:24:28 PM PDT 24
Finished	Mar 17 01:24:29 PM PDT 24
Peak memory	196300 kb
Host	smart-08da21d8-f13d-44e0-92be-8409798f4461
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941600378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3941600378
Directory	/workspace/11.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1495915830
Short name	T922
Test name
Test status
Simulation time	104657913 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:28 PM PDT 24
Finished	Mar 17 01:24:28 PM PDT 24
Peak memory	194948 kb
Host	smart-1d8c0309-6fdd-443e-a860-26bc3ca3c437
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495915830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1495915830
Directory	/workspace/11.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1687125469
Short name	T971
Test name
Test status
Simulation time	41595359 ps
CPU time	0.74 seconds
Started	Mar 17 01:24:30 PM PDT 24
Finished	Mar 17 01:24:31 PM PDT 24
Peak memory	197276 kb
Host	smart-236da00a-821a-4884-9fd2-394753d0775f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687125469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s ame_csr_outstanding.1687125469
Directory	/workspace/11.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1581493597
Short name	T997
Test name
Test status
Simulation time	50080232 ps
CPU time	1.28 seconds
Started	Mar 17 01:24:22 PM PDT 24
Finished	Mar 17 01:24:23 PM PDT 24
Peak memory	197204 kb
Host	smart-277d05d2-b3cb-4675-b97b-82bb3b2db81d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581493597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1581493597
Directory	/workspace/11.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.4283517082
Short name	T1004
Test name
Test status
Simulation time	145743380 ps
CPU time	1.16 seconds
Started	Mar 17 01:24:22 PM PDT 24
Finished	Mar 17 01:24:24 PM PDT 24
Peak memory	195192 kb
Host	smart-7848e312-9653-49d1-b689-a6190f2e8098
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283517082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er r.4283517082
Directory	/workspace/11.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.829328176
Short name	T75
Test name
Test status
Simulation time	56682359 ps
CPU time	0.82 seconds
Started	Mar 17 01:24:30 PM PDT 24
Finished	Mar 17 01:24:31 PM PDT 24
Peak memory	195076 kb
Host	smart-577a3d70-01fa-485f-a56c-82df0baf51d0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829328176 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.829328176
Directory	/workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3366408183
Short name	T93
Test name
Test status
Simulation time	18594351 ps
CPU time	0.66 seconds
Started	Mar 17 01:24:32 PM PDT 24
Finished	Mar 17 01:24:32 PM PDT 24
Peak memory	197284 kb
Host	smart-c50badcb-e15c-4af0-a4c1-da208b149313
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366408183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.3366408183
Directory	/workspace/12.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3393138599
Short name	T994
Test name
Test status
Simulation time	100116979 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:27 PM PDT 24
Finished	Mar 17 01:24:28 PM PDT 24
Peak memory	194972 kb
Host	smart-b13a5ffe-58cf-403b-af5b-f8b3e11952ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393138599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3393138599
Directory	/workspace/12.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2469691788
Short name	T926
Test name
Test status
Simulation time	355249347 ps
CPU time	0.79 seconds
Started	Mar 17 01:24:32 PM PDT 24
Finished	Mar 17 01:24:32 PM PDT 24
Peak memory	197292 kb
Host	smart-e320267b-f8ef-4405-bbd0-db21d752d33a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469691788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s ame_csr_outstanding.2469691788
Directory	/workspace/12.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1286112884
Short name	T54
Test name
Test status
Simulation time	29848625 ps
CPU time	1.32 seconds
Started	Mar 17 01:24:30 PM PDT 24
Finished	Mar 17 01:24:31 PM PDT 24
Peak memory	195356 kb
Host	smart-0026993c-791c-427f-b813-85f2bcebfe08
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286112884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.1286112884
Directory	/workspace/12.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.82491919
Short name	T978
Test name
Test status
Simulation time	909022987 ps
CPU time	1.11 seconds
Started	Mar 17 01:24:28 PM PDT 24
Finished	Mar 17 01:24:29 PM PDT 24
Peak memory	199484 kb
Host	smart-3b534f49-dbd9-42af-aedc-8890f24ede84
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82491919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.82491919
Directory	/workspace/12.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2062826865
Short name	T911
Test name
Test status
Simulation time	50009626 ps
CPU time	0.77 seconds
Started	Mar 17 01:24:34 PM PDT 24
Finished	Mar 17 01:24:35 PM PDT 24
Peak memory	195156 kb
Host	smart-53badc07-9df7-4b19-bea6-f9edcb6381d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062826865 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.2062826865
Directory	/workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3838677093
Short name	T96
Test name
Test status
Simulation time	55688888 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:35 PM PDT 24
Finished	Mar 17 01:24:36 PM PDT 24
Peak memory	194992 kb
Host	smart-4ac23910-c2a2-40a0-b480-cb9773a33d29
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838677093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3838677093
Directory	/workspace/13.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2417506704
Short name	T986
Test name
Test status
Simulation time	21962536 ps
CPU time	0.83 seconds
Started	Mar 17 01:24:35 PM PDT 24
Finished	Mar 17 01:24:36 PM PDT 24
Peak memory	198304 kb
Host	smart-10a038fa-e24d-4aea-9a95-742ca34762ec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417506704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s ame_csr_outstanding.2417506704
Directory	/workspace/13.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3461292772
Short name	T949
Test name
Test status
Simulation time	773998321 ps
CPU time	2.57 seconds
Started	Mar 17 01:24:28 PM PDT 24
Finished	Mar 17 01:24:31 PM PDT 24
Peak memory	200508 kb
Host	smart-131ee894-8dc2-4323-a730-7de644d1a6c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461292772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3461292772
Directory	/workspace/13.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1178141264
Short name	T943
Test name
Test status
Simulation time	113123088 ps
CPU time	1.08 seconds
Started	Mar 17 01:24:29 PM PDT 24
Finished	Mar 17 01:24:31 PM PDT 24
Peak memory	199576 kb
Host	smart-d6d22fe9-9393-47d5-b8ce-121f21792241
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178141264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er r.1178141264
Directory	/workspace/13.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2383818209
Short name	T55
Test name
Test status
Simulation time	124903680 ps
CPU time	1.62 seconds
Started	Mar 17 01:24:34 PM PDT 24
Finished	Mar 17 01:24:36 PM PDT 24
Peak memory	196216 kb
Host	smart-d275dcbe-0770-4cde-af64-e9fb5b89773a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383818209 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.2383818209
Directory	/workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1350709552
Short name	T98
Test name
Test status
Simulation time	42636218 ps
CPU time	0.65 seconds
Started	Mar 17 01:24:37 PM PDT 24
Finished	Mar 17 01:24:38 PM PDT 24
Peak memory	195012 kb
Host	smart-573d7cfa-f107-47b6-b03e-c91d4fcc95fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350709552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1350709552
Directory	/workspace/14.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4105131803
Short name	T916
Test name
Test status
Simulation time	36287291 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:34 PM PDT 24
Finished	Mar 17 01:24:34 PM PDT 24
Peak memory	194984 kb
Host	smart-dd96c2d1-4447-4310-a359-fee504cc6952
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105131803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.4105131803
Directory	/workspace/14.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1271098124
Short name	T97
Test name
Test status
Simulation time	58829348 ps
CPU time	0.73 seconds
Started	Mar 17 01:24:34 PM PDT 24
Finished	Mar 17 01:24:35 PM PDT 24
Peak memory	199552 kb
Host	smart-7e4bf92d-72fb-4b28-9395-212ab9c7d7ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271098124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s ame_csr_outstanding.1271098124
Directory	/workspace/14.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.408174015
Short name	T124
Test name
Test status
Simulation time	1268586591 ps
CPU time	2.88 seconds
Started	Mar 17 01:24:35 PM PDT 24
Finished	Mar 17 01:24:38 PM PDT 24
Peak memory	196404 kb
Host	smart-959d42f6-81d1-4267-b085-217fadba66f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408174015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.408174015
Directory	/workspace/14.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.662095366
Short name	T930
Test name
Test status
Simulation time	110299520 ps
CPU time	1.11 seconds
Started	Mar 17 01:24:34 PM PDT 24
Finished	Mar 17 01:24:36 PM PDT 24
Peak memory	200484 kb
Host	smart-c90af3c6-c2d0-448f-bf32-21ab732ec26b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662095366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err .662095366
Directory	/workspace/14.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3699840727
Short name	T1002
Test name
Test status
Simulation time	43420156 ps
CPU time	0.83 seconds
Started	Mar 17 01:24:39 PM PDT 24
Finished	Mar 17 01:24:41 PM PDT 24
Peak memory	195132 kb
Host	smart-306e04a3-5fe3-49e3-9129-df69967f98b7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699840727 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3699840727
Directory	/workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3395590970
Short name	T106
Test name
Test status
Simulation time	19592820 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:42 PM PDT 24
Finished	Mar 17 01:24:43 PM PDT 24
Peak memory	195008 kb
Host	smart-a091b27f-0432-45b6-b98e-237c9fd48f22
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395590970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3395590970
Directory	/workspace/15.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3882989067
Short name	T139
Test name
Test status
Simulation time	45218464 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:46 PM PDT 24
Finished	Mar 17 01:24:46 PM PDT 24
Peak memory	194832 kb
Host	smart-3272524b-3538-4fe8-ae59-7c2fcf3b8483
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882989067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3882989067
Directory	/workspace/15.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2852270305
Short name	T989
Test name
Test status
Simulation time	156146458 ps
CPU time	0.84 seconds
Started	Mar 17 01:24:42 PM PDT 24
Finished	Mar 17 01:24:43 PM PDT 24
Peak memory	198280 kb
Host	smart-4e58ec26-994c-4c0e-b3d7-ce50fb4243dd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852270305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s ame_csr_outstanding.2852270305
Directory	/workspace/15.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.946724847
Short name	T933
Test name
Test status
Simulation time	248199662 ps
CPU time	1.36 seconds
Started	Mar 17 01:24:39 PM PDT 24
Finished	Mar 17 01:24:40 PM PDT 24
Peak memory	196132 kb
Host	smart-667a562a-e910-48ec-b5a0-a5eab214dbd2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946724847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.946724847
Directory	/workspace/15.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2206747218
Short name	T72
Test name
Test status
Simulation time	191093347 ps
CPU time	1.68 seconds
Started	Mar 17 01:24:41 PM PDT 24
Finished	Mar 17 01:24:43 PM PDT 24
Peak memory	200356 kb
Host	smart-ef9f35cf-f6c4-46f5-8ee3-fd08c124596e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206747218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er r.2206747218
Directory	/workspace/15.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4206507305
Short name	T967
Test name
Test status
Simulation time	50508864 ps
CPU time	1.02 seconds
Started	Mar 17 01:24:43 PM PDT 24
Finished	Mar 17 01:24:44 PM PDT 24
Peak memory	195096 kb
Host	smart-9ad784d5-b9fa-4f35-a811-1e7d910d386a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206507305 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.4206507305
Directory	/workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1372679347
Short name	T946
Test name
Test status
Simulation time	66847184 ps
CPU time	0.7 seconds
Started	Mar 17 01:24:40 PM PDT 24
Finished	Mar 17 01:24:41 PM PDT 24
Peak memory	195136 kb
Host	smart-32086f46-e8ea-4044-b3bc-12868bc29a16
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372679347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1372679347
Directory	/workspace/16.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.2404394771
Short name	T944
Test name
Test status
Simulation time	181076651 ps
CPU time	0.59 seconds
Started	Mar 17 01:24:39 PM PDT 24
Finished	Mar 17 01:24:41 PM PDT 24
Peak memory	194964 kb
Host	smart-07b75f5b-c6ca-443d-b6cc-4196f2bf9881
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404394771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.2404394771
Directory	/workspace/16.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.334356824
Short name	T115
Test name
Test status
Simulation time	33685550 ps
CPU time	0.79 seconds
Started	Mar 17 01:24:38 PM PDT 24
Finished	Mar 17 01:24:40 PM PDT 24
Peak memory	197304 kb
Host	smart-84d7ad49-410f-4ecc-8ec2-e91b345c3a62
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334356824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa me_csr_outstanding.334356824
Directory	/workspace/16.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.661240415
Short name	T65
Test name
Test status
Simulation time	197347242 ps
CPU time	0.93 seconds
Started	Mar 17 01:24:46 PM PDT 24
Finished	Mar 17 01:24:47 PM PDT 24
Peak memory	195056 kb
Host	smart-a1a63b79-717e-4328-981c-cc56434ad79b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661240415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.661240415
Directory	/workspace/16.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3789828498
Short name	T957
Test name
Test status
Simulation time	364063572 ps
CPU time	1.1 seconds
Started	Mar 17 01:24:39 PM PDT 24
Finished	Mar 17 01:24:41 PM PDT 24
Peak memory	200224 kb
Host	smart-2320a910-b1db-4f99-9d53-3a41634113ef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789828498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er r.3789828498
Directory	/workspace/16.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.4207469202
Short name	T937
Test name
Test status
Simulation time	140221262 ps
CPU time	0.82 seconds
Started	Mar 17 01:24:44 PM PDT 24
Finished	Mar 17 01:24:45 PM PDT 24
Peak memory	200436 kb
Host	smart-10cbb6fe-44e7-49da-97d0-944ca4615084
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207469202 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.4207469202
Directory	/workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1797963774
Short name	T104
Test name
Test status
Simulation time	51547160 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:44 PM PDT 24
Finished	Mar 17 01:24:45 PM PDT 24
Peak memory	197240 kb
Host	smart-fdf9bf3c-bd83-4cd7-b1d5-52b81be77c2e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797963774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1797963774
Directory	/workspace/17.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3353035051
Short name	T899
Test name
Test status
Simulation time	89255325 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:43 PM PDT 24
Finished	Mar 17 01:24:44 PM PDT 24
Peak memory	194980 kb
Host	smart-a71c9508-5b29-40f5-8a50-c9ee299a23ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353035051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3353035051
Directory	/workspace/17.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3808413258
Short name	T123
Test name
Test status
Simulation time	27434502 ps
CPU time	0.71 seconds
Started	Mar 17 01:24:43 PM PDT 24
Finished	Mar 17 01:24:44 PM PDT 24
Peak memory	197228 kb
Host	smart-d6129fed-cbf7-4758-aa4e-37bb3c14fdcd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808413258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s ame_csr_outstanding.3808413258
Directory	/workspace/17.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1606455593
Short name	T73
Test name
Test status
Simulation time	246014861 ps
CPU time	2.48 seconds
Started	Mar 17 01:24:42 PM PDT 24
Finished	Mar 17 01:24:45 PM PDT 24
Peak memory	197428 kb
Host	smart-ff413b10-ee8d-416b-99cb-082c91462f82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606455593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1606455593
Directory	/workspace/17.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.394237634
Short name	T142
Test name
Test status
Simulation time	62569862 ps
CPU time	1.17 seconds
Started	Mar 17 01:24:57 PM PDT 24
Finished	Mar 17 01:24:58 PM PDT 24
Peak memory	196156 kb
Host	smart-a288c5bb-6d0f-4726-a52f-b3c9a4ec1358
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394237634 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.394237634
Directory	/workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1514991882
Short name	T112
Test name
Test status
Simulation time	82450009 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:44 PM PDT 24
Finished	Mar 17 01:24:45 PM PDT 24
Peak memory	195072 kb
Host	smart-a416942b-0a16-4a64-a7c1-837b0dd3870a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514991882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.1514991882
Directory	/workspace/18.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.58498531
Short name	T953
Test name
Test status
Simulation time	20058405 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:45 PM PDT 24
Finished	Mar 17 01:24:46 PM PDT 24
Peak memory	194988 kb
Host	smart-8c15c6bc-1efe-4b5d-a548-0487bd13c9c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58498531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.58498531
Directory	/workspace/18.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2720202535
Short name	T999
Test name
Test status
Simulation time	42098889 ps
CPU time	0.88 seconds
Started	Mar 17 01:24:49 PM PDT 24
Finished	Mar 17 01:24:50 PM PDT 24
Peak memory	198380 kb
Host	smart-3b7abbec-27e0-4cb9-b7ea-f5ce4fd76fce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720202535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s ame_csr_outstanding.2720202535
Directory	/workspace/18.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.119040301
Short name	T966
Test name
Test status
Simulation time	344269733 ps
CPU time	2.07 seconds
Started	Mar 17 01:24:43 PM PDT 24
Finished	Mar 17 01:24:45 PM PDT 24
Peak memory	196116 kb
Host	smart-8df4d6ce-82a8-4683-acea-d3bf590a58f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119040301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.119040301
Directory	/workspace/18.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1621309321
Short name	T70
Test name
Test status
Simulation time	36560883 ps
CPU time	0.72 seconds
Started	Mar 17 01:24:48 PM PDT 24
Finished	Mar 17 01:24:49 PM PDT 24
Peak memory	195216 kb
Host	smart-9fe5849c-5aea-4b9d-99be-97fbdb963ec7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621309321 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1621309321
Directory	/workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3917273538
Short name	T947
Test name
Test status
Simulation time	18531794 ps
CPU time	0.65 seconds
Started	Mar 17 01:24:48 PM PDT 24
Finished	Mar 17 01:24:49 PM PDT 24
Peak memory	195048 kb
Host	smart-a3160864-ee8a-423c-bf1c-a89b4a50f4a4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917273538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3917273538
Directory	/workspace/19.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3136127142
Short name	T973
Test name
Test status
Simulation time	17457818 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:51 PM PDT 24
Finished	Mar 17 01:24:51 PM PDT 24
Peak memory	194980 kb
Host	smart-5532fff3-6be4-4e0d-8943-145d1b5856f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136127142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3136127142
Directory	/workspace/19.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2681139278
Short name	T113
Test name
Test status
Simulation time	68607958 ps
CPU time	0.83 seconds
Started	Mar 17 01:24:51 PM PDT 24
Finished	Mar 17 01:24:52 PM PDT 24
Peak memory	195012 kb
Host	smart-3515e725-e3ab-4f3d-95be-3220fcaf2232
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681139278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s ame_csr_outstanding.2681139278
Directory	/workspace/19.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1006605898
Short name	T985
Test name
Test status
Simulation time	149923906 ps
CPU time	1.93 seconds
Started	Mar 17 01:24:49 PM PDT 24
Finished	Mar 17 01:24:51 PM PDT 24
Peak memory	196184 kb
Host	smart-878969d2-edba-4196-8708-e880c1919aba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006605898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1006605898
Directory	/workspace/19.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4190559718
Short name	T1003
Test name
Test status
Simulation time	213757527 ps
CPU time	1.03 seconds
Started	Mar 17 01:24:50 PM PDT 24
Finished	Mar 17 01:24:51 PM PDT 24
Peak memory	199952 kb
Host	smart-7bf33614-63f8-4c21-a2a0-2679da78f38a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190559718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er r.4190559718
Directory	/workspace/19.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.4250783670
Short name	T141
Test name
Test status
Simulation time	623947695 ps
CPU time	1.86 seconds
Started	Mar 17 01:23:49 PM PDT 24
Finished	Mar 17 01:23:51 PM PDT 24
Peak memory	195148 kb
Host	smart-3d5ce8c5-7682-4e0d-b01f-dc7f8de5b060
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250783670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.4 250783670
Directory	/workspace/2.pwrmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.3676510630
Short name	T95
Test name
Test status
Simulation time	77747677 ps
CPU time	0.67 seconds
Started	Mar 17 01:23:44 PM PDT 24
Finished	Mar 17 01:23:45 PM PDT 24
Peak memory	195040 kb
Host	smart-f5c3c477-601c-41c5-9b71-f373178facb0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676510630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.3 676510630
Directory	/workspace/2.pwrmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.149358394
Short name	T962
Test name
Test status
Simulation time	59820011 ps
CPU time	0.95 seconds
Started	Mar 17 01:23:49 PM PDT 24
Finished	Mar 17 01:23:50 PM PDT 24
Peak memory	195160 kb
Host	smart-497438fe-09b9-4d61-b480-bc58f3a494c0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149358394 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.149358394
Directory	/workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3827828658
Short name	T105
Test name
Test status
Simulation time	18173620 ps
CPU time	0.66 seconds
Started	Mar 17 01:23:47 PM PDT 24
Finished	Mar 17 01:23:48 PM PDT 24
Peak memory	197236 kb
Host	smart-6515f292-aaea-4085-aa80-336881a2992a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827828658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3827828658
Directory	/workspace/2.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.2481840185
Short name	T948
Test name
Test status
Simulation time	33569180 ps
CPU time	0.64 seconds
Started	Mar 17 01:23:41 PM PDT 24
Finished	Mar 17 01:23:42 PM PDT 24
Peak memory	194936 kb
Host	smart-cb5d07a7-1764-4564-bd54-219c40449126
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481840185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.2481840185
Directory	/workspace/2.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2996569368
Short name	T958
Test name
Test status
Simulation time	64265495 ps
CPU time	0.84 seconds
Started	Mar 17 01:23:50 PM PDT 24
Finished	Mar 17 01:23:51 PM PDT 24
Peak memory	198292 kb
Host	smart-d593e8d9-bb92-48e3-b7c5-fd0dd9495b7d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996569368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa me_csr_outstanding.2996569368
Directory	/workspace/2.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2300083758
Short name	T129
Test name
Test status
Simulation time	144198287 ps
CPU time	1.1 seconds
Started	Mar 17 01:23:40 PM PDT 24
Finished	Mar 17 01:23:41 PM PDT 24
Peak memory	200252 kb
Host	smart-62b3300b-2928-4e2d-9f29-1339b08a027b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300083758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err .2300083758
Directory	/workspace/2.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.1906693070
Short name	T138
Test name
Test status
Simulation time	20288547 ps
CPU time	0.59 seconds
Started	Mar 17 01:24:57 PM PDT 24
Finished	Mar 17 01:24:58 PM PDT 24
Peak memory	194956 kb
Host	smart-ecfd1439-4a58-45a2-9fda-99f78f841588
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906693070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1906693070
Directory	/workspace/20.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.1939968848
Short name	T902
Test name
Test status
Simulation time	55241546 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:50 PM PDT 24
Finished	Mar 17 01:24:51 PM PDT 24
Peak memory	194932 kb
Host	smart-76a25152-ec4b-4cf5-92af-13b6ad0b2902
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939968848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.1939968848
Directory	/workspace/21.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.890989901
Short name	T998
Test name
Test status
Simulation time	31196461 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:50 PM PDT 24
Finished	Mar 17 01:24:51 PM PDT 24
Peak memory	194964 kb
Host	smart-3151fbca-1640-4c9e-b99e-d6efb2478c03
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890989901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.890989901
Directory	/workspace/22.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3244605137
Short name	T961
Test name
Test status
Simulation time	183360573 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:52 PM PDT 24
Finished	Mar 17 01:24:53 PM PDT 24
Peak memory	195028 kb
Host	smart-3681da9b-e8fc-4a32-87b6-0a4f004d46b3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244605137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3244605137
Directory	/workspace/23.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1613833501
Short name	T69
Test name
Test status
Simulation time	17801890 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:51 PM PDT 24
Finished	Mar 17 01:24:52 PM PDT 24
Peak memory	194996 kb
Host	smart-cf11e6e5-3a8f-4f1b-8765-78903543c786
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613833501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1613833501
Directory	/workspace/24.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3783327841
Short name	T974
Test name
Test status
Simulation time	61962058 ps
CPU time	0.59 seconds
Started	Mar 17 01:24:50 PM PDT 24
Finished	Mar 17 01:24:51 PM PDT 24
Peak memory	194996 kb
Host	smart-c3667aea-09f4-41c1-a698-27a877b5150f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783327841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3783327841
Directory	/workspace/25.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.4245756452
Short name	T940
Test name
Test status
Simulation time	53951519 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:49 PM PDT 24
Finished	Mar 17 01:24:50 PM PDT 24
Peak memory	194964 kb
Host	smart-c8181c96-1b96-4567-b13c-3742df49b887
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245756452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.4245756452
Directory	/workspace/26.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.1403640921
Short name	T905
Test name
Test status
Simulation time	17140949 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:49 PM PDT 24
Finished	Mar 17 01:24:50 PM PDT 24
Peak memory	194944 kb
Host	smart-7bab2c9a-de48-47b4-84f5-98105e0bbe08
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403640921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.1403640921
Directory	/workspace/27.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3645955398
Short name	T959
Test name
Test status
Simulation time	20728228 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:50 PM PDT 24
Finished	Mar 17 01:24:51 PM PDT 24
Peak memory	195004 kb
Host	smart-8829d375-d918-41e6-b0d0-5326fb974274
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645955398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3645955398
Directory	/workspace/28.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3088431597
Short name	T68
Test name
Test status
Simulation time	20078527 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:56 PM PDT 24
Finished	Mar 17 01:24:57 PM PDT 24
Peak memory	195004 kb
Host	smart-f4566f89-b505-43b8-8507-e4b8e7bcfd21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088431597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3088431597
Directory	/workspace/29.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2871176474
Short name	T936
Test name
Test status
Simulation time	67783317 ps
CPU time	0.91 seconds
Started	Mar 17 01:23:53 PM PDT 24
Finished	Mar 17 01:23:54 PM PDT 24
Peak memory	198748 kb
Host	smart-e354c57f-10d5-437f-9303-f4217a987d3b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871176474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.2 871176474
Directory	/workspace/3.pwrmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.894386340
Short name	T62
Test name
Test status
Simulation time	683066415 ps
CPU time	3.29 seconds
Started	Mar 17 01:23:54 PM PDT 24
Finished	Mar 17 01:23:57 PM PDT 24
Peak memory	195140 kb
Host	smart-7dbf0299-72ac-4a84-a7ee-6cba8907e46c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894386340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.894386340
Directory	/workspace/3.pwrmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1091781979
Short name	T100
Test name
Test status
Simulation time	54146567 ps
CPU time	0.67 seconds
Started	Mar 17 01:23:54 PM PDT 24
Finished	Mar 17 01:23:55 PM PDT 24
Peak memory	197552 kb
Host	smart-49688d8e-ee5c-4852-a57b-490ed56bdc44
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091781979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.1 091781979
Directory	/workspace/3.pwrmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1556717432
Short name	T975
Test name
Test status
Simulation time	45109854 ps
CPU time	1.28 seconds
Started	Mar 17 01:24:03 PM PDT 24
Finished	Mar 17 01:24:04 PM PDT 24
Peak memory	197956 kb
Host	smart-af1c2f65-8caa-4bbc-ac6f-997c68e97dc1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556717432 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.1556717432
Directory	/workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3717154103
Short name	T917
Test name
Test status
Simulation time	127987825 ps
CPU time	0.64 seconds
Started	Mar 17 01:23:54 PM PDT 24
Finished	Mar 17 01:23:55 PM PDT 24
Peak memory	195092 kb
Host	smart-3826c4b6-278a-46e1-9cb5-e46a1c04566f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717154103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3717154103
Directory	/workspace/3.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.4085726923
Short name	T921
Test name
Test status
Simulation time	20351247 ps
CPU time	0.65 seconds
Started	Mar 17 01:23:54 PM PDT 24
Finished	Mar 17 01:23:55 PM PDT 24
Peak memory	194952 kb
Host	smart-3262d2e5-cd36-4100-bce8-0e0fbf0d0db7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085726923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.4085726923
Directory	/workspace/3.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1792253297
Short name	T110
Test name
Test status
Simulation time	115742194 ps
CPU time	0.86 seconds
Started	Mar 17 01:23:54 PM PDT 24
Finished	Mar 17 01:23:55 PM PDT 24
Peak memory	195008 kb
Host	smart-333f55a9-89a5-4c31-b478-145cd8724237
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792253297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa me_csr_outstanding.1792253297
Directory	/workspace/3.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3798970542
Short name	T945
Test name
Test status
Simulation time	469187957 ps
CPU time	2.36 seconds
Started	Mar 17 01:23:48 PM PDT 24
Finished	Mar 17 01:23:50 PM PDT 24
Peak memory	196108 kb
Host	smart-8ed59d77-5400-44fb-b52a-11104f3c4052
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798970542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3798970542
Directory	/workspace/3.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1063036811
Short name	T956
Test name
Test status
Simulation time	221472609 ps
CPU time	1.2 seconds
Started	Mar 17 01:23:55 PM PDT 24
Finished	Mar 17 01:23:56 PM PDT 24
Peak memory	200468 kb
Host	smart-854c4214-3785-4e33-a4e7-1dd074dc2661
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063036811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err .1063036811
Directory	/workspace/3.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3609117274
Short name	T914
Test name
Test status
Simulation time	17930371 ps
CPU time	0.66 seconds
Started	Mar 17 01:24:55 PM PDT 24
Finished	Mar 17 01:24:56 PM PDT 24
Peak memory	194968 kb
Host	smart-45a909f6-a55e-4d53-b61e-01d0eac8da46
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609117274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3609117274
Directory	/workspace/30.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1070053803
Short name	T929
Test name
Test status
Simulation time	41011970 ps
CPU time	0.59 seconds
Started	Mar 17 01:24:56 PM PDT 24
Finished	Mar 17 01:24:57 PM PDT 24
Peak memory	195044 kb
Host	smart-52af16ea-a076-4c36-bf80-459eeccf71e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070053803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1070053803
Directory	/workspace/31.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2156354907
Short name	T906
Test name
Test status
Simulation time	54056352 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:54 PM PDT 24
Finished	Mar 17 01:24:54 PM PDT 24
Peak memory	194980 kb
Host	smart-dceaaea4-cb86-4b1f-8a2c-d3206e431a0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156354907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.2156354907
Directory	/workspace/32.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3422805732
Short name	T991
Test name
Test status
Simulation time	55273498 ps
CPU time	0.57 seconds
Started	Mar 17 01:24:55 PM PDT 24
Finished	Mar 17 01:24:55 PM PDT 24
Peak memory	195000 kb
Host	smart-7dd0d8ce-2a83-432e-a5cf-a08d9927e281
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422805732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3422805732
Directory	/workspace/33.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.797978859
Short name	T970
Test name
Test status
Simulation time	41787701 ps
CPU time	0.59 seconds
Started	Mar 17 01:24:54 PM PDT 24
Finished	Mar 17 01:24:55 PM PDT 24
Peak memory	195016 kb
Host	smart-a2159afe-4866-42db-8232-8f96300026a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797978859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.797978859
Directory	/workspace/34.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3624997936
Short name	T137
Test name
Test status
Simulation time	38097198 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:55 PM PDT 24
Finished	Mar 17 01:24:56 PM PDT 24
Peak memory	194976 kb
Host	smart-2177fe19-d247-44fe-9d05-3a7e598e57e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624997936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3624997936
Directory	/workspace/35.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1888792493
Short name	T939
Test name
Test status
Simulation time	32172387 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:56 PM PDT 24
Finished	Mar 17 01:24:57 PM PDT 24
Peak memory	194988 kb
Host	smart-d7a79d88-f6b2-4586-adc5-5a2030a331c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888792493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.1888792493
Directory	/workspace/36.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3467818559
Short name	T954
Test name
Test status
Simulation time	29438546 ps
CPU time	0.59 seconds
Started	Mar 17 01:24:54 PM PDT 24
Finished	Mar 17 01:24:55 PM PDT 24
Peak memory	194996 kb
Host	smart-cda11ff5-741b-4e50-bca9-40da6fba9533
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467818559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3467818559
Directory	/workspace/37.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.19186175
Short name	T909
Test name
Test status
Simulation time	45712130 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:55 PM PDT 24
Finished	Mar 17 01:24:56 PM PDT 24
Peak memory	195004 kb
Host	smart-0cbfd928-49c4-453b-ab15-c4845ef13e73
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19186175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.19186175
Directory	/workspace/38.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.4235179050
Short name	T900
Test name
Test status
Simulation time	45055684 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:55 PM PDT 24
Finished	Mar 17 01:24:56 PM PDT 24
Peak memory	194944 kb
Host	smart-e7e0e1a5-c757-4106-9c9c-7a34cf1bd797
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235179050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.4235179050
Directory	/workspace/39.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.932497209
Short name	T102
Test name
Test status
Simulation time	167611768 ps
CPU time	1.05 seconds
Started	Mar 17 01:24:06 PM PDT 24
Finished	Mar 17 01:24:07 PM PDT 24
Peak memory	198156 kb
Host	smart-07c0d4ee-1ec4-44ff-9fd2-1d58e73850b6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932497209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.932497209
Directory	/workspace/4.pwrmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1501214307
Short name	T972
Test name
Test status
Simulation time	599368336 ps
CPU time	3.47 seconds
Started	Mar 17 01:24:05 PM PDT 24
Finished	Mar 17 01:24:08 PM PDT 24
Peak memory	195036 kb
Host	smart-c7adc0b9-8de3-4ebc-a79a-dc685e6fac35
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501214307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1 501214307
Directory	/workspace/4.pwrmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2306057526
Short name	T117
Test name
Test status
Simulation time	48058239 ps
CPU time	0.69 seconds
Started	Mar 17 01:24:03 PM PDT 24
Finished	Mar 17 01:24:04 PM PDT 24
Peak memory	195008 kb
Host	smart-f9aaa766-62fb-4ce6-8c51-57b06e334739
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306057526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.2 306057526
Directory	/workspace/4.pwrmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1616936926
Short name	T928
Test name
Test status
Simulation time	58811381 ps
CPU time	0.71 seconds
Started	Mar 17 01:24:05 PM PDT 24
Finished	Mar 17 01:24:06 PM PDT 24
Peak memory	195132 kb
Host	smart-8124955e-1032-4443-8832-af208a318ede
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616936926 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1616936926
Directory	/workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3525963841
Short name	T99
Test name
Test status
Simulation time	16752623 ps
CPU time	0.64 seconds
Started	Mar 17 01:24:04 PM PDT 24
Finished	Mar 17 01:24:05 PM PDT 24
Peak memory	195060 kb
Host	smart-6c3b8e44-a3d2-4ef0-b0f0-76e864f073a5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525963841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3525963841
Directory	/workspace/4.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3583178916
Short name	T904
Test name
Test status
Simulation time	28201639 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:03 PM PDT 24
Finished	Mar 17 01:24:04 PM PDT 24
Peak memory	195028 kb
Host	smart-34591dc5-8ebc-4663-abf7-43f53a783ff8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583178916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.3583178916
Directory	/workspace/4.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2979227338
Short name	T980
Test name
Test status
Simulation time	71902852 ps
CPU time	0.73 seconds
Started	Mar 17 01:24:06 PM PDT 24
Finished	Mar 17 01:24:07 PM PDT 24
Peak memory	197268 kb
Host	smart-58099cc9-d5d4-40bf-aece-60dc28d36aee
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979227338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa me_csr_outstanding.2979227338
Directory	/workspace/4.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1921563757
Short name	T908
Test name
Test status
Simulation time	395973572 ps
CPU time	1.46 seconds
Started	Mar 17 01:24:02 PM PDT 24
Finished	Mar 17 01:24:03 PM PDT 24
Peak memory	196212 kb
Host	smart-be7d2eec-986c-4b09-bc88-c8c2cdf9ea02
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921563757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1921563757
Directory	/workspace/4.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1534225779
Short name	T131
Test name
Test status
Simulation time	178279823 ps
CPU time	1.59 seconds
Started	Mar 17 01:24:03 PM PDT 24
Finished	Mar 17 01:24:05 PM PDT 24
Peak memory	200156 kb
Host	smart-10432434-a5fd-4877-beee-d3da0ff3834e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534225779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err .1534225779
Directory	/workspace/4.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1157254280
Short name	T1001
Test name
Test status
Simulation time	17707482 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:55 PM PDT 24
Finished	Mar 17 01:24:56 PM PDT 24
Peak memory	194944 kb
Host	smart-63e6686b-87e2-497e-84af-015aca715cf6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157254280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1157254280
Directory	/workspace/40.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1290770151
Short name	T993
Test name
Test status
Simulation time	24864802 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:59 PM PDT 24
Finished	Mar 17 01:24:59 PM PDT 24
Peak memory	195028 kb
Host	smart-4d9abe1e-a59c-47b6-8626-2c3d8496faa6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290770151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1290770151
Directory	/workspace/41.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.267446462
Short name	T919
Test name
Test status
Simulation time	34733313 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:58 PM PDT 24
Finished	Mar 17 01:24:59 PM PDT 24
Peak memory	195032 kb
Host	smart-ef7897e6-4d5b-43cd-9471-2577dd0aa357
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267446462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.267446462
Directory	/workspace/42.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.629540619
Short name	T915
Test name
Test status
Simulation time	23717824 ps
CPU time	0.63 seconds
Started	Mar 17 01:25:00 PM PDT 24
Finished	Mar 17 01:25:01 PM PDT 24
Peak memory	194988 kb
Host	smart-2f703536-9d56-4be4-a8d3-57af447d40b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629540619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.629540619
Directory	/workspace/43.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1466213254
Short name	T918
Test name
Test status
Simulation time	26919430 ps
CPU time	0.61 seconds
Started	Mar 17 01:25:01 PM PDT 24
Finished	Mar 17 01:25:02 PM PDT 24
Peak memory	195044 kb
Host	smart-1bed6ff0-e130-4c27-9cfe-f0217bacac83
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466213254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1466213254
Directory	/workspace/44.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.406600038
Short name	T965
Test name
Test status
Simulation time	82492091 ps
CPU time	0.63 seconds
Started	Mar 17 01:24:59 PM PDT 24
Finished	Mar 17 01:25:00 PM PDT 24
Peak memory	195004 kb
Host	smart-6d1654fe-97bc-47ba-93ea-5e6e50397a2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406600038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.406600038
Directory	/workspace/45.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1137654955
Short name	T955
Test name
Test status
Simulation time	16853937 ps
CPU time	0.65 seconds
Started	Mar 17 01:24:58 PM PDT 24
Finished	Mar 17 01:24:59 PM PDT 24
Peak memory	195004 kb
Host	smart-a2a87f08-6c42-4f6e-8658-e29ef4d75a84
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137654955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1137654955
Directory	/workspace/46.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.3068794386
Short name	T903
Test name
Test status
Simulation time	49948141 ps
CPU time	0.59 seconds
Started	Mar 17 01:25:00 PM PDT 24
Finished	Mar 17 01:25:00 PM PDT 24
Peak memory	194960 kb
Host	smart-61a1630d-62cc-4444-89da-4d2ba53dd059
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068794386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.3068794386
Directory	/workspace/47.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3646143834
Short name	T964
Test name
Test status
Simulation time	51597364 ps
CPU time	0.63 seconds
Started	Mar 17 01:25:03 PM PDT 24
Finished	Mar 17 01:25:04 PM PDT 24
Peak memory	194952 kb
Host	smart-862f462e-aab7-4e4f-a6bf-12435279a97b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646143834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3646143834
Directory	/workspace/48.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2880325456
Short name	T920
Test name
Test status
Simulation time	19624759 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:59 PM PDT 24
Finished	Mar 17 01:24:59 PM PDT 24
Peak memory	195008 kb
Host	smart-b24e1255-f58e-4ddd-833b-382d1d7fddcf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880325456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2880325456
Directory	/workspace/49.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1911767925
Short name	T912
Test name
Test status
Simulation time	48702288 ps
CPU time	1.14 seconds
Started	Mar 17 01:24:11 PM PDT 24
Finished	Mar 17 01:24:13 PM PDT 24
Peak memory	197120 kb
Host	smart-50a4787f-852d-4e29-ab86-9313fc1cd321
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911767925 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1911767925
Directory	/workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3935849222
Short name	T925
Test name
Test status
Simulation time	37731804 ps
CPU time	0.66 seconds
Started	Mar 17 01:24:04 PM PDT 24
Finished	Mar 17 01:24:05 PM PDT 24
Peak memory	197240 kb
Host	smart-d10f7995-51b4-426d-85b5-38e40bdb8e4c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935849222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3935849222
Directory	/workspace/5.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.409849433
Short name	T67
Test name
Test status
Simulation time	31129420 ps
CPU time	0.6 seconds
Started	Mar 17 01:24:03 PM PDT 24
Finished	Mar 17 01:24:04 PM PDT 24
Peak memory	194996 kb
Host	smart-5ca30643-806b-46a2-9a61-dc91d783fabe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409849433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.409849433
Directory	/workspace/5.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1942474722
Short name	T913
Test name
Test status
Simulation time	141881544 ps
CPU time	0.87 seconds
Started	Mar 17 01:24:05 PM PDT 24
Finished	Mar 17 01:24:06 PM PDT 24
Peak memory	198400 kb
Host	smart-18d0deb4-c772-4f3b-8aa3-4945c7c38eab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942474722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa me_csr_outstanding.1942474722
Directory	/workspace/5.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3265095210
Short name	T66
Test name
Test status
Simulation time	861136468 ps
CPU time	2.22 seconds
Started	Mar 17 01:24:04 PM PDT 24
Finished	Mar 17 01:24:06 PM PDT 24
Peak memory	197196 kb
Host	smart-097b507d-c47b-444e-818f-343fb5293fad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265095210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3265095210
Directory	/workspace/5.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.976061452
Short name	T58
Test name
Test status
Simulation time	2096127163 ps
CPU time	1.52 seconds
Started	Mar 17 01:24:03 PM PDT 24
Finished	Mar 17 01:24:05 PM PDT 24
Peak memory	195096 kb
Host	smart-94d9d2a8-d41f-498a-88e3-0fa0e75e0e6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976061452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err. 976061452
Directory	/workspace/5.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3744512678
Short name	T984
Test name
Test status
Simulation time	45949455 ps
CPU time	0.85 seconds
Started	Mar 17 01:24:08 PM PDT 24
Finished	Mar 17 01:24:09 PM PDT 24
Peak memory	195080 kb
Host	smart-b060ce6c-a587-42dc-b841-c5ed7977bac4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744512678 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.3744512678
Directory	/workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1811723074
Short name	T941
Test name
Test status
Simulation time	50587617 ps
CPU time	0.67 seconds
Started	Mar 17 01:24:09 PM PDT 24
Finished	Mar 17 01:24:10 PM PDT 24
Peak memory	197276 kb
Host	smart-e61d1a58-8ad8-45ef-9a5c-1cde77554bfe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811723074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1811723074
Directory	/workspace/6.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.1151195381
Short name	T938
Test name
Test status
Simulation time	21416666 ps
CPU time	0.61 seconds
Started	Mar 17 01:24:10 PM PDT 24
Finished	Mar 17 01:24:10 PM PDT 24
Peak memory	194996 kb
Host	smart-c4c03377-a515-495a-b54a-1d18d88f55b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151195381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.1151195381
Directory	/workspace/6.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.849227080
Short name	T960
Test name
Test status
Simulation time	47608643 ps
CPU time	0.86 seconds
Started	Mar 17 01:24:11 PM PDT 24
Finished	Mar 17 01:24:12 PM PDT 24
Peak memory	199876 kb
Host	smart-b19acf56-281c-4542-84ba-68e7776933f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849227080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sam e_csr_outstanding.849227080
Directory	/workspace/6.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3716598114
Short name	T950
Test name
Test status
Simulation time	41367642 ps
CPU time	1.61 seconds
Started	Mar 17 01:24:11 PM PDT 24
Finished	Mar 17 01:24:13 PM PDT 24
Peak memory	196536 kb
Host	smart-a21978b9-5ed2-4c57-a0af-37ece0e3d6c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716598114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3716598114
Directory	/workspace/6.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2137921007
Short name	T969
Test name
Test status
Simulation time	147949900 ps
CPU time	1.22 seconds
Started	Mar 17 01:24:08 PM PDT 24
Finished	Mar 17 01:24:10 PM PDT 24
Peak memory	199996 kb
Host	smart-ecd43311-70d0-4515-891f-f7c15826c766
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137921007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err .2137921007
Directory	/workspace/6.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.54508691
Short name	T983
Test name
Test status
Simulation time	366383098 ps
CPU time	1.42 seconds
Started	Mar 17 01:24:16 PM PDT 24
Finished	Mar 17 01:24:18 PM PDT 24
Peak memory	197680 kb
Host	smart-dcf64b6c-4415-4cc3-b509-adf1c1a425cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54508691 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.54508691
Directory	/workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1820966008
Short name	T1000
Test name
Test status
Simulation time	96999024 ps
CPU time	0.66 seconds
Started	Mar 17 01:24:09 PM PDT 24
Finished	Mar 17 01:24:10 PM PDT 24
Peak memory	197288 kb
Host	smart-18bdd5d6-45ef-4c98-ae4e-934c38ee3319
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820966008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1820966008
Directory	/workspace/7.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2550334646
Short name	T990
Test name
Test status
Simulation time	43482636 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:11 PM PDT 24
Finished	Mar 17 01:24:12 PM PDT 24
Peak memory	194964 kb
Host	smart-e3d00856-a6bb-4c45-a8b5-3418fa6ba92a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550334646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2550334646
Directory	/workspace/7.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1089447544
Short name	T934
Test name
Test status
Simulation time	41336223 ps
CPU time	0.89 seconds
Started	Mar 17 01:24:10 PM PDT 24
Finished	Mar 17 01:24:12 PM PDT 24
Peak memory	198268 kb
Host	smart-4fc2b311-83e0-4983-aef7-7ef134151e12
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089447544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa me_csr_outstanding.1089447544
Directory	/workspace/7.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1669437683
Short name	T942
Test name
Test status
Simulation time	120926512 ps
CPU time	1.6 seconds
Started	Mar 17 01:24:12 PM PDT 24
Finished	Mar 17 01:24:14 PM PDT 24
Peak memory	196196 kb
Host	smart-dde85e01-6bc2-4f47-b078-8f6f19c7fe06
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669437683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1669437683
Directory	/workspace/7.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2228691810
Short name	T996
Test name
Test status
Simulation time	218022691 ps
CPU time	1.18 seconds
Started	Mar 17 01:24:09 PM PDT 24
Finished	Mar 17 01:24:10 PM PDT 24
Peak memory	200408 kb
Host	smart-00efac40-2441-48e6-b5e6-8931aba3cbf0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228691810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err .2228691810
Directory	/workspace/7.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.397188307
Short name	T56
Test name
Test status
Simulation time	51615342 ps
CPU time	0.89 seconds
Started	Mar 17 01:24:17 PM PDT 24
Finished	Mar 17 01:24:18 PM PDT 24
Peak memory	195212 kb
Host	smart-dc09df4e-012b-4f3f-b842-5247cd498f0e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397188307 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.397188307
Directory	/workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2601630658
Short name	T140
Test name
Test status
Simulation time	20433188 ps
CPU time	0.68 seconds
Started	Mar 17 01:24:15 PM PDT 24
Finished	Mar 17 01:24:16 PM PDT 24
Peak memory	197244 kb
Host	smart-8137273c-3bd4-496e-b37b-685c87be5f87
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601630658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2601630658
Directory	/workspace/8.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3897938820
Short name	T995
Test name
Test status
Simulation time	44656986 ps
CPU time	0.73 seconds
Started	Mar 17 01:24:15 PM PDT 24
Finished	Mar 17 01:24:16 PM PDT 24
Peak memory	195036 kb
Host	smart-40685755-5317-4b55-8415-304b388c08cf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897938820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa me_csr_outstanding.3897938820
Directory	/workspace/8.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.607379306
Short name	T981
Test name
Test status
Simulation time	271146302 ps
CPU time	2.1 seconds
Started	Mar 17 01:24:15 PM PDT 24
Finished	Mar 17 01:24:17 PM PDT 24
Peak memory	196128 kb
Host	smart-f03399c3-23ed-4db7-99f8-3c3e148fd6f7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607379306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.607379306
Directory	/workspace/8.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1725668980
Short name	T976
Test name
Test status
Simulation time	583133457 ps
CPU time	1.04 seconds
Started	Mar 17 01:24:17 PM PDT 24
Finished	Mar 17 01:24:18 PM PDT 24
Peak memory	200364 kb
Host	smart-91e17e6b-4765-464d-ad27-92a9c2bd9a31
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725668980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err .1725668980
Directory	/workspace/8.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.110855898
Short name	T924
Test name
Test status
Simulation time	44936798 ps
CPU time	1.23 seconds
Started	Mar 17 01:24:15 PM PDT 24
Finished	Mar 17 01:24:17 PM PDT 24
Peak memory	197224 kb
Host	smart-c937cf0d-79f8-4dfd-b215-363f6b3eb82b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110855898 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.110855898
Directory	/workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2040326674
Short name	T94
Test name
Test status
Simulation time	30524632 ps
CPU time	0.66 seconds
Started	Mar 17 01:24:18 PM PDT 24
Finished	Mar 17 01:24:19 PM PDT 24
Peak memory	195008 kb
Host	smart-9b6e24e7-44bc-40ab-b7ff-adee4d6bd474
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040326674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2040326674
Directory	/workspace/9.pwrmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.758774266
Short name	T931
Test name
Test status
Simulation time	61643478 ps
CPU time	0.62 seconds
Started	Mar 17 01:24:15 PM PDT 24
Finished	Mar 17 01:24:16 PM PDT 24
Peak memory	195000 kb
Host	smart-be06418f-c42d-40b9-b3c1-97c401d98173
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758774266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.758774266
Directory	/workspace/9.pwrmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2262212448
Short name	T111
Test name
Test status
Simulation time	286469159 ps
CPU time	0.73 seconds
Started	Mar 17 01:24:15 PM PDT 24
Finished	Mar 17 01:24:15 PM PDT 24
Peak memory	197248 kb
Host	smart-9a8b75b1-8879-4867-85e9-9d4d2cc67906
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262212448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa me_csr_outstanding.2262212448
Directory	/workspace/9.pwrmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.991872982
Short name	T932
Test name
Test status
Simulation time	131658496 ps
CPU time	1.13 seconds
Started	Mar 17 01:24:15 PM PDT 24
Finished	Mar 17 01:24:16 PM PDT 24
Peak memory	196084 kb
Host	smart-1e572807-e88b-4897-a83a-01198edc5c0f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991872982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.991872982
Directory	/workspace/9.pwrmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.728573954
Short name	T130
Test name
Test status
Simulation time	114516625 ps
CPU time	1.13 seconds
Started	Mar 17 01:24:14 PM PDT 24
Finished	Mar 17 01:24:16 PM PDT 24
Peak memory	200264 kb
Host	smart-df6994ff-84fc-4d79-8d97-c16e6fe8867a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728573954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err. 728573954
Directory	/workspace/9.pwrmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.pwrmgr_aborted_low_power.916441956
Short name	T673
Test name
Test status
Simulation time	25292175 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:04 PM PDT 24
Finished	Mar 17 01:44:05 PM PDT 24
Peak memory	197772 kb
Host	smart-7981b165-c30f-4226-9093-ef7f688113c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916441956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.916441956
Directory	/workspace/0.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.3683092038
Short name	T831
Test name
Test status
Simulation time	81192461 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:04 PM PDT 24
Finished	Mar 17 01:44:05 PM PDT 24
Peak memory	197940 kb
Host	smart-90957394-9dd0-460e-93ef-a53000525d39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683092038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa ble_rom_integrity_check.3683092038
Directory	/workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2519074112
Short name	T430
Test name
Test status
Simulation time	32693073 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:03 PM PDT 24
Finished	Mar 17 01:44:04 PM PDT 24
Peak memory	197388 kb
Host	smart-9bbc1243-e960-4b89-b794-b6ab9f831dad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519074112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_ malfunc.2519074112
Directory	/workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/0.pwrmgr_escalation_timeout.1660344382
Short name	T636
Test name
Test status
Simulation time	606134062 ps
CPU time	1.01 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:08 PM PDT 24
Peak memory	197376 kb
Host	smart-51be0af1-abc0-44e4-ab87-02f7f9898352
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660344382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.1660344382
Directory	/workspace/0.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/0.pwrmgr_glitch.784925161
Short name	T170
Test name
Test status
Simulation time	65208451 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:03 PM PDT 24
Finished	Mar 17 01:44:04 PM PDT 24
Peak memory	196664 kb
Host	smart-3d33f24b-a9de-4315-91dd-61e89b65e2a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784925161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.784925161
Directory	/workspace/0.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/0.pwrmgr_global_esc.3850787429
Short name	T2
Test name
Test status
Simulation time	49954776 ps
CPU time	0.67 seconds
Started	Mar 17 01:44:05 PM PDT 24
Finished	Mar 17 01:44:06 PM PDT 24
Peak memory	197848 kb
Host	smart-748e3a74-28e7-42a0-ab0e-0088f5c080f5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850787429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3850787429
Directory	/workspace/0.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/0.pwrmgr_lowpower_invalid.1628325689
Short name	T610
Test name
Test status
Simulation time	57571762 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	200744 kb
Host	smart-8e84fe63-9c6f-4c8f-a787-829bb56dd4a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628325689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali d.1628325689
Directory	/workspace/0.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/0.pwrmgr_reset.1424709911
Short name	T324
Test name
Test status
Simulation time	49571643 ps
CPU time	0.91 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	199332 kb
Host	smart-2e59d4ff-f9a3-456c-b23d-14c06fc76286
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424709911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.1424709911
Directory	/workspace/0.pwrmgr_reset/latest

Test location	/workspace/coverage/default/0.pwrmgr_reset_invalid.3921472457
Short name	T519
Test name
Test status
Simulation time	108913338 ps
CPU time	0.96 seconds
Started	Mar 17 01:44:04 PM PDT 24
Finished	Mar 17 01:44:05 PM PDT 24
Peak memory	208864 kb
Host	smart-563f8c61-eeb0-4c40-baa2-2ef346280e3b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921472457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3921472457
Directory	/workspace/0.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/0.pwrmgr_sec_cm.1110326535
Short name	T19
Test name
Test status
Simulation time	336292107 ps
CPU time	1.51 seconds
Started	Mar 17 01:44:02 PM PDT 24
Finished	Mar 17 01:44:04 PM PDT 24
Peak memory	216344 kb
Host	smart-9839bf0d-3c2e-454f-88ab-ca2c7a13d6f7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110326535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1110326535
Directory	/workspace/0.pwrmgr_sec_cm/latest

Test location	/workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1112096340
Short name	T571
Test name
Test status
Simulation time	85275319 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:08 PM PDT 24
Peak memory	198484 kb
Host	smart-d3b301e6-3560-44cc-b270-bd891a298000
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112096340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c m_ctrl_config_regwen.1112096340
Directory	/workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2591384709
Short name	T780
Test name
Test status
Simulation time	893420057 ps
CPU time	3.08 seconds
Started	Mar 17 01:44:05 PM PDT 24
Finished	Mar 17 01:44:08 PM PDT 24
Peak memory	200700 kb
Host	smart-7f9a6854-a787-441e-a638-ca792ab5cb15
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591384709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2591384709
Directory	/workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.636315168
Short name	T412
Test name
Test status
Simulation time	64703551 ps
CPU time	0.85 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	198560 kb
Host	smart-b3501824-6cb4-4dbd-a043-489d5caf5285
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636315168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_m ubi.636315168
Directory	/workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/0.pwrmgr_smoke.2287260747
Short name	T264
Test name
Test status
Simulation time	45639709 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:09 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	198700 kb
Host	smart-73341697-48a3-4527-a7a2-87aea246108c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287260747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2287260747
Directory	/workspace/0.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/0.pwrmgr_wakeup.3074090074
Short name	T698
Test name
Test status
Simulation time	281069042 ps
CPU time	1.35 seconds
Started	Mar 17 01:44:05 PM PDT 24
Finished	Mar 17 01:44:07 PM PDT 24
Peak memory	200036 kb
Host	smart-9019d58c-7553-4fec-9c22-0d3875ad5b3e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074090074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.3074090074
Directory	/workspace/0.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/0.pwrmgr_wakeup_reset.2659185366
Short name	T679
Test name
Test status
Simulation time	382755953 ps
CPU time	1.41 seconds
Started	Mar 17 01:44:03 PM PDT 24
Finished	Mar 17 01:44:05 PM PDT 24
Peak memory	200492 kb
Host	smart-82d0d6eb-86fa-4b94-a42c-f90056ed7f02
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659185366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.2659185366
Directory	/workspace/0.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/1.pwrmgr_aborted_low_power.936824352
Short name	T223
Test name
Test status
Simulation time	106269593 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:14 PM PDT 24
Peak memory	197988 kb
Host	smart-37c98fda-5231-4f2a-8d15-89fec7d74058
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936824352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.936824352
Directory	/workspace/1.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1624309617
Short name	T132
Test name
Test status
Simulation time	68049028 ps
CPU time	0.91 seconds
Started	Mar 17 01:44:12 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	198524 kb
Host	smart-fe632638-525d-43a9-b05c-90d0469ae897
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624309617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa ble_rom_integrity_check.1624309617
Directory	/workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.358401422
Short name	T485
Test name
Test status
Simulation time	30287320 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	196680 kb
Host	smart-8126c456-ade6-4fc1-8a45-ea2d77791a1d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358401422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_m alfunc.358401422
Directory	/workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/1.pwrmgr_escalation_timeout.1862280278
Short name	T456
Test name
Test status
Simulation time	162118815 ps
CPU time	1.03 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:14 PM PDT 24
Peak memory	197784 kb
Host	smart-c47c1ec5-011e-4f60-ab2f-1fbf75e39ea6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862280278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1862280278
Directory	/workspace/1.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/1.pwrmgr_global_esc.2749449969
Short name	T625
Test name
Test status
Simulation time	39170693 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	197448 kb
Host	smart-085801cd-6fda-498c-961b-e24fd2c6f979
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749449969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2749449969
Directory	/workspace/1.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/1.pwrmgr_lowpower_invalid.3216638027
Short name	T864
Test name
Test status
Simulation time	50371210 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:12 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	200716 kb
Host	smart-6f5bbb85-0eaf-4d3f-bfaa-1d21809814f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216638027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali d.3216638027
Directory	/workspace/1.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.516276793
Short name	T421
Test name
Test status
Simulation time	33912307 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:09 PM PDT 24
Peak memory	197700 kb
Host	smart-b7f98995-43f0-4fdc-bc2b-a2f632a45d05
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516276793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wak eup_race.516276793
Directory	/workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/1.pwrmgr_reset.528855675
Short name	T685
Test name
Test status
Simulation time	185618916 ps
CPU time	0.99 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:08 PM PDT 24
Peak memory	199144 kb
Host	smart-e579bc12-fb5e-4e70-972e-70d0f06fdba6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528855675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.528855675
Directory	/workspace/1.pwrmgr_reset/latest

Test location	/workspace/coverage/default/1.pwrmgr_reset_invalid.2484536846
Short name	T13
Test name
Test status
Simulation time	515226474 ps
CPU time	0.79 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	208848 kb
Host	smart-a237b8e2-0d9d-4c36-bf45-ec02816c2331
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484536846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2484536846
Directory	/workspace/1.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.347148768
Short name	T272
Test name
Test status
Simulation time	237397047 ps
CPU time	0.89 seconds
Started	Mar 17 01:44:06 PM PDT 24
Finished	Mar 17 01:44:07 PM PDT 24
Peak memory	199352 kb
Host	smart-9a1c4e50-480b-4cb5-926b-1e136091b16e
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347148768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm _ctrl_config_regwen.347148768
Directory	/workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.718558573
Short name	T696
Test name
Test status
Simulation time	763285168 ps
CPU time	2.47 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	200696 kb
Host	smart-bb223757-e0f0-4e85-88c3-b24962dd02d4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718558573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.718558573
Directory	/workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2122816581
Short name	T396
Test name
Test status
Simulation time	889991671 ps
CPU time	2.86 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	200592 kb
Host	smart-ade8ffce-b9ab-471f-ada8-6da02b2af17f
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122816581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2122816581
Directory	/workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.207502722
Short name	T814
Test name
Test status
Simulation time	54093691 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:14 PM PDT 24
Finished	Mar 17 01:44:15 PM PDT 24
Peak memory	198580 kb
Host	smart-0b056a5f-c894-46ce-bdd8-f17cb4beafe3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207502722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_m ubi.207502722
Directory	/workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/1.pwrmgr_smoke.2336439194
Short name	T708
Test name
Test status
Simulation time	55234259 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:09 PM PDT 24
Peak memory	197868 kb
Host	smart-f71767c3-e50f-4399-b229-78450652e087
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336439194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2336439194
Directory	/workspace/1.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/1.pwrmgr_wakeup.1559812861
Short name	T880
Test name
Test status
Simulation time	285648140 ps
CPU time	0.96 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	199004 kb
Host	smart-bb7649a5-ae53-47aa-9234-0191c219839c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559812861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1559812861
Directory	/workspace/1.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/1.pwrmgr_wakeup_reset.628171632
Short name	T660
Test name
Test status
Simulation time	61872313 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	198472 kb
Host	smart-03e8f959-301e-451e-861a-c394218d095a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628171632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.628171632
Directory	/workspace/1.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/10.pwrmgr_aborted_low_power.2579562079
Short name	T47
Test name
Test status
Simulation time	23531451 ps
CPU time	0.75 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	197976 kb
Host	smart-88e79797-3edf-47e3-b7e4-59a45df7f898
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579562079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2579562079
Directory	/workspace/10.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.3731045968
Short name	T135
Test name
Test status
Simulation time	55718446 ps
CPU time	0.86 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	198512 kb
Host	smart-b379499e-7b9e-4c96-9a54-afcb420e672d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731045968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis able_rom_integrity_check.3731045968
Directory	/workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3756864847
Short name	T646
Test name
Test status
Simulation time	31383780 ps
CPU time	0.59 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:39 PM PDT 24
Peak memory	196656 kb
Host	smart-00fb0e07-f32b-409c-b75d-8030c555ba1f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756864847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst _malfunc.3756864847
Directory	/workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/10.pwrmgr_escalation_timeout.4080432568
Short name	T873
Test name
Test status
Simulation time	612031082 ps
CPU time	1.02 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	197516 kb
Host	smart-5e97d55f-6bb1-4821-8dfa-9a5ceeb9142a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080432568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.4080432568
Directory	/workspace/10.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/10.pwrmgr_glitch.1344818196
Short name	T17
Test name
Test status
Simulation time	32402316 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:39 PM PDT 24
Peak memory	197500 kb
Host	smart-be02f322-f92c-4fc2-94e2-801ea658e439
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344818196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1344818196
Directory	/workspace/10.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/10.pwrmgr_global_esc.685784604
Short name	T549
Test name
Test status
Simulation time	46384647 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:34 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	197816 kb
Host	smart-5ec341e7-cf1e-4bf3-a2e6-6175b4278432
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685784604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.685784604
Directory	/workspace/10.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/10.pwrmgr_lowpower_invalid.2823581831
Short name	T51
Test name
Test status
Simulation time	86835063 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	200732 kb
Host	smart-7609cbb9-8170-4392-81eb-a9f3de7e2c6c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823581831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval id.2823581831
Directory	/workspace/10.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/10.pwrmgr_reset.79551189
Short name	T168
Test name
Test status
Simulation time	143039585 ps
CPU time	0.88 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	198512 kb
Host	smart-c9f5367e-1387-4c20-afcb-f47afabf8bfb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79551189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.79551189
Directory	/workspace/10.pwrmgr_reset/latest

Test location	/workspace/coverage/default/10.pwrmgr_reset_invalid.1419409741
Short name	T312
Test name
Test status
Simulation time	98210351 ps
CPU time	1.08 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:34 PM PDT 24
Peak memory	208904 kb
Host	smart-7aa58344-1682-40d5-bc67-ca278916dedf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419409741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1419409741
Directory	/workspace/10.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4269184575
Short name	T514
Test name
Test status
Simulation time	278445549 ps
CPU time	0.96 seconds
Started	Mar 17 01:44:36 PM PDT 24
Finished	Mar 17 01:44:37 PM PDT 24
Peak memory	199252 kb
Host	smart-20294620-00c7-4da6-809b-b3fd6a8b2925
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269184575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_ cm_ctrl_config_regwen.4269184575
Directory	/workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2123089048
Short name	T397
Test name
Test status
Simulation time	938030403 ps
CPU time	2.56 seconds
Started	Mar 17 01:44:36 PM PDT 24
Finished	Mar 17 01:44:39 PM PDT 24
Peak memory	200456 kb
Host	smart-e5f470f6-83f5-45fc-aeeb-8b937c4f84b8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123089048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2123089048
Directory	/workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.89160480
Short name	T389
Test name
Test status
Simulation time	974234967 ps
CPU time	2.69 seconds
Started	Mar 17 01:44:31 PM PDT 24
Finished	Mar 17 01:44:34 PM PDT 24
Peak memory	200608 kb
Host	smart-41db32e4-fcd6-44f8-b453-55217ff3afcc
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89160480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.89160480
Directory	/workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3606837416
Short name	T457
Test name
Test status
Simulation time	66789147 ps
CPU time	1.05 seconds
Started	Mar 17 01:44:33 PM PDT 24
Finished	Mar 17 01:44:34 PM PDT 24
Peak memory	198684 kb
Host	smart-561c91c9-75e8-47f6-8cd3-ae3c921a5b20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606837416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig _mubi.3606837416
Directory	/workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/10.pwrmgr_smoke.270874245
Short name	T790
Test name
Test status
Simulation time	54319828 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	198656 kb
Host	smart-d19dc726-4eea-43c7-aabf-f154c9a73269
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270874245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.270874245
Directory	/workspace/10.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/10.pwrmgr_stress_all.1088382898
Short name	T482
Test name
Test status
Simulation time	1064274487 ps
CPU time	2.1 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:39 PM PDT 24
Peak memory	200600 kb
Host	smart-0d6726dd-9ba0-466a-a0ee-730b6c95a064
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088382898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.1088382898
Directory	/workspace/10.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/10.pwrmgr_wakeup.3971460606
Short name	T235
Test name
Test status
Simulation time	221668572 ps
CPU time	1.16 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	199028 kb
Host	smart-08d369ec-084b-4fc6-9706-8a80cf1119d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971460606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.3971460606
Directory	/workspace/10.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/10.pwrmgr_wakeup_reset.676486306
Short name	T618
Test name
Test status
Simulation time	136834209 ps
CPU time	0.75 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	198704 kb
Host	smart-bf33ec32-e891-4014-bf3f-576d7f3f5950
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676486306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.676486306
Directory	/workspace/10.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/11.pwrmgr_aborted_low_power.2977559688
Short name	T14
Test name
Test status
Simulation time	29077513 ps
CPU time	0.74 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	197968 kb
Host	smart-ae320dea-8f94-48d6-a98e-948e6960e848
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977559688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2977559688
Directory	/workspace/11.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.589042628
Short name	T460
Test name
Test status
Simulation time	30082057 ps
CPU time	0.67 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	196764 kb
Host	smart-2511a724-5203-4059-8c41-31ebcd5744c9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589042628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_ malfunc.589042628
Directory	/workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/11.pwrmgr_glitch.913196626
Short name	T709
Test name
Test status
Simulation time	63281745 ps
CPU time	0.78 seconds
Started	Mar 17 01:44:43 PM PDT 24
Finished	Mar 17 01:44:44 PM PDT 24
Peak memory	197528 kb
Host	smart-cef25288-187b-43cb-8f25-4ac4aae1a9cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913196626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.913196626
Directory	/workspace/11.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/11.pwrmgr_global_esc.89339061
Short name	T470
Test name
Test status
Simulation time	34165444 ps
CPU time	0.67 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	197772 kb
Host	smart-86196fcc-2ee0-4a94-970c-7774acd3a03d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89339061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.89339061
Directory	/workspace/11.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/11.pwrmgr_lowpower_invalid.1443133039
Short name	T440
Test name
Test status
Simulation time	46130622 ps
CPU time	0.7 seconds
Started	Mar 17 01:44:39 PM PDT 24
Finished	Mar 17 01:44:41 PM PDT 24
Peak memory	200756 kb
Host	smart-d14e6ecd-bb14-409d-ab2b-cf74acf2298d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443133039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval id.1443133039
Directory	/workspace/11.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.3865337612
Short name	T452
Test name
Test status
Simulation time	48361421 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	197660 kb
Host	smart-6154ce72-8f85-40e0-963e-2a972ef4f917
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865337612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w akeup_race.3865337612
Directory	/workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/11.pwrmgr_reset.3657161200
Short name	T245
Test name
Test status
Simulation time	146523810 ps
CPU time	0.86 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:39 PM PDT 24
Peak memory	198568 kb
Host	smart-5d0ad07e-1648-4b29-a975-b544094df67f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657161200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3657161200
Directory	/workspace/11.pwrmgr_reset/latest

Test location	/workspace/coverage/default/11.pwrmgr_reset_invalid.2259419626
Short name	T767
Test name
Test status
Simulation time	128712294 ps
CPU time	0.85 seconds
Started	Mar 17 01:44:47 PM PDT 24
Finished	Mar 17 01:44:48 PM PDT 24
Peak memory	208900 kb
Host	smart-62a76a8f-a0ca-435b-a6f9-6cb2a2536012
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259419626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2259419626
Directory	/workspace/11.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.1980521866
Short name	T454
Test name
Test status
Simulation time	127480750 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	198116 kb
Host	smart-bff8d1ba-774a-49b4-aff5-c2cb460f5cd7
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980521866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_ cm_ctrl_config_regwen.1980521866
Directory	/workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2085106620
Short name	T384
Test name
Test status
Simulation time	960590792 ps
CPU time	2.14 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:40 PM PDT 24
Peak memory	200532 kb
Host	smart-82ab955e-c626-491f-8af3-6697b26dd70e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085106620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2085106620
Directory	/workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.783284279
Short name	T163
Test name
Test status
Simulation time	1021678672 ps
CPU time	2.53 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:41 PM PDT 24
Peak memory	200436 kb
Host	smart-f868b13b-de8a-4d63-808c-428fde929131
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783284279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.783284279
Directory	/workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.592605152
Short name	T427
Test name
Test status
Simulation time	77763032 ps
CPU time	0.97 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	198512 kb
Host	smart-a9910b5e-aaa5-4984-8f4f-6dfa2cf3364a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592605152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_ mubi.592605152
Directory	/workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/11.pwrmgr_smoke.1926717384
Short name	T804
Test name
Test status
Simulation time	65092262 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:31 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	197864 kb
Host	smart-8fb37bfa-f3b3-4111-9098-399023124683
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926717384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1926717384
Directory	/workspace/11.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/11.pwrmgr_wakeup.3817815651
Short name	T784
Test name
Test status
Simulation time	65622514 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:33 PM PDT 24
Finished	Mar 17 01:44:34 PM PDT 24
Peak memory	197696 kb
Host	smart-91529266-3ed8-436e-a277-3541605e8968
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817815651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.3817815651
Directory	/workspace/11.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/11.pwrmgr_wakeup_reset.1705786138
Short name	T760
Test name
Test status
Simulation time	55153638 ps
CPU time	0.79 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	198504 kb
Host	smart-c98b31db-97d4-4a0d-ae49-e9155c3e9dab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705786138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.1705786138
Directory	/workspace/11.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/12.pwrmgr_aborted_low_power.330988777
Short name	T375
Test name
Test status
Simulation time	20495712 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:39 PM PDT 24
Finished	Mar 17 01:44:41 PM PDT 24
Peak memory	197920 kb
Host	smart-4cb9e041-73bf-46db-a812-f4f64ad0d51f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330988777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.330988777
Directory	/workspace/12.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.563202387
Short name	T92
Test name
Test status
Simulation time	67261857 ps
CPU time	0.75 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197856 kb
Host	smart-5de38fed-d87a-4b3a-bd78-0cb118619d7c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563202387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disa ble_rom_integrity_check.563202387
Directory	/workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2628062798
Short name	T641
Test name
Test status
Simulation time	29028573 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:48 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	196716 kb
Host	smart-304b74f0-6d8b-4c1b-ae6e-fe42c0e7f5c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628062798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst _malfunc.2628062798
Directory	/workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/12.pwrmgr_escalation_timeout.957586564
Short name	T177
Test name
Test status
Simulation time	168524885 ps
CPU time	0.97 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:52 PM PDT 24
Peak memory	197516 kb
Host	smart-f44f3f26-6ca5-4058-8b05-89631e15ae27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957586564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.957586564
Directory	/workspace/12.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/12.pwrmgr_glitch.1087813702
Short name	T479
Test name
Test status
Simulation time	33428833 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	197436 kb
Host	smart-89ba0e28-3e55-4998-9254-f67f8bc671d0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087813702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1087813702
Directory	/workspace/12.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/12.pwrmgr_global_esc.918774683
Short name	T441
Test name
Test status
Simulation time	99221047 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	197416 kb
Host	smart-07290c32-c8dc-4a59-b1b5-e90736fe74ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918774683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.918774683
Directory	/workspace/12.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/12.pwrmgr_lowpower_invalid.1296553747
Short name	T199
Test name
Test status
Simulation time	79395859 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	200560 kb
Host	smart-06e6da86-0593-49e7-a8ec-766d4143fe1c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296553747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval id.1296553747
Directory	/workspace/12.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.1756455446
Short name	T504
Test name
Test status
Simulation time	785282878 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:40 PM PDT 24
Finished	Mar 17 01:44:41 PM PDT 24
Peak memory	198992 kb
Host	smart-73203289-7117-4170-a443-c4fa093b9a84
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756455446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w akeup_race.1756455446
Directory	/workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/12.pwrmgr_reset.2063171451
Short name	T484
Test name
Test status
Simulation time	60779949 ps
CPU time	0.78 seconds
Started	Mar 17 01:44:42 PM PDT 24
Finished	Mar 17 01:44:43 PM PDT 24
Peak memory	198520 kb
Host	smart-f631d657-b348-443d-80f1-05a0c8bf8e21
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063171451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2063171451
Directory	/workspace/12.pwrmgr_reset/latest

Test location	/workspace/coverage/default/12.pwrmgr_reset_invalid.3141293276
Short name	T890
Test name
Test status
Simulation time	96216285 ps
CPU time	1.08 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	208884 kb
Host	smart-655e8699-a573-48db-8a68-dcd42f6b5f34
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141293276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3141293276
Directory	/workspace/12.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3866279528
Short name	T574
Test name
Test status
Simulation time	857722197 ps
CPU time	2.85 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	200588 kb
Host	smart-a68e1da0-3bee-424b-b927-a53cb1f10081
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866279528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3866279528
Directory	/workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1265071509
Short name	T661
Test name
Test status
Simulation time	855506167 ps
CPU time	3.21 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	200588 kb
Host	smart-6f7a25a9-871d-43f3-8d56-4d0b15ee2bdf
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265071509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1265071509
Directory	/workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2771591795
Short name	T33
Test name
Test status
Simulation time	103245379 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	198688 kb
Host	smart-7e2f1ac4-e16b-44ea-9e54-39b3b4950cf5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771591795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig _mubi.2771591795
Directory	/workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/12.pwrmgr_smoke.3251911720
Short name	T807
Test name
Test status
Simulation time	67663814 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	197884 kb
Host	smart-dd5b66d1-0796-44bc-8d35-ba6bb4429d42
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251911720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3251911720
Directory	/workspace/12.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/12.pwrmgr_wakeup.14986326
Short name	T892
Test name
Test status
Simulation time	344165078 ps
CPU time	1.23 seconds
Started	Mar 17 01:44:41 PM PDT 24
Finished	Mar 17 01:44:43 PM PDT 24
Peak memory	199124 kb
Host	smart-a0360aa9-a94a-4eff-a7c5-a30579b9628f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.14986326
Directory	/workspace/12.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/12.pwrmgr_wakeup_reset.3463223121
Short name	T637
Test name
Test status
Simulation time	198077442 ps
CPU time	0.95 seconds
Started	Mar 17 01:44:48 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	199256 kb
Host	smart-079f6fac-f130-4121-a1e0-3bcfe978cf58
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463223121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3463223121
Directory	/workspace/12.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/13.pwrmgr_aborted_low_power.79895905
Short name	T298
Test name
Test status
Simulation time	35147698 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197872 kb
Host	smart-1912f35d-cacd-4aca-9f63-3392a0f30426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79895905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.79895905
Directory	/workspace/13.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.1868330924
Short name	T224
Test name
Test status
Simulation time	67943752 ps
CPU time	0.89 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	198452 kb
Host	smart-3228c068-700e-4502-93bc-aecfa610a0c9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868330924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis able_rom_integrity_check.1868330924
Directory	/workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1789217797
Short name	T182
Test name
Test status
Simulation time	52586499 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	197552 kb
Host	smart-40a40295-a9c4-4155-b554-fdc12fc64019
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789217797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst _malfunc.1789217797
Directory	/workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/13.pwrmgr_escalation_timeout.3126617705
Short name	T768
Test name
Test status
Simulation time	610425397 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	197484 kb
Host	smart-42105886-79e6-4a1b-90d8-344740eca785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126617705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.3126617705
Directory	/workspace/13.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/13.pwrmgr_glitch.2439476995
Short name	T620
Test name
Test status
Simulation time	61665442 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	197444 kb
Host	smart-94d00c2d-5f1f-4928-b3e0-b7ff335f29ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439476995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2439476995
Directory	/workspace/13.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/13.pwrmgr_global_esc.102838649
Short name	T88
Test name
Test status
Simulation time	60541909 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	197508 kb
Host	smart-035e93a2-234f-4bce-bfab-244d40a57a4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102838649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.102838649
Directory	/workspace/13.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/13.pwrmgr_lowpower_invalid.2542626726
Short name	T564
Test name
Test status
Simulation time	81816934 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	200744 kb
Host	smart-24305028-9141-4cbf-ba62-c78dc6ef5085
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542626726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval id.2542626726
Directory	/workspace/13.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.1025765309
Short name	T351
Test name
Test status
Simulation time	246362198 ps
CPU time	0.81 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	197916 kb
Host	smart-51fd2c8a-ea5b-47ff-b9e9-67bb21c33a76
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025765309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w akeup_race.1025765309
Directory	/workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/13.pwrmgr_reset.1271661532
Short name	T337
Test name
Test status
Simulation time	200702208 ps
CPU time	0.91 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	199184 kb
Host	smart-f1cb3f98-a707-42e3-8cff-9db493260484
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271661532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.1271661532
Directory	/workspace/13.pwrmgr_reset/latest

Test location	/workspace/coverage/default/13.pwrmgr_reset_invalid.1835567636
Short name	T662
Test name
Test status
Simulation time	172514276 ps
CPU time	0.84 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	208964 kb
Host	smart-d9156295-cfca-4d4c-a472-6854b5ffea8f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835567636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1835567636
Directory	/workspace/13.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3431135880
Short name	T623
Test name
Test status
Simulation time	526722291 ps
CPU time	1.1 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	200100 kb
Host	smart-c7a2fbcf-490a-4202-b5d7-6199cfc7e082
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431135880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_ cm_ctrl_config_regwen.3431135880
Directory	/workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1080095255
Short name	T204
Test name
Test status
Simulation time	809578502 ps
CPU time	2.27 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	200584 kb
Host	smart-bdf3fc87-f21f-47de-b4f3-69683c20550f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080095255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1080095255
Directory	/workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3082820978
Short name	T529
Test name
Test status
Simulation time	1044534444 ps
CPU time	1.96 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	200592 kb
Host	smart-88acd6db-9853-46aa-a82e-53f85ff2adf4
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082820978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3082820978
Directory	/workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.563822330
Short name	T395
Test name
Test status
Simulation time	111379692 ps
CPU time	0.89 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	198740 kb
Host	smart-ce2ec5c4-7ce7-4420-9ac2-483e1ab3701b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563822330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_ mubi.563822330
Directory	/workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/13.pwrmgr_smoke.1749158093
Short name	T401
Test name
Test status
Simulation time	29357904 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	198740 kb
Host	smart-3029534a-056d-4ec7-8990-6ac8226ddab8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749158093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1749158093
Directory	/workspace/13.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/13.pwrmgr_stress_all.768347967
Short name	T453
Test name
Test status
Simulation time	697190739 ps
CPU time	1.53 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	200592 kb
Host	smart-9ecbad36-e4a2-4275-8a1b-84c60c95f9e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768347967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.768347967
Directory	/workspace/13.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/13.pwrmgr_wakeup.1061658323
Short name	T492
Test name
Test status
Simulation time	509783119 ps
CPU time	1 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	199180 kb
Host	smart-0091eb3e-8d4b-477a-8bea-df8739f5628f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061658323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.1061658323
Directory	/workspace/13.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/13.pwrmgr_wakeup_reset.3959281984
Short name	T327
Test name
Test status
Simulation time	187915938 ps
CPU time	1.05 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	199432 kb
Host	smart-3c7de41f-2254-4b9e-b544-cf80367dc6c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959281984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3959281984
Directory	/workspace/13.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/14.pwrmgr_aborted_low_power.1682018899
Short name	T678
Test name
Test status
Simulation time	46255314 ps
CPU time	0.7 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	197912 kb
Host	smart-697b8b28-9464-4411-a800-6a347cb6c442
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682018899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1682018899
Directory	/workspace/14.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.4136596156
Short name	T677
Test name
Test status
Simulation time	58476478 ps
CPU time	0.83 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	198532 kb
Host	smart-2af0422a-8d49-4209-a6c2-19ab03418110
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136596156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis able_rom_integrity_check.4136596156
Directory	/workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1100706818
Short name	T428
Test name
Test status
Simulation time	28909820 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	197384 kb
Host	smart-b697e40a-98eb-4e97-a751-1df3edcaacef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100706818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst _malfunc.1100706818
Directory	/workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/14.pwrmgr_escalation_timeout.3077487262
Short name	T350
Test name
Test status
Simulation time	494522909 ps
CPU time	0.95 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197556 kb
Host	smart-45f36bcb-4453-4e08-9c92-45c07bdde362
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077487262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.3077487262
Directory	/workspace/14.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/14.pwrmgr_glitch.3571121361
Short name	T717
Test name
Test status
Simulation time	35437263 ps
CPU time	0.67 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	196740 kb
Host	smart-d92e80d6-d135-4e9f-93e9-c1191096947b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571121361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3571121361
Directory	/workspace/14.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/14.pwrmgr_global_esc.2389008390
Short name	T681
Test name
Test status
Simulation time	86695454 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	197448 kb
Host	smart-22039d1b-0d4c-4506-ae84-ccccf32af848
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389008390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.2389008390
Directory	/workspace/14.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/14.pwrmgr_lowpower_invalid.1984969905
Short name	T490
Test name
Test status
Simulation time	48997796 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	200812 kb
Host	smart-cae00228-52df-40d3-b039-6b96d45e8544
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984969905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval id.1984969905
Directory	/workspace/14.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.1330221145
Short name	T248
Test name
Test status
Simulation time	420745000 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:52 PM PDT 24
Peak memory	199108 kb
Host	smart-936a2676-9e96-4c46-bddd-bd649a387720
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330221145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w akeup_race.1330221145
Directory	/workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/14.pwrmgr_reset.3841267782
Short name	T659
Test name
Test status
Simulation time	199203954 ps
CPU time	0.83 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	199136 kb
Host	smart-d06ecbba-9417-4383-8795-7fde0f7c2973
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841267782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3841267782
Directory	/workspace/14.pwrmgr_reset/latest

Test location	/workspace/coverage/default/14.pwrmgr_reset_invalid.2771752981
Short name	T751
Test name
Test status
Simulation time	569871844 ps
CPU time	0.79 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	208892 kb
Host	smart-d6d515a0-db10-4660-a0c4-aa4c3a630e4a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771752981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2771752981
Directory	/workspace/14.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.1440519981
Short name	T237
Test name
Test status
Simulation time	438313986 ps
CPU time	1.21 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	200316 kb
Host	smart-fb41d2f0-a0ce-42fb-993a-e1a165c4a929
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440519981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_ cm_ctrl_config_regwen.1440519981
Directory	/workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3215430870
Short name	T279
Test name
Test status
Simulation time	892028081 ps
CPU time	2.29 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:52 PM PDT 24
Peak memory	200592 kb
Host	smart-7d9e6f82-5781-415f-aef9-3cb01902960a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215430870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3215430870
Directory	/workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3241471156
Short name	T273
Test name
Test status
Simulation time	866541194 ps
CPU time	2.11 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	200672 kb
Host	smart-f7e0e192-c97b-4c78-ac17-aef1e7a77750
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241471156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3241471156
Directory	/workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3426176890
Short name	T307
Test name
Test status
Simulation time	54410998 ps
CPU time	0.93 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:52 PM PDT 24
Peak memory	198436 kb
Host	smart-279e3c8f-4ea1-4b9f-af4b-4069d543754e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426176890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig _mubi.3426176890
Directory	/workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/14.pwrmgr_smoke.2190277111
Short name	T5
Test name
Test status
Simulation time	101761561 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	197904 kb
Host	smart-41b1ec23-ab89-416c-bb57-7809526176b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190277111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2190277111
Directory	/workspace/14.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/14.pwrmgr_wakeup.3840938116
Short name	T849
Test name
Test status
Simulation time	130773280 ps
CPU time	1.01 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	199080 kb
Host	smart-dcd9f866-44a2-45d0-bdd4-7bfc88bbf924
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840938116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.3840938116
Directory	/workspace/14.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/14.pwrmgr_wakeup_reset.2658618895
Short name	T64
Test name
Test status
Simulation time	148273746 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:47 PM PDT 24
Finished	Mar 17 01:44:49 PM PDT 24
Peak memory	197844 kb
Host	smart-7147d376-a475-4452-8cd2-a5e4a77d6531
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658618895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.2658618895
Directory	/workspace/14.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/15.pwrmgr_aborted_low_power.717831669
Short name	T258
Test name
Test status
Simulation time	28594747 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	197944 kb
Host	smart-f7c4fda6-2f06-49ff-8a23-c87a8e1636f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717831669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.717831669
Directory	/workspace/15.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.948816968
Short name	T420
Test name
Test status
Simulation time	72992097 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	198520 kb
Host	smart-5e7929cb-c52a-4273-aa84-ca01d58ca36f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948816968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disa ble_rom_integrity_check.948816968
Directory	/workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.467184017
Short name	T658
Test name
Test status
Simulation time	28342406 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197344 kb
Host	smart-fe3981ef-b87a-4cb6-80fd-41686fafb094
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467184017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_ malfunc.467184017
Directory	/workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/15.pwrmgr_escalation_timeout.1968731387
Short name	T242
Test name
Test status
Simulation time	640129582 ps
CPU time	0.93 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197520 kb
Host	smart-77be876b-9d65-4c9f-9b71-41d54657baa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968731387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.1968731387
Directory	/workspace/15.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/15.pwrmgr_glitch.4285451757
Short name	T731
Test name
Test status
Simulation time	30392128 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	197528 kb
Host	smart-7c9f70e8-48a9-4ccc-9185-50abcaa02597
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285451757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.4285451757
Directory	/workspace/15.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/15.pwrmgr_global_esc.224149902
Short name	T194
Test name
Test status
Simulation time	303127365 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197612 kb
Host	smart-5f06b4f7-bd6f-4848-bbd4-478f0119f71f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224149902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.224149902
Directory	/workspace/15.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/15.pwrmgr_lowpower_invalid.3586565095
Short name	T601
Test name
Test status
Simulation time	81824257 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	200756 kb
Host	smart-6a0d8e10-f0e5-4380-8312-d76fd0268661
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586565095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval id.3586565095
Directory	/workspace/15.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.956526237
Short name	T86
Test name
Test status
Simulation time	227006767 ps
CPU time	0.85 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	197864 kb
Host	smart-af89c440-10db-426b-b24d-39160e38dc89
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956526237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wa keup_race.956526237
Directory	/workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/15.pwrmgr_reset.3317832504
Short name	T154
Test name
Test status
Simulation time	78612480 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	199176 kb
Host	smart-013873c7-d6a9-42b7-9b2d-7a853a00671f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317832504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3317832504
Directory	/workspace/15.pwrmgr_reset/latest

Test location	/workspace/coverage/default/15.pwrmgr_reset_invalid.1497774720
Short name	T530
Test name
Test status
Simulation time	97845049 ps
CPU time	0.92 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	208868 kb
Host	smart-27cccac4-9771-40f1-8834-dcce4d1ec023
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497774720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1497774720
Directory	/workspace/15.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3144213871
Short name	T79
Test name
Test status
Simulation time	1232627308 ps
CPU time	2.05 seconds
Started	Mar 17 01:44:48 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	200536 kb
Host	smart-36e34fa9-d93b-43f8-9652-eee2fc75dddc
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144213871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3144213871
Directory	/workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1221809286
Short name	T770
Test name
Test status
Simulation time	744528047 ps
CPU time	2.76 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	200544 kb
Host	smart-f68a5acf-503b-48d1-bc0d-e77fdd376fcc
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221809286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1221809286
Directory	/workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2289755249
Short name	T603
Test name
Test status
Simulation time	165292234 ps
CPU time	0.88 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	198564 kb
Host	smart-783eb0f6-e8b2-4fac-b042-a8b663709e71
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289755249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig _mubi.2289755249
Directory	/workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/15.pwrmgr_smoke.1094479354
Short name	T356
Test name
Test status
Simulation time	64423754 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197944 kb
Host	smart-e6efc9a2-43b1-4c69-a63e-4ba423494949
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094479354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1094479354
Directory	/workspace/15.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/15.pwrmgr_wakeup.471932171
Short name	T577
Test name
Test status
Simulation time	95250514 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197548 kb
Host	smart-753c6885-aa49-4aba-af70-a0362e9aa4a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471932171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.471932171
Directory	/workspace/15.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/15.pwrmgr_wakeup_reset.3791643323
Short name	T507
Test name
Test status
Simulation time	365820652 ps
CPU time	1.34 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	200560 kb
Host	smart-1bcab9a4-e5e7-43be-96cd-fedfc3d67c21
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791643323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.3791643323
Directory	/workspace/15.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/16.pwrmgr_aborted_low_power.4290379791
Short name	T570
Test name
Test status
Simulation time	117129031 ps
CPU time	0.81 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	198184 kb
Host	smart-e1dc4259-4d0a-432c-a843-6e6c6eb3942f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290379791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.4290379791
Directory	/workspace/16.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.1092577337
Short name	T374
Test name
Test status
Simulation time	83390119 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:16 PM PDT 24
Peak memory	197888 kb
Host	smart-9c86a443-7668-4d11-a432-c43ffd64d018
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092577337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis able_rom_integrity_check.1092577337
Directory	/workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.34996707
Short name	T511
Test name
Test status
Simulation time	29478346 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	197468 kb
Host	smart-32f86f99-a26e-4728-9917-4134fd0d1285
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_m alfunc.34996707
Directory	/workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/16.pwrmgr_escalation_timeout.4211667131
Short name	T363
Test name
Test status
Simulation time	662224984 ps
CPU time	0.96 seconds
Started	Mar 17 01:45:01 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	197836 kb
Host	smart-7e5ed22e-7b4e-4225-b8d9-c01e63df5292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211667131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.4211667131
Directory	/workspace/16.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/16.pwrmgr_glitch.2244772176
Short name	T269
Test name
Test status
Simulation time	32621701 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:02 PM PDT 24
Finished	Mar 17 01:45:03 PM PDT 24
Peak memory	196740 kb
Host	smart-c6efaa97-8c0c-487e-949d-612b33629d67
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244772176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2244772176
Directory	/workspace/16.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/16.pwrmgr_global_esc.4272904490
Short name	T495
Test name
Test status
Simulation time	40081063 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	197756 kb
Host	smart-c0060c24-ef91-4db4-b92d-0d0962bf684a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272904490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.4272904490
Directory	/workspace/16.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/16.pwrmgr_lowpower_invalid.1241638041
Short name	T385
Test name
Test status
Simulation time	76081448 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:12 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	200712 kb
Host	smart-b95bc2b2-7626-4a5e-a0f5-2f7eb56a4f07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241638041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval id.1241638041
Directory	/workspace/16.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.3817847253
Short name	T612
Test name
Test status
Simulation time	165518979 ps
CPU time	0.76 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	197692 kb
Host	smart-9816ade7-ee14-44d5-aa3a-857bea98a5f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817847253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w akeup_race.3817847253
Directory	/workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/16.pwrmgr_reset.345826996
Short name	T371
Test name
Test status
Simulation time	114341319 ps
CPU time	0.8 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	199392 kb
Host	smart-cdd6f32b-2f36-4f25-bd1f-65a0a9502a9d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345826996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.345826996
Directory	/workspace/16.pwrmgr_reset/latest

Test location	/workspace/coverage/default/16.pwrmgr_reset_invalid.1913112054
Short name	T796
Test name
Test status
Simulation time	156137856 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:01 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	208860 kb
Host	smart-50923a80-97eb-418e-afa8-a9c9f06454a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913112054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.1913112054
Directory	/workspace/16.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1294940805
Short name	T642
Test name
Test status
Simulation time	75758098 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	199464 kb
Host	smart-92676fa4-8360-4cff-a4fd-49ebf3372249
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294940805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_ cm_ctrl_config_regwen.1294940805
Directory	/workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3274221746
Short name	T216
Test name
Test status
Simulation time	877480328 ps
CPU time	2.36 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	200192 kb
Host	smart-a49f1592-61aa-4773-bd0a-6e3ec4632ecb
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274221746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3274221746
Directory	/workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2522524525
Short name	T345
Test name
Test status
Simulation time	992600365 ps
CPU time	2.15 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:07 PM PDT 24
Peak memory	200696 kb
Host	smart-094040a0-2132-4e33-ada4-3f239d374d01
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522524525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2522524525
Directory	/workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.3046670136
Short name	T261
Test name
Test status
Simulation time	67323459 ps
CPU time	0.97 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	198600 kb
Host	smart-6d811028-91c3-46db-9ba9-711d27e23a79
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046670136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig _mubi.3046670136
Directory	/workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/16.pwrmgr_smoke.2648515967
Short name	T446
Test name
Test status
Simulation time	31000680 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	198760 kb
Host	smart-4c02ae3e-6c6e-4e60-a519-2b758c9acd23
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648515967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2648515967
Directory	/workspace/16.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/16.pwrmgr_stress_all.3626649825
Short name	T475
Test name
Test status
Simulation time	152661191 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:12 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	198732 kb
Host	smart-8a834281-d95e-49ac-a36c-785cfd73062f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626649825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.3626649825
Directory	/workspace/16.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/16.pwrmgr_wakeup_reset.1429900485
Short name	T635
Test name
Test status
Simulation time	310770280 ps
CPU time	0.99 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	199636 kb
Host	smart-f1d03e26-59c3-4bbe-a423-76ada79eecd7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429900485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.1429900485
Directory	/workspace/16.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/17.pwrmgr_aborted_low_power.316827138
Short name	T212
Test name
Test status
Simulation time	94080095 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	197908 kb
Host	smart-7cc1f5ff-df2e-47b5-a655-07fe8f2de3e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316827138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.316827138
Directory	/workspace/17.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3758907960
Short name	T476
Test name
Test status
Simulation time	53453876 ps
CPU time	0.78 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	198516 kb
Host	smart-33a05659-7fc1-4822-b77e-2c377a5e4df7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758907960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis able_rom_integrity_check.3758907960
Directory	/workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1239763771
Short name	T462
Test name
Test status
Simulation time	38362473 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	197400 kb
Host	smart-0be38f5c-0ff7-42f0-a459-d62cf9487dd6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239763771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst _malfunc.1239763771
Directory	/workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/17.pwrmgr_escalation_timeout.2823143645
Short name	T201
Test name
Test status
Simulation time	632954142 ps
CPU time	0.98 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	197484 kb
Host	smart-8911ed06-8501-4f73-8355-4e3f81f8cddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823143645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2823143645
Directory	/workspace/17.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/17.pwrmgr_glitch.1341414466
Short name	T306
Test name
Test status
Simulation time	73292561 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197452 kb
Host	smart-c566f63b-519b-4728-9767-64db11b1d307
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341414466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1341414466
Directory	/workspace/17.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/17.pwrmgr_global_esc.1216124660
Short name	T364
Test name
Test status
Simulation time	38602341 ps
CPU time	0.58 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:52 PM PDT 24
Peak memory	197524 kb
Host	smart-66166d67-ba48-40bf-8ed6-bf02232f9e2d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216124660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1216124660
Directory	/workspace/17.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/17.pwrmgr_lowpower_invalid.81741694
Short name	T50
Test name
Test status
Simulation time	39839233 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	200732 kb
Host	smart-aabf61c0-cd05-484e-82a8-732acead96d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81741694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid .81741694
Directory	/workspace/17.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.763429678
Short name	T537
Test name
Test status
Simulation time	137210857 ps
CPU time	0.8 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	197656 kb
Host	smart-d89106d2-3c7a-4d33-a63d-80b69fd2ad3d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763429678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wa keup_race.763429678
Directory	/workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/17.pwrmgr_reset.2740485461
Short name	T265
Test name
Test status
Simulation time	67613497 ps
CPU time	1.05 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	199252 kb
Host	smart-4110bbb8-2a3a-4944-900a-1956b43a0740
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740485461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.2740485461
Directory	/workspace/17.pwrmgr_reset/latest

Test location	/workspace/coverage/default/17.pwrmgr_reset_invalid.2421358735
Short name	T832
Test name
Test status
Simulation time	140551101 ps
CPU time	0.85 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	208908 kb
Host	smart-e5a89e69-3da1-4e63-966f-d6e88d2f0d66
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421358735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2421358735
Directory	/workspace/17.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1410460552
Short name	T466
Test name
Test status
Simulation time	916333726 ps
CPU time	2.38 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	200548 kb
Host	smart-bf23b1ad-4373-474a-a19d-6f532f8fac0f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410460552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1410460552
Directory	/workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2015415138
Short name	T858
Test name
Test status
Simulation time	1766521343 ps
CPU time	1.84 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	200328 kb
Host	smart-5d327296-e90c-4be9-8b5d-87177dc21e12
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015415138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2015415138
Directory	/workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1529703272
Short name	T771
Test name
Test status
Simulation time	76034869 ps
CPU time	0.95 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	198936 kb
Host	smart-54e11b31-e065-43cd-9479-c117a564e5e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529703272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig _mubi.1529703272
Directory	/workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/17.pwrmgr_smoke.4073421244
Short name	T221
Test name
Test status
Simulation time	28161527 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:52 PM PDT 24
Peak memory	198644 kb
Host	smart-e3b21aab-328f-45cd-b0cb-1993cf7b25fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073421244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.4073421244
Directory	/workspace/17.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/17.pwrmgr_stress_all.1839506251
Short name	T732
Test name
Test status
Simulation time	884099271 ps
CPU time	2.06 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	200680 kb
Host	smart-d320854c-969c-45f0-99f7-62d10f71409c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839506251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.1839506251
Directory	/workspace/17.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/17.pwrmgr_wakeup.2731834149
Short name	T669
Test name
Test status
Simulation time	86350279 ps
CPU time	0.75 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	198484 kb
Host	smart-8c1b3d32-1716-4da6-a0c2-91c70fbe4115
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731834149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.2731834149
Directory	/workspace/17.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/17.pwrmgr_wakeup_reset.805502414
Short name	T809
Test name
Test status
Simulation time	303058997 ps
CPU time	0.98 seconds
Started	Mar 17 01:44:50 PM PDT 24
Finished	Mar 17 01:44:51 PM PDT 24
Peak memory	199620 kb
Host	smart-aba61777-acc7-4baa-b75b-ce1d18cd5da3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805502414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.805502414
Directory	/workspace/17.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/18.pwrmgr_aborted_low_power.1639982980
Short name	T781
Test name
Test status
Simulation time	76154609 ps
CPU time	0.75 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	199108 kb
Host	smart-b5cdfafd-9953-454c-8065-8fdd75c8b788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639982980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1639982980
Directory	/workspace/18.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.4247298240
Short name	T551
Test name
Test status
Simulation time	63990442 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	198532 kb
Host	smart-6e47cc4c-2cb1-438a-8ed7-27325a12572f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247298240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis able_rom_integrity_check.4247298240
Directory	/workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3506571587
Short name	T157
Test name
Test status
Simulation time	29605957 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	197372 kb
Host	smart-77fb128c-a1d8-4c07-b302-5a05aa69c386
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506571587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst _malfunc.3506571587
Directory	/workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/18.pwrmgr_escalation_timeout.3959176510
Short name	T759
Test name
Test status
Simulation time	159596037 ps
CPU time	0.98 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	197852 kb
Host	smart-41133e92-4d39-48dc-b703-39bb6cd103d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959176510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.3959176510
Directory	/workspace/18.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/18.pwrmgr_glitch.3914420026
Short name	T560
Test name
Test status
Simulation time	35802389 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	196312 kb
Host	smart-884635bf-83f6-48a0-b81e-321df6da7765
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914420026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.3914420026
Directory	/workspace/18.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/18.pwrmgr_global_esc.1129003335
Short name	T773
Test name
Test status
Simulation time	81959455 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	197436 kb
Host	smart-df6ea697-0ea7-4879-8e36-e06caf726a59
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129003335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1129003335
Directory	/workspace/18.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/18.pwrmgr_lowpower_invalid.728654914
Short name	T827
Test name
Test status
Simulation time	53943458 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	200780 kb
Host	smart-e2c77c21-73f2-4fb5-9ae1-291c5f4569c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728654914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invali d.728654914
Directory	/workspace/18.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/18.pwrmgr_reset.2476788997
Short name	T596
Test name
Test status
Simulation time	67466629 ps
CPU time	0.7 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	197952 kb
Host	smart-59783038-c568-4a0f-be03-cdb8672bb0f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476788997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.2476788997
Directory	/workspace/18.pwrmgr_reset/latest

Test location	/workspace/coverage/default/18.pwrmgr_reset_invalid.3372009342
Short name	T777
Test name
Test status
Simulation time	117352778 ps
CPU time	0.93 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	208944 kb
Host	smart-8e779b6f-24ed-46e4-8fd5-b698615d57d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372009342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3372009342
Directory	/workspace/18.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.284027079
Short name	T121
Test name
Test status
Simulation time	294778154 ps
CPU time	0.86 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	199208 kb
Host	smart-21447007-1670-49e5-81c2-cdb5a718ff48
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284027079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_c m_ctrl_config_regwen.284027079
Directory	/workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1924432137
Short name	T811
Test name
Test status
Simulation time	929884776 ps
CPU time	2.68 seconds
Started	Mar 17 01:44:52 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	200516 kb
Host	smart-27fc9826-af8c-4bf5-bbc8-c9bc4e1cb93c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924432137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1924432137
Directory	/workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4195787509
Short name	T705
Test name
Test status
Simulation time	1193812473 ps
CPU time	2.1 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	200568 kb
Host	smart-94a05aa2-02e4-45bf-b80e-673b96f03aa4
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195787509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4195787509
Directory	/workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.656150072
Short name	T756
Test name
Test status
Simulation time	53818779 ps
CPU time	0.88 seconds
Started	Mar 17 01:44:49 PM PDT 24
Finished	Mar 17 01:44:50 PM PDT 24
Peak memory	198492 kb
Host	smart-ea20d2f4-30bf-430f-9f3d-2c6da6d6f04f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656150072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_ mubi.656150072
Directory	/workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/18.pwrmgr_smoke.1420220087
Short name	T672
Test name
Test status
Simulation time	32969868 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:51 PM PDT 24
Finished	Mar 17 01:44:53 PM PDT 24
Peak memory	198652 kb
Host	smart-2935750d-1426-4033-ad07-9ca6dae6b79d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420220087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.1420220087
Directory	/workspace/18.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/18.pwrmgr_wakeup.4157567274
Short name	T572
Test name
Test status
Simulation time	290810066 ps
CPU time	1.19 seconds
Started	Mar 17 01:44:53 PM PDT 24
Finished	Mar 17 01:44:54 PM PDT 24
Peak memory	199008 kb
Host	smart-2a8ac14a-8a73-41d8-9d82-abd90eeca383
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157567274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.4157567274
Directory	/workspace/18.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/18.pwrmgr_wakeup_reset.48170422
Short name	T498
Test name
Test status
Simulation time	230329834 ps
CPU time	0.85 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	198600 kb
Host	smart-ed2d3fc7-050e-4374-b14b-af94882afe49
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48170422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.48170422
Directory	/workspace/18.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/19.pwrmgr_aborted_low_power.1400544319
Short name	T633
Test name
Test status
Simulation time	19387838 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	197940 kb
Host	smart-6f942f94-9ac7-4d61-b332-e5de05cc4de4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400544319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1400544319
Directory	/workspace/19.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.4240338906
Short name	T448
Test name
Test status
Simulation time	63132707 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197860 kb
Host	smart-2e519e91-4653-4c7c-bfa6-b492f1c2302c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240338906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis able_rom_integrity_check.4240338906
Directory	/workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.904353084
Short name	T693
Test name
Test status
Simulation time	31525683 ps
CPU time	0.59 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	196680 kb
Host	smart-4d76ccef-9a27-4c5d-be9a-7fe87beed435
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904353084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_ malfunc.904353084
Directory	/workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/19.pwrmgr_escalation_timeout.1668685493
Short name	T403
Test name
Test status
Simulation time	273041728 ps
CPU time	1.01 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	197532 kb
Host	smart-14b3d5d9-d600-4a9c-94d7-604c0861f468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668685493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1668685493
Directory	/workspace/19.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/19.pwrmgr_glitch.4253340508
Short name	T346
Test name
Test status
Simulation time	50493911 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	197524 kb
Host	smart-f7ddfe55-720f-4d4b-a4df-e6d6338b34f7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253340508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.4253340508
Directory	/workspace/19.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/19.pwrmgr_global_esc.1610757619
Short name	T744
Test name
Test status
Simulation time	50568293 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	197172 kb
Host	smart-88c0797b-1c24-4c29-b4a3-5fdbfb6f5cc3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610757619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1610757619
Directory	/workspace/19.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/19.pwrmgr_lowpower_invalid.780702971
Short name	T32
Test name
Test status
Simulation time	50858468 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	200760 kb
Host	smart-989c5bec-688b-42e0-8939-ef8b1fd6d8d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780702971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invali d.780702971
Directory	/workspace/19.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.2726225
Short name	T390
Test name
Test status
Simulation time	263413302 ps
CPU time	0.87 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	197872 kb
Host	smart-415828dd-4371-4998-92a3-58560775acd7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_ race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wake up_race.2726225
Directory	/workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/19.pwrmgr_reset.1676998408
Short name	T697
Test name
Test status
Simulation time	125625536 ps
CPU time	0.91 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	199148 kb
Host	smart-fe48cefb-bb19-436f-9b21-148036c72138
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676998408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1676998408
Directory	/workspace/19.pwrmgr_reset/latest

Test location	/workspace/coverage/default/19.pwrmgr_reset_invalid.3991033582
Short name	T225
Test name
Test status
Simulation time	267151456 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	208916 kb
Host	smart-c625f6da-f377-4012-ad3f-43080cd970e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991033582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3991033582
Directory	/workspace/19.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2936988158
Short name	T718
Test name
Test status
Simulation time	949400463 ps
CPU time	2.55 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:03 PM PDT 24
Peak memory	200632 kb
Host	smart-37245780-8cd9-42d5-984f-0e38b6a8739d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936988158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2936988158
Directory	/workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2489723508
Short name	T520
Test name
Test status
Simulation time	1201132170 ps
CPU time	2.22 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	200616 kb
Host	smart-f17b1f6f-1a1a-43f1-8cfe-2c61ed3ce0a2
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489723508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2489723508
Directory	/workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.829281146
Short name	T517
Test name
Test status
Simulation time	52482439 ps
CPU time	0.97 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	198692 kb
Host	smart-cf48fd56-1ed3-40ca-8874-9f33da1e0e5c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829281146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_ mubi.829281146
Directory	/workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/19.pwrmgr_smoke.971381526
Short name	T499
Test name
Test status
Simulation time	30005225 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:56 PM PDT 24
Peak memory	198648 kb
Host	smart-749406a5-14c8-4f93-9083-7cf046e6cf44
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971381526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.971381526
Directory	/workspace/19.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/19.pwrmgr_wakeup.1268134184
Short name	T750
Test name
Test status
Simulation time	336229292 ps
CPU time	0.84 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	198972 kb
Host	smart-efdd0bc5-afb2-45d4-917b-3c9970715698
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268134184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1268134184
Directory	/workspace/19.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/19.pwrmgr_wakeup_reset.3060368521
Short name	T9
Test name
Test status
Simulation time	87553589 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	198672 kb
Host	smart-8c9c73a5-bf47-4e4b-bf9e-e05c2d8730f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060368521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.3060368521
Directory	/workspace/19.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/2.pwrmgr_aborted_low_power.4180510215
Short name	T639
Test name
Test status
Simulation time	34562594 ps
CPU time	0.7 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:09 PM PDT 24
Peak memory	197880 kb
Host	smart-97ff3725-a18b-41f7-bfc6-2d509d24e778
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180510215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.4180510215
Directory	/workspace/2.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3245970150
Short name	T228
Test name
Test status
Simulation time	32232330 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	197376 kb
Host	smart-34398202-9486-477e-bcd1-fc99b836d481
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245970150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_ malfunc.3245970150
Directory	/workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/2.pwrmgr_escalation_timeout.2188733326
Short name	T267
Test name
Test status
Simulation time	564441034 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:09 PM PDT 24
Peak memory	197652 kb
Host	smart-25d6e0db-72d7-4040-8a82-48ac1b2f1683
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188733326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2188733326
Directory	/workspace/2.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/2.pwrmgr_glitch.4021536421
Short name	T37
Test name
Test status
Simulation time	43935078 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:14 PM PDT 24
Peak memory	197464 kb
Host	smart-e26d07db-1bf6-498c-9c78-c3f7ed497060
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021536421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.4021536421
Directory	/workspace/2.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/2.pwrmgr_global_esc.1350248724
Short name	T399
Test name
Test status
Simulation time	25082270 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:07 PM PDT 24
Peak memory	197548 kb
Host	smart-88e0d784-28b2-4a95-ac8f-611fdca5a910
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350248724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1350248724
Directory	/workspace/2.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/2.pwrmgr_lowpower_invalid.4042110292
Short name	T481
Test name
Test status
Simulation time	47852895 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:09 PM PDT 24
Peak memory	200704 kb
Host	smart-9f172944-7f95-4ae0-9ffc-95bc795eb6e3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042110292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali d.4042110292
Directory	/workspace/2.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.1155172904
Short name	T63
Test name
Test status
Simulation time	181044388 ps
CPU time	0.78 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	197896 kb
Host	smart-1f8a9455-eeb3-41ed-a96f-82c704e1550b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155172904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa keup_race.1155172904
Directory	/workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/2.pwrmgr_reset.3023650057
Short name	T737
Test name
Test status
Simulation time	94917638 ps
CPU time	0.85 seconds
Started	Mar 17 01:44:16 PM PDT 24
Finished	Mar 17 01:44:16 PM PDT 24
Peak memory	199004 kb
Host	smart-f236d470-d82c-433d-a187-eaddfb042421
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023650057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3023650057
Directory	/workspace/2.pwrmgr_reset/latest

Test location	/workspace/coverage/default/2.pwrmgr_reset_invalid.3658306089
Short name	T155
Test name
Test status
Simulation time	177907258 ps
CPU time	0.77 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	208908 kb
Host	smart-6c671e22-f803-44ae-b5d6-5ebfdea834c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658306089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3658306089
Directory	/workspace/2.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/2.pwrmgr_sec_cm.559789845
Short name	T30
Test name
Test status
Simulation time	316250714 ps
CPU time	1.56 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:09 PM PDT 24
Peak memory	216472 kb
Host	smart-d1ded62d-9152-4887-ad96-81674440bfe5
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559789845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.559789845
Directory	/workspace/2.pwrmgr_sec_cm/latest

Test location	/workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3580261233
Short name	T853
Test name
Test status
Simulation time	48858220 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	198520 kb
Host	smart-95980182-7d74-48c1-85f3-21c7ea0bf7a7
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580261233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c m_ctrl_config_regwen.3580261233
Directory	/workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3107505530
Short name	T379
Test name
Test status
Simulation time	1270488436 ps
CPU time	2.28 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	200560 kb
Host	smart-bd073c9e-1dd8-45a9-9751-6a137f12a80c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107505530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3107505530
Directory	/workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3226883695
Short name	T810
Test name
Test status
Simulation time	2988493651 ps
CPU time	1.98 seconds
Started	Mar 17 01:44:09 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	200584 kb
Host	smart-4dfd77cc-f707-4a3a-9cdf-fdf18404426f
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226883695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3226883695
Directory	/workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.4067060358
Short name	T607
Test name
Test status
Simulation time	76183663 ps
CPU time	0.99 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:09 PM PDT 24
Peak memory	198500 kb
Host	smart-0fecfec0-6ee0-4cba-9d92-de5275b6ddbe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067060358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_ mubi.4067060358
Directory	/workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/2.pwrmgr_smoke.476355266
Short name	T695
Test name
Test status
Simulation time	76601658 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	197868 kb
Host	smart-2f99cb8b-1f60-4c23-83f8-344dd5ba6015
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476355266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.476355266
Directory	/workspace/2.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/2.pwrmgr_stress_all.3553063881
Short name	T16
Test name
Test status
Simulation time	1275283773 ps
CPU time	2.44 seconds
Started	Mar 17 01:44:08 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	200648 kb
Host	smart-4cb1e14f-98bd-462f-b8a8-a539f4122b60
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553063881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.3553063881
Directory	/workspace/2.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/2.pwrmgr_wakeup.1108694151
Short name	T765
Test name
Test status
Simulation time	272379344 ps
CPU time	0.86 seconds
Started	Mar 17 01:44:09 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	197896 kb
Host	smart-8b7dbff2-5710-487f-93d7-174522e1adaa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108694151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1108694151
Directory	/workspace/2.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/2.pwrmgr_wakeup_reset.1125644348
Short name	T720
Test name
Test status
Simulation time	197814618 ps
CPU time	0.83 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	198652 kb
Host	smart-40862a61-2515-4d57-9862-56ac26b5614a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125644348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1125644348
Directory	/workspace/2.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/20.pwrmgr_aborted_low_power.1408374128
Short name	T355
Test name
Test status
Simulation time	49499765 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	198020 kb
Host	smart-ce77f2e9-c8d2-4aae-be86-77c2c15337e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408374128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1408374128
Directory	/workspace/20.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1819611954
Short name	T754
Test name
Test status
Simulation time	198143407 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	198484 kb
Host	smart-9d3216d9-2bb4-4085-bf36-cf0d8f608ee7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819611954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis able_rom_integrity_check.1819611954
Directory	/workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2030928593
Short name	T438
Test name
Test status
Simulation time	30497330 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	196724 kb
Host	smart-6a1fefd0-10fc-4408-b321-b8b483260ce5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030928593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst _malfunc.2030928593
Directory	/workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/20.pwrmgr_escalation_timeout.2010254908
Short name	T548
Test name
Test status
Simulation time	608961339 ps
CPU time	0.98 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	197792 kb
Host	smart-a81be1ed-7690-4cf5-8581-f7e07d134e40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010254908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2010254908
Directory	/workspace/20.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/20.pwrmgr_glitch.500163076
Short name	T588
Test name
Test status
Simulation time	103765853 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:01 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	197508 kb
Host	smart-8901db84-efd7-46e6-9a35-9d755305ad81
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500163076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.500163076
Directory	/workspace/20.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/20.pwrmgr_global_esc.3936089861
Short name	T230
Test name
Test status
Simulation time	52774950 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197780 kb
Host	smart-b737a484-b68c-4fd9-b31d-4a8c607eccbf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936089861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3936089861
Directory	/workspace/20.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/20.pwrmgr_lowpower_invalid.2579302488
Short name	T545
Test name
Test status
Simulation time	54364438 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	200700 kb
Host	smart-3d3e5bc5-fe5d-4181-852e-c11b8d490964
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579302488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval id.2579302488
Directory	/workspace/20.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.2246859697
Short name	T893
Test name
Test status
Simulation time	123354361 ps
CPU time	0.89 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	197900 kb
Host	smart-66e172e9-73a5-4f02-a888-46e4857aaafb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246859697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w akeup_race.2246859697
Directory	/workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/20.pwrmgr_reset.3209541488
Short name	T503
Test name
Test status
Simulation time	96519217 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	197600 kb
Host	smart-6f1c3436-5190-4586-8009-c9651ff317eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209541488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3209541488
Directory	/workspace/20.pwrmgr_reset/latest

Test location	/workspace/coverage/default/20.pwrmgr_reset_invalid.3131991507
Short name	T546
Test name
Test status
Simulation time	163873552 ps
CPU time	0.75 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:21 PM PDT 24
Peak memory	208852 kb
Host	smart-fb629705-c1e3-43a5-b251-5c44a81b99ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131991507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3131991507
Directory	/workspace/20.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.1972274400
Short name	T402
Test name
Test status
Simulation time	75785340 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:01 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	197996 kb
Host	smart-14f75157-657b-4dc6-9aec-6f42594821da
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972274400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_ cm_ctrl_config_regwen.1972274400
Directory	/workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1207277833
Short name	T189
Test name
Test status
Simulation time	996860734 ps
CPU time	2.07 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	200412 kb
Host	smart-fd317d47-ae56-4d54-b318-f4bd1ae1facd
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207277833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1207277833
Directory	/workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.638475393
Short name	T126
Test name
Test status
Simulation time	1493698790 ps
CPU time	1.89 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	200548 kb
Host	smart-60b8d160-8933-4909-9c59-bcbaf90c388a
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638475393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.638475393
Directory	/workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1719998747
Short name	T29
Test name
Test status
Simulation time	178138967 ps
CPU time	0.9 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	198652 kb
Host	smart-0a4dd25d-5282-42ff-8ff8-56f4b71d5857
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719998747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig _mubi.1719998747
Directory	/workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/20.pwrmgr_smoke.3285332057
Short name	T533
Test name
Test status
Simulation time	45904453 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	198732 kb
Host	smart-599160b0-a994-41e9-9988-f278569f7e1a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285332057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3285332057
Directory	/workspace/20.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/20.pwrmgr_stress_all.3481051503
Short name	T398
Test name
Test status
Simulation time	1215672469 ps
CPU time	1.88 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	200616 kb
Host	smart-7be3bb19-bae2-4188-81c7-98087faff64b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481051503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.3481051503
Directory	/workspace/20.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/20.pwrmgr_wakeup.935545466
Short name	T348
Test name
Test status
Simulation time	136649352 ps
CPU time	0.82 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197808 kb
Host	smart-71892cd2-5a9d-4c19-ad88-535fd3da86a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935545466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.935545466
Directory	/workspace/20.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/20.pwrmgr_wakeup_reset.1371846082
Short name	T535
Test name
Test status
Simulation time	384351302 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	198568 kb
Host	smart-ec11cf06-50e7-4770-8d3b-75c87e1b91e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371846082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1371846082
Directory	/workspace/20.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/21.pwrmgr_aborted_low_power.1662728348
Short name	T406
Test name
Test status
Simulation time	33650664 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197920 kb
Host	smart-c1c65677-7163-4c94-ae56-d49f3568cbf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1662728348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1662728348
Directory	/workspace/21.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.2772052484
Short name	T46
Test name
Test status
Simulation time	62212251 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	197932 kb
Host	smart-0e478da5-c24d-4b86-9faa-b7aae47bbb53
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772052484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis able_rom_integrity_check.2772052484
Directory	/workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2533012665
Short name	T594
Test name
Test status
Simulation time	32791943 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	196752 kb
Host	smart-3ba64fd3-9115-4314-a2c3-1bfe2ae84dd5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533012665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst _malfunc.2533012665
Directory	/workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/21.pwrmgr_escalation_timeout.1070753842
Short name	T318
Test name
Test status
Simulation time	603356674 ps
CPU time	0.95 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197836 kb
Host	smart-9436bf7b-c5f5-4570-8538-2ce6b61decdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070753842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1070753842
Directory	/workspace/21.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/21.pwrmgr_glitch.949448081
Short name	T783
Test name
Test status
Simulation time	45514657 ps
CPU time	0.57 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:57 PM PDT 24
Peak memory	197412 kb
Host	smart-c7b66812-4fba-4aa4-a254-394a62ab6ebf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949448081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.949448081
Directory	/workspace/21.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/21.pwrmgr_global_esc.1458078976
Short name	T461
Test name
Test status
Simulation time	26919020 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197544 kb
Host	smart-cd5dfe63-d01b-471e-8da2-8d4fba55f6a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458078976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1458078976
Directory	/workspace/21.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/21.pwrmgr_lowpower_invalid.63068192
Short name	T542
Test name
Test status
Simulation time	83448588 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	200776 kb
Host	smart-8efb96ae-f692-4b38-a01a-53dc2924e977
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63068192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid .63068192
Directory	/workspace/21.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.1016832919
Short name	T493
Test name
Test status
Simulation time	219234492 ps
CPU time	0.86 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	197908 kb
Host	smart-848c1b2b-0b45-4f1f-8758-005e1cb860c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016832919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w akeup_race.1016832919
Directory	/workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/21.pwrmgr_reset.489878584
Short name	T755
Test name
Test status
Simulation time	71242728 ps
CPU time	0.79 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	199112 kb
Host	smart-7eed38c4-7d2a-4e28-8991-8cdfdb1d189f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489878584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.489878584
Directory	/workspace/21.pwrmgr_reset/latest

Test location	/workspace/coverage/default/21.pwrmgr_reset_invalid.1704354203
Short name	T304
Test name
Test status
Simulation time	108937697 ps
CPU time	0.93 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	208912 kb
Host	smart-e095e20a-9232-42c8-aade-3dfc92f184db
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704354203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1704354203
Directory	/workspace/21.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3705686994
Short name	T219
Test name
Test status
Simulation time	905374933 ps
CPU time	2.67 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	200548 kb
Host	smart-1af292b0-e24c-4de4-90e7-d37f6ffc9320
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705686994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3705686994
Directory	/workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3570406814
Short name	T489
Test name
Test status
Simulation time	914612048 ps
CPU time	3.2 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	200600 kb
Host	smart-29b1dbc1-e7d4-45ca-ad5c-273f163eb387
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570406814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3570406814
Directory	/workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.4161945520
Short name	T550
Test name
Test status
Simulation time	66827197 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	198676 kb
Host	smart-b194dc1e-ba09-487c-81ed-c1fc988cb67c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161945520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig _mubi.4161945520
Directory	/workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/21.pwrmgr_smoke.29655030
Short name	T367
Test name
Test status
Simulation time	42387258 ps
CPU time	0.67 seconds
Started	Mar 17 01:44:54 PM PDT 24
Finished	Mar 17 01:44:55 PM PDT 24
Peak memory	198740 kb
Host	smart-77a1b340-49ba-4399-9003-27009cf47298
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29655030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.29655030
Directory	/workspace/21.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/21.pwrmgr_stress_all.2382458321
Short name	T792
Test name
Test status
Simulation time	247441530 ps
CPU time	1.32 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	200056 kb
Host	smart-f1599ffb-2960-4776-aa95-038a62566abd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382458321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.2382458321
Directory	/workspace/21.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.3308755703
Short name	T24
Test name
Test status
Simulation time	21003541254 ps
CPU time	15.69 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	200860 kb
Host	smart-7c96f6e4-a6d1-4e51-a424-8b71cf352606
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308755703 -assert nopos tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.3308755703
Directory	/workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.pwrmgr_wakeup.2960325770
Short name	T388
Test name
Test status
Simulation time	209761670 ps
CPU time	0.78 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	197812 kb
Host	smart-b794d0f1-206d-40f9-a694-f4448e80ea6a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960325770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2960325770
Directory	/workspace/21.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/21.pwrmgr_wakeup_reset.1726931779
Short name	T779
Test name
Test status
Simulation time	422650766 ps
CPU time	1.26 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	200520 kb
Host	smart-a1ef3a1f-67bf-40e9-bf3a-4fe24ef9da9f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726931779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.1726931779
Directory	/workspace/21.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/22.pwrmgr_aborted_low_power.3959226991
Short name	T353
Test name
Test status
Simulation time	78762629 ps
CPU time	0.77 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	199332 kb
Host	smart-078439a7-e897-4dbe-99d2-85c92bc3b033
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959226991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3959226991
Directory	/workspace/22.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2064943960
Short name	T701
Test name
Test status
Simulation time	83331212 ps
CPU time	0.7 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	198020 kb
Host	smart-41ad91d1-8b5f-4ee7-b4a4-088da0af1642
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064943960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis able_rom_integrity_check.2064943960
Directory	/workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1281995262
Short name	T87
Test name
Test status
Simulation time	38727098 ps
CPU time	0.59 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	196656 kb
Host	smart-bd7ae863-6228-4722-966f-7c138cb4faf6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281995262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst _malfunc.1281995262
Directory	/workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/22.pwrmgr_escalation_timeout.595048300
Short name	T772
Test name
Test status
Simulation time	160441363 ps
CPU time	1.02 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	197524 kb
Host	smart-c2629e8d-6f34-4347-929c-0a22ec1e5dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595048300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.595048300
Directory	/workspace/22.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/22.pwrmgr_glitch.2994334201
Short name	T868
Test name
Test status
Simulation time	47521997 ps
CPU time	0.64 seconds
Started	Mar 17 01:45:12 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	197440 kb
Host	smart-aebeeb21-356a-4c4e-a0f3-ff2deeb7aa17
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994334201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2994334201
Directory	/workspace/22.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/22.pwrmgr_global_esc.4084303691
Short name	T392
Test name
Test status
Simulation time	102425738 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197468 kb
Host	smart-6acd8bdb-849e-4c88-a643-0e7118e50a47
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084303691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.4084303691
Directory	/workspace/22.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/22.pwrmgr_lowpower_invalid.1219917742
Short name	T366
Test name
Test status
Simulation time	45124180 ps
CPU time	0.7 seconds
Started	Mar 17 01:45:12 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	200712 kb
Host	smart-7f85e67f-e93a-47be-9f9a-f38bb6b8ef77
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219917742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval id.1219917742
Directory	/workspace/22.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/22.pwrmgr_reset.566168506
Short name	T288
Test name
Test status
Simulation time	65837325 ps
CPU time	0.85 seconds
Started	Mar 17 01:44:55 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	199188 kb
Host	smart-65346d03-9c8c-4843-aa28-9a908285f9d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566168506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.566168506
Directory	/workspace/22.pwrmgr_reset/latest

Test location	/workspace/coverage/default/22.pwrmgr_reset_invalid.796555697
Short name	T426
Test name
Test status
Simulation time	111222112 ps
CPU time	0.93 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	208888 kb
Host	smart-11cb339c-f640-4d54-87ad-3ce6468f55cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796555697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.796555697
Directory	/workspace/22.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.2350882937
Short name	T559
Test name
Test status
Simulation time	340619318 ps
CPU time	0.84 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	199312 kb
Host	smart-2e658d2e-74ea-44fe-8c86-9220526622cc
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350882937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_ cm_ctrl_config_regwen.2350882937
Directory	/workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3552415753
Short name	T898
Test name
Test status
Simulation time	827307840 ps
CPU time	2.69 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	200596 kb
Host	smart-31032bb8-ec8a-4422-a157-a9a081ea8e71
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552415753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3552415753
Directory	/workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2595110904
Short name	T331
Test name
Test status
Simulation time	1401071788 ps
CPU time	2.37 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	200528 kb
Host	smart-0ab33e56-3dd1-41e7-9fc1-879868f2fc51
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595110904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2595110904
Directory	/workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3037512024
Short name	T241
Test name
Test status
Simulation time	75323724 ps
CPU time	0.95 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	198824 kb
Host	smart-565b1b74-1f93-497b-9e59-211490566043
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037512024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig _mubi.3037512024
Directory	/workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/22.pwrmgr_smoke.567578018
Short name	T735
Test name
Test status
Simulation time	95125767 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:01 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	198752 kb
Host	smart-c5105047-27b7-4b16-b9d0-54147d2c4908
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567578018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.567578018
Directory	/workspace/22.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/22.pwrmgr_stress_all.2027163735
Short name	T791
Test name
Test status
Simulation time	297390958 ps
CPU time	0.82 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	199072 kb
Host	smart-7bf812c2-0ac8-4271-ae8f-5a11d3b4784f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027163735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.2027163735
Directory	/workspace/22.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/22.pwrmgr_wakeup_reset.407126140
Short name	T234
Test name
Test status
Simulation time	264305577 ps
CPU time	1.38 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	200352 kb
Host	smart-d6363dd7-cca8-4fd2-80bd-f2bd257b9a57
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407126140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.407126140
Directory	/workspace/22.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/23.pwrmgr_aborted_low_power.2208933450
Short name	T870
Test name
Test status
Simulation time	74121090 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197916 kb
Host	smart-ca4553ee-ced7-4418-ac33-d46103b6d004
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208933450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2208933450
Directory	/workspace/23.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3435210523
Short name	T878
Test name
Test status
Simulation time	78182806 ps
CPU time	0.73 seconds
Started	Mar 17 01:45:03 PM PDT 24
Finished	Mar 17 01:45:04 PM PDT 24
Peak memory	198120 kb
Host	smart-18e4816f-041f-4c3a-99d9-bb35017c11ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435210523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis able_rom_integrity_check.3435210523
Directory	/workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1279987444
Short name	T7
Test name
Test status
Simulation time	31791502 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	197404 kb
Host	smart-90ec796f-aac7-4ef8-ad5b-cb2b1c5cc1f5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279987444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst _malfunc.1279987444
Directory	/workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/23.pwrmgr_escalation_timeout.2236890996
Short name	T459
Test name
Test status
Simulation time	847921447 ps
CPU time	0.95 seconds
Started	Mar 17 01:45:17 PM PDT 24
Finished	Mar 17 01:45:18 PM PDT 24
Peak memory	197452 kb
Host	smart-f6a117c2-0e0a-4038-bddf-68128feab9f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236890996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.2236890996
Directory	/workspace/23.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/23.pwrmgr_glitch.1871982543
Short name	T226
Test name
Test status
Simulation time	75864080 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:58 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	196808 kb
Host	smart-9dcd3266-d5a4-4649-abec-8388cb16ec00
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871982543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1871982543
Directory	/workspace/23.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/23.pwrmgr_global_esc.514821898
Short name	T148
Test name
Test status
Simulation time	49512758 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197700 kb
Host	smart-0c4a194d-fb58-4e39-b64e-2b27e3ebbf4e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514821898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.514821898
Directory	/workspace/23.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/23.pwrmgr_lowpower_invalid.345104103
Short name	T342
Test name
Test status
Simulation time	82203352 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	200684 kb
Host	smart-b2c9c85f-ec6e-4ee7-9313-11871ae3ac69
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345104103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invali d.345104103
Directory	/workspace/23.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.1807206843
Short name	T277
Test name
Test status
Simulation time	373738810 ps
CPU time	1.01 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	199184 kb
Host	smart-694af2f2-3238-4739-9fa4-ccaee8908317
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807206843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w akeup_race.1807206843
Directory	/workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/23.pwrmgr_reset.4038630164
Short name	T193
Test name
Test status
Simulation time	51651402 ps
CPU time	0.82 seconds
Started	Mar 17 01:44:59 PM PDT 24
Finished	Mar 17 01:45:00 PM PDT 24
Peak memory	198104 kb
Host	smart-c73d5083-27ca-4cb5-894e-3844e7ea2a8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038630164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.4038630164
Directory	/workspace/23.pwrmgr_reset/latest

Test location	/workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1322753433
Short name	T473
Test name
Test status
Simulation time	974182052 ps
CPU time	2.19 seconds
Started	Mar 17 01:45:03 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	200648 kb
Host	smart-4456fc7c-5bfb-4c99-9556-1060b72ec671
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322753433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1322753433
Directory	/workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.125216731
Short name	T202
Test name
Test status
Simulation time	876809436 ps
CPU time	2.43 seconds
Started	Mar 17 01:45:08 PM PDT 24
Finished	Mar 17 01:45:10 PM PDT 24
Peak memory	200360 kb
Host	smart-6e2cafbe-cda7-4890-a9c1-7533b3717531
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125216731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.125216731
Directory	/workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3512683893
Short name	T22
Test name
Test status
Simulation time	72427932 ps
CPU time	1.04 seconds
Started	Mar 17 01:45:03 PM PDT 24
Finished	Mar 17 01:45:04 PM PDT 24
Peak memory	198652 kb
Host	smart-a02ff886-96b9-4f73-a1ce-9d6b8c744e4f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512683893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig _mubi.3512683893
Directory	/workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/23.pwrmgr_smoke.3464237604
Short name	T753
Test name
Test status
Simulation time	71351944 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:44:59 PM PDT 24
Peak memory	197816 kb
Host	smart-8386cda7-7576-4955-a808-44600736e461
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464237604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3464237604
Directory	/workspace/23.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/23.pwrmgr_stress_all.3160689958
Short name	T167
Test name
Test status
Simulation time	912496469 ps
CPU time	3.57 seconds
Started	Mar 17 01:44:57 PM PDT 24
Finished	Mar 17 01:45:02 PM PDT 24
Peak memory	200660 kb
Host	smart-62c901cd-1377-4136-b2ac-b5bbfefa9b19
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160689958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.3160689958
Directory	/workspace/23.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/23.pwrmgr_wakeup_reset.1097327478
Short name	T761
Test name
Test status
Simulation time	221032085 ps
CPU time	1.42 seconds
Started	Mar 17 01:45:00 PM PDT 24
Finished	Mar 17 01:45:01 PM PDT 24
Peak memory	200432 kb
Host	smart-836d9e6c-873c-4f09-989f-ab3266717182
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097327478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.1097327478
Directory	/workspace/23.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/24.pwrmgr_aborted_low_power.1493967548
Short name	T644
Test name
Test status
Simulation time	22398605 ps
CPU time	0.73 seconds
Started	Mar 17 01:45:06 PM PDT 24
Finished	Mar 17 01:45:07 PM PDT 24
Peak memory	197792 kb
Host	smart-e6fd1661-324a-43e4-b82d-98b0ab7a5d0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493967548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.1493967548
Directory	/workspace/24.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.4041879340
Short name	T884
Test name
Test status
Simulation time	85009403 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:09 PM PDT 24
Finished	Mar 17 01:45:10 PM PDT 24
Peak memory	198460 kb
Host	smart-ef056f6b-6ce8-4e39-9010-82dbb8360047
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041879340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis able_rom_integrity_check.4041879340
Directory	/workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3165088401
Short name	T605
Test name
Test status
Simulation time	39821232 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:09 PM PDT 24
Finished	Mar 17 01:45:10 PM PDT 24
Peak memory	196660 kb
Host	smart-c7807f86-5f8b-407c-82fc-43ca2a292f64
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165088401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst _malfunc.3165088401
Directory	/workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/24.pwrmgr_escalation_timeout.1034153047
Short name	T335
Test name
Test status
Simulation time	315687352 ps
CPU time	0.97 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	197796 kb
Host	smart-ce079d64-1d73-47de-9e26-5843ff6bf616
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034153047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.1034153047
Directory	/workspace/24.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/24.pwrmgr_glitch.356758719
Short name	T310
Test name
Test status
Simulation time	44257881 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	197440 kb
Host	smart-2b164e6a-3f5f-4994-a527-cb86268dd2e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356758719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.356758719
Directory	/workspace/24.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/24.pwrmgr_global_esc.291501140
Short name	T632
Test name
Test status
Simulation time	25808592 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:02 PM PDT 24
Finished	Mar 17 01:45:03 PM PDT 24
Peak memory	197524 kb
Host	smart-e32ce31b-6977-41f9-9d5d-b7db89a96a2c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291501140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.291501140
Directory	/workspace/24.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/24.pwrmgr_lowpower_invalid.3947459274
Short name	T222
Test name
Test status
Simulation time	81268779 ps
CPU time	0.7 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:05 PM PDT 24
Peak memory	200756 kb
Host	smart-3e951e54-d7ef-4dea-a543-e43f651f73f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947459274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval id.3947459274
Directory	/workspace/24.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.645988692
Short name	T592
Test name
Test status
Simulation time	40575156 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:56 PM PDT 24
Finished	Mar 17 01:44:58 PM PDT 24
Peak memory	198476 kb
Host	smart-3384d539-478b-4dfa-bb85-58ae7794d202
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645988692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wa keup_race.645988692
Directory	/workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/24.pwrmgr_reset.3522422211
Short name	T464
Test name
Test status
Simulation time	125062138 ps
CPU time	0.89 seconds
Started	Mar 17 01:45:02 PM PDT 24
Finished	Mar 17 01:45:03 PM PDT 24
Peak memory	199212 kb
Host	smart-86db7884-82ab-4ee7-8a85-781ffc258dd3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522422211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3522422211
Directory	/workspace/24.pwrmgr_reset/latest

Test location	/workspace/coverage/default/24.pwrmgr_reset_invalid.272860584
Short name	T295
Test name
Test status
Simulation time	151028099 ps
CPU time	0.84 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	208856 kb
Host	smart-2e742129-0942-47e9-835a-e572d226887d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272860584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.272860584
Directory	/workspace/24.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.2699513643
Short name	T80
Test name
Test status
Simulation time	79617478 ps
CPU time	0.73 seconds
Started	Mar 17 01:45:06 PM PDT 24
Finished	Mar 17 01:45:07 PM PDT 24
Peak memory	198236 kb
Host	smart-8495a291-c1d3-4672-b10d-15930c44c437
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699513643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_ cm_ctrl_config_regwen.2699513643
Directory	/workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1802454275
Short name	T198
Test name
Test status
Simulation time	1387285698 ps
CPU time	2.37 seconds
Started	Mar 17 01:45:02 PM PDT 24
Finished	Mar 17 01:45:05 PM PDT 24
Peak memory	200536 kb
Host	smart-f53487f0-8bd2-416d-96e9-b1d83e03bcb4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802454275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1802454275
Directory	/workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.9714599
Short name	T505
Test name
Test status
Simulation time	1073937122 ps
CPU time	2.12 seconds
Started	Mar 17 01:45:10 PM PDT 24
Finished	Mar 17 01:45:12 PM PDT 24
Peak memory	200624 kb
Host	smart-25db055e-5c04-45f4-9fc4-6cfb057fd1bf
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9714599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test + UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.9714599
Directory	/workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3140398662
Short name	T752
Test name
Test status
Simulation time	110820849 ps
CPU time	0.93 seconds
Started	Mar 17 01:45:08 PM PDT 24
Finished	Mar 17 01:45:10 PM PDT 24
Peak memory	198592 kb
Host	smart-56fca168-c8f4-4aec-ac6d-1d1aeda731ec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140398662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig _mubi.3140398662
Directory	/workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/24.pwrmgr_smoke.3259036432
Short name	T734
Test name
Test status
Simulation time	40546572 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:02 PM PDT 24
Finished	Mar 17 01:45:03 PM PDT 24
Peak memory	198728 kb
Host	smart-0255eb0f-738c-4f08-960c-bfdde379bc4a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259036432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.3259036432
Directory	/workspace/24.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/24.pwrmgr_stress_all.2140663447
Short name	T795
Test name
Test status
Simulation time	634071825 ps
CPU time	2.62 seconds
Started	Mar 17 01:45:02 PM PDT 24
Finished	Mar 17 01:45:04 PM PDT 24
Peak memory	200568 kb
Host	smart-2d9c4b53-7aac-482a-ad50-80981a0e1244
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140663447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2140663447
Directory	/workspace/24.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/24.pwrmgr_wakeup.1507614340
Short name	T169
Test name
Test status
Simulation time	238837470 ps
CPU time	1.16 seconds
Started	Mar 17 01:45:04 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	198844 kb
Host	smart-d499139a-7011-4c05-ae21-4d6ed2643769
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507614340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.1507614340
Directory	/workspace/24.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/24.pwrmgr_wakeup_reset.2062617139
Short name	T844
Test name
Test status
Simulation time	210651104 ps
CPU time	0.95 seconds
Started	Mar 17 01:45:04 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	199452 kb
Host	smart-64cb30c8-e852-440a-bf49-32fc5090dd74
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062617139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.2062617139
Directory	/workspace/24.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/25.pwrmgr_aborted_low_power.1877092964
Short name	T532
Test name
Test status
Simulation time	31058298 ps
CPU time	0.73 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	197984 kb
Host	smart-a69e63b0-7290-4343-b800-8d51b2f37634
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877092964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.1877092964
Directory	/workspace/25.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3245506390
Short name	T435
Test name
Test status
Simulation time	66205764 ps
CPU time	0.7 seconds
Started	Mar 17 01:45:17 PM PDT 24
Finished	Mar 17 01:45:19 PM PDT 24
Peak memory	198092 kb
Host	smart-91e9fdb7-6c9e-49bb-a245-ef1cae6e918a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245506390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis able_rom_integrity_check.3245506390
Directory	/workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3600090400
Short name	T343
Test name
Test status
Simulation time	30828666 ps
CPU time	0.73 seconds
Started	Mar 17 01:45:12 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	197480 kb
Host	smart-e7a634d5-9326-42c6-adc9-87d38303fcb6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600090400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst _malfunc.3600090400
Directory	/workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/25.pwrmgr_escalation_timeout.2847866564
Short name	T257
Test name
Test status
Simulation time	308457467 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:38 PM PDT 24
Finished	Mar 17 01:45:39 PM PDT 24
Peak memory	197516 kb
Host	smart-f203aff8-91b3-416c-8ad0-00ba9472db08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847866564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2847866564
Directory	/workspace/25.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/25.pwrmgr_glitch.1518700303
Short name	T725
Test name
Test status
Simulation time	49644576 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	196712 kb
Host	smart-1c716e9c-a782-4af3-bb2d-3551ef3915b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518700303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1518700303
Directory	/workspace/25.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/25.pwrmgr_global_esc.4069108859
Short name	T606
Test name
Test status
Simulation time	44061161 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	197748 kb
Host	smart-8de1c4cb-688a-4e31-98a9-5e370a1cb5ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069108859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.4069108859
Directory	/workspace/25.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/25.pwrmgr_lowpower_invalid.80573579
Short name	T255
Test name
Test status
Simulation time	49869485 ps
CPU time	0.75 seconds
Started	Mar 17 01:45:19 PM PDT 24
Finished	Mar 17 01:45:21 PM PDT 24
Peak memory	200716 kb
Host	smart-4958eba6-eef9-4da5-9ba6-ffc05007afee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80573579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid .80573579
Directory	/workspace/25.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.705149689
Short name	T173
Test name
Test status
Simulation time	574016446 ps
CPU time	0.92 seconds
Started	Mar 17 01:45:05 PM PDT 24
Finished	Mar 17 01:45:06 PM PDT 24
Peak memory	199208 kb
Host	smart-6a8fd9d7-8aac-410c-a392-2cf45eddb1a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705149689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wa keup_race.705149689
Directory	/workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/25.pwrmgr_reset.3271001063
Short name	T805
Test name
Test status
Simulation time	80104602 ps
CPU time	0.72 seconds
Started	Mar 17 01:45:11 PM PDT 24
Finished	Mar 17 01:45:12 PM PDT 24
Peak memory	198616 kb
Host	smart-2e7b9667-ebd1-4a69-8889-1a1755b1f9c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271001063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.3271001063
Directory	/workspace/25.pwrmgr_reset/latest

Test location	/workspace/coverage/default/25.pwrmgr_reset_invalid.4051380328
Short name	T220
Test name
Test status
Simulation time	99997678 ps
CPU time	1.09 seconds
Started	Mar 17 01:45:12 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	208876 kb
Host	smart-6654e785-98d5-45cb-8f66-17aff2139f66
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051380328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.4051380328
Directory	/workspace/25.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1798659931
Short name	T838
Test name
Test status
Simulation time	104484290 ps
CPU time	0.9 seconds
Started	Mar 17 01:45:12 PM PDT 24
Finished	Mar 17 01:45:13 PM PDT 24
Peak memory	198172 kb
Host	smart-44a73730-71a2-4950-9fcd-52d85f91b262
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798659931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_ cm_ctrl_config_regwen.1798659931
Directory	/workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.425761915
Short name	T585
Test name
Test status
Simulation time	1263377688 ps
CPU time	2.29 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:26 PM PDT 24
Peak memory	200608 kb
Host	smart-09f2c305-f7a4-44ce-b32f-ebd252c2fb3b
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425761915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.425761915
Directory	/workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1375611364
Short name	T547
Test name
Test status
Simulation time	52885217 ps
CPU time	0.9 seconds
Started	Mar 17 01:45:27 PM PDT 24
Finished	Mar 17 01:45:28 PM PDT 24
Peak memory	198676 kb
Host	smart-30ad39db-5466-47f3-9ee0-b553808238cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375611364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig _mubi.1375611364
Directory	/workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/25.pwrmgr_smoke.529944816
Short name	T865
Test name
Test status
Simulation time	38150143 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	198752 kb
Host	smart-be64c549-4650-4bbb-91d4-1bd2f66c0a58
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529944816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.529944816
Directory	/workspace/25.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/25.pwrmgr_stress_all.289721310
Short name	T260
Test name
Test status
Simulation time	1973621610 ps
CPU time	3.6 seconds
Started	Mar 17 01:45:15 PM PDT 24
Finished	Mar 17 01:45:19 PM PDT 24
Peak memory	200660 kb
Host	smart-91040c75-6540-4a70-ab90-0cf9473d29e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289721310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.289721310
Directory	/workspace/25.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.283639222
Short name	T25
Test name
Test status
Simulation time	19993138735 ps
CPU time	14.86 seconds
Started	Mar 17 01:45:15 PM PDT 24
Finished	Mar 17 01:45:30 PM PDT 24
Peak memory	200788 kb
Host	smart-a8d53253-6c1a-4a50-8d1b-bfe9030d9aaf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283639222 -assert nopost proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.283639222
Directory	/workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.pwrmgr_wakeup.676180067
Short name	T119
Test name
Test status
Simulation time	412525986 ps
CPU time	0.88 seconds
Started	Mar 17 01:45:02 PM PDT 24
Finished	Mar 17 01:45:03 PM PDT 24
Peak memory	199060 kb
Host	smart-e73d3fba-7424-4aa3-b8f9-04526b8e7474
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676180067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.676180067
Directory	/workspace/25.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/25.pwrmgr_wakeup_reset.2019640599
Short name	T727
Test name
Test status
Simulation time	63142922 ps
CPU time	0.84 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:14 PM PDT 24
Peak memory	198656 kb
Host	smart-5a2bddd7-f309-4dc8-aee9-df4b9eedf0a3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019640599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.2019640599
Directory	/workspace/25.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/26.pwrmgr_aborted_low_power.336207449
Short name	T488
Test name
Test status
Simulation time	41403445 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:11 PM PDT 24
Finished	Mar 17 01:45:12 PM PDT 24
Peak memory	198072 kb
Host	smart-83a1f437-3350-4dd6-baa7-653a349914d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336207449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.336207449
Directory	/workspace/26.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.1548269253
Short name	T270
Test name
Test status
Simulation time	54429064 ps
CPU time	0.81 seconds
Started	Mar 17 01:45:28 PM PDT 24
Finished	Mar 17 01:45:29 PM PDT 24
Peak memory	198560 kb
Host	smart-7a828626-4ea3-4322-90d7-424b9adb8058
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548269253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis able_rom_integrity_check.1548269253
Directory	/workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2784676696
Short name	T238
Test name
Test status
Simulation time	32432561 ps
CPU time	0.59 seconds
Started	Mar 17 01:45:29 PM PDT 24
Finished	Mar 17 01:45:30 PM PDT 24
Peak memory	197392 kb
Host	smart-1d152460-6d91-4c35-9807-b40bbc986f66
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784676696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst _malfunc.2784676696
Directory	/workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/26.pwrmgr_escalation_timeout.2404851053
Short name	T885
Test name
Test status
Simulation time	322658134 ps
CPU time	0.97 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	197520 kb
Host	smart-9efacb1e-3c04-4749-9754-0280c148c053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404851053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2404851053
Directory	/workspace/26.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/26.pwrmgr_glitch.818863805
Short name	T776
Test name
Test status
Simulation time	41213942 ps
CPU time	0.69 seconds
Started	Mar 17 01:45:09 PM PDT 24
Finished	Mar 17 01:45:11 PM PDT 24
Peak memory	197508 kb
Host	smart-590306e2-59bb-41b0-a485-1d101a4fea5f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818863805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.818863805
Directory	/workspace/26.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/26.pwrmgr_global_esc.4066454625
Short name	T647
Test name
Test status
Simulation time	46924903 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:11 PM PDT 24
Finished	Mar 17 01:45:12 PM PDT 24
Peak memory	197520 kb
Host	smart-332bdc0b-bf8b-44c0-9203-dab8c07928f5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066454625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.4066454625
Directory	/workspace/26.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/26.pwrmgr_lowpower_invalid.4163384215
Short name	T480
Test name
Test status
Simulation time	44360052 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	200764 kb
Host	smart-54ded680-f4f5-4e40-a15b-88a0eaed0675
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163384215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval id.4163384215
Directory	/workspace/26.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/26.pwrmgr_reset.111407953
Short name	T203
Test name
Test status
Simulation time	125612557 ps
CPU time	0.78 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:14 PM PDT 24
Peak memory	198520 kb
Host	smart-965fe1f7-9af3-40f8-8867-33d5adfdcf51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111407953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.111407953
Directory	/workspace/26.pwrmgr_reset/latest

Test location	/workspace/coverage/default/26.pwrmgr_reset_invalid.1688182213
Short name	T417
Test name
Test status
Simulation time	107201764 ps
CPU time	1.12 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:14 PM PDT 24
Peak memory	208776 kb
Host	smart-037e7d6a-c39f-46b5-b7e5-ed75daad0c68
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688182213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1688182213
Directory	/workspace/26.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.1103877789
Short name	T502
Test name
Test status
Simulation time	418778738 ps
CPU time	1.21 seconds
Started	Mar 17 01:45:09 PM PDT 24
Finished	Mar 17 01:45:10 PM PDT 24
Peak memory	200308 kb
Host	smart-6d56f990-1438-4164-be4a-0670d5d4b42d
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103877789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_ cm_ctrl_config_regwen.1103877789
Directory	/workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.917867243
Short name	T197
Test name
Test status
Simulation time	832369378 ps
CPU time	2.44 seconds
Started	Mar 17 01:45:33 PM PDT 24
Finished	Mar 17 01:45:36 PM PDT 24
Peak memory	200600 kb
Host	smart-9de4862c-7140-493f-93fa-fb04db37f90d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917867243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.917867243
Directory	/workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3296044275
Short name	T715
Test name
Test status
Simulation time	815630227 ps
CPU time	3.11 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:16 PM PDT 24
Peak memory	200484 kb
Host	smart-1e27b5ef-e127-4003-be73-e7fada43e70e
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296044275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3296044275
Directory	/workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.420018484
Short name	T621
Test name
Test status
Simulation time	102041585 ps
CPU time	0.95 seconds
Started	Mar 17 01:45:28 PM PDT 24
Finished	Mar 17 01:45:30 PM PDT 24
Peak memory	198744 kb
Host	smart-19aee7c7-c89c-4550-ae2f-1a9c0da51a94
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420018484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_ mubi.420018484
Directory	/workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/26.pwrmgr_smoke.1267161323
Short name	T89
Test name
Test status
Simulation time	105417681 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:14 PM PDT 24
Finished	Mar 17 01:45:15 PM PDT 24
Peak memory	197864 kb
Host	smart-ee8d373a-f359-489c-8b1e-3ba6ac1e97bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267161323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1267161323
Directory	/workspace/26.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/26.pwrmgr_wakeup.2694490307
Short name	T497
Test name
Test status
Simulation time	225047638 ps
CPU time	1.12 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	199052 kb
Host	smart-b7e8e421-7913-4492-a6f6-3bb20b6e7bc4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694490307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2694490307
Directory	/workspace/26.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/26.pwrmgr_wakeup_reset.974041708
Short name	T774
Test name
Test status
Simulation time	129246556 ps
CPU time	0.81 seconds
Started	Mar 17 01:45:10 PM PDT 24
Finished	Mar 17 01:45:12 PM PDT 24
Peak memory	197992 kb
Host	smart-94bb5457-60fc-4119-acb1-3089ff664456
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974041708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.974041708
Directory	/workspace/26.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/27.pwrmgr_aborted_low_power.634784938
Short name	T716
Test name
Test status
Simulation time	21643536 ps
CPU time	0.69 seconds
Started	Mar 17 01:45:31 PM PDT 24
Finished	Mar 17 01:45:32 PM PDT 24
Peak memory	197928 kb
Host	smart-9552527e-6662-4a00-9672-172e5d280aa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634784938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.634784938
Directory	/workspace/27.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1470966904
Short name	T896
Test name
Test status
Simulation time	66763010 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	199116 kb
Host	smart-28fbca5a-e5fe-4e20-a5a4-d83bfc40362d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470966904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis able_rom_integrity_check.1470966904
Directory	/workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1405439813
Short name	T557
Test name
Test status
Simulation time	32530384 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:10 PM PDT 24
Finished	Mar 17 01:45:11 PM PDT 24
Peak memory	197372 kb
Host	smart-386bfbf5-84fe-4288-8165-4f4625c90fba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405439813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst _malfunc.1405439813
Directory	/workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/27.pwrmgr_escalation_timeout.1700553947
Short name	T290
Test name
Test status
Simulation time	841643772 ps
CPU time	1.01 seconds
Started	Mar 17 01:45:37 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	197508 kb
Host	smart-4e7dbc17-5145-4f1e-9c7a-fce7a7ad3e4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700553947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1700553947
Directory	/workspace/27.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/27.pwrmgr_glitch.3784913089
Short name	T626
Test name
Test status
Simulation time	112343873 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:19 PM PDT 24
Finished	Mar 17 01:45:19 PM PDT 24
Peak memory	196836 kb
Host	smart-18317947-38e2-4e7d-a28e-40a51c87403b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784913089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3784913089
Directory	/workspace/27.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/27.pwrmgr_global_esc.1380926328
Short name	T391
Test name
Test status
Simulation time	25036581 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	197472 kb
Host	smart-5230ed00-4c21-4833-893e-c746b431f4d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380926328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1380926328
Directory	/workspace/27.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/27.pwrmgr_lowpower_invalid.224743591
Short name	T739
Test name
Test status
Simulation time	44255115 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:20 PM PDT 24
Finished	Mar 17 01:45:21 PM PDT 24
Peak memory	200792 kb
Host	smart-f4f2a6e7-5952-40b3-9e8a-e2e55961bf68
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224743591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali d.224743591
Directory	/workspace/27.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/27.pwrmgr_reset.1704975829
Short name	T496
Test name
Test status
Simulation time	88806644 ps
CPU time	0.87 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:14 PM PDT 24
Peak memory	199316 kb
Host	smart-e3a3c895-f7c5-41e9-b22d-9056ee9fa5be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704975829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1704975829
Directory	/workspace/27.pwrmgr_reset/latest

Test location	/workspace/coverage/default/27.pwrmgr_reset_invalid.332737024
Short name	T158
Test name
Test status
Simulation time	156931756 ps
CPU time	0.78 seconds
Started	Mar 17 01:45:30 PM PDT 24
Finished	Mar 17 01:45:31 PM PDT 24
Peak memory	208840 kb
Host	smart-9ed0b888-b0cf-4ef1-a035-2d2b393dd739
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332737024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.332737024
Directory	/workspace/27.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.970412086
Short name	T451
Test name
Test status
Simulation time	724326135 ps
CPU time	2.78 seconds
Started	Mar 17 01:45:26 PM PDT 24
Finished	Mar 17 01:45:29 PM PDT 24
Peak memory	200712 kb
Host	smart-88f48af0-dbba-425e-9edd-0676e68e82b0
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970412086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.970412086
Directory	/workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3191544482
Short name	T82
Test name
Test status
Simulation time	1300017019 ps
CPU time	2.39 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:16 PM PDT 24
Peak memory	200552 kb
Host	smart-181ecc9c-b296-45be-b5b7-59a180c6e91d
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191544482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3191544482
Directory	/workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.281401240
Short name	T376
Test name
Test status
Simulation time	131655844 ps
CPU time	1.05 seconds
Started	Mar 17 01:45:13 PM PDT 24
Finished	Mar 17 01:45:14 PM PDT 24
Peak memory	199028 kb
Host	smart-f6805500-bfff-4ba6-bb63-bad608994dbf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281401240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_ mubi.281401240
Directory	/workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/27.pwrmgr_smoke.1831530625
Short name	T723
Test name
Test status
Simulation time	32921976 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:31 PM PDT 24
Finished	Mar 17 01:45:31 PM PDT 24
Peak memory	197852 kb
Host	smart-0e04be25-ef9d-4aa8-a103-2fb3da2b32ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831530625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.1831530625
Directory	/workspace/27.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/27.pwrmgr_stress_all.3374782723
Short name	T394
Test name
Test status
Simulation time	419721819 ps
CPU time	1.08 seconds
Started	Mar 17 01:45:23 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	200408 kb
Host	smart-631b0ca3-0f5e-4828-b181-133c525afb11
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374782723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.3374782723
Directory	/workspace/27.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/27.pwrmgr_wakeup.3759201017
Short name	T316
Test name
Test status
Simulation time	355298271 ps
CPU time	0.93 seconds
Started	Mar 17 01:45:10 PM PDT 24
Finished	Mar 17 01:45:11 PM PDT 24
Peak memory	198932 kb
Host	smart-0587c989-0487-4448-bc1d-21b7d044b12d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759201017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.3759201017
Directory	/workspace/27.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/27.pwrmgr_wakeup_reset.3975071579
Short name	T726
Test name
Test status
Simulation time	206196221 ps
CPU time	0.83 seconds
Started	Mar 17 01:45:10 PM PDT 24
Finished	Mar 17 01:45:12 PM PDT 24
Peak memory	199044 kb
Host	smart-6f2760cc-9be9-4ae0-8086-ea90bb4b439c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975071579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.3975071579
Directory	/workspace/27.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/28.pwrmgr_aborted_low_power.1078282507
Short name	T778
Test name
Test status
Simulation time	62623753 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:23 PM PDT 24
Finished	Mar 17 01:45:24 PM PDT 24
Peak memory	197964 kb
Host	smart-a6d6f4e4-2fd5-4df2-a629-1d093d3ce274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078282507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.1078282507
Directory	/workspace/28.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.1011014982
Short name	T122
Test name
Test status
Simulation time	91514863 ps
CPU time	0.72 seconds
Started	Mar 17 01:45:37 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	198224 kb
Host	smart-8fdbb035-1166-46cc-85af-68a450bfb82e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011014982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis able_rom_integrity_check.1011014982
Directory	/workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.82965857
Short name	T39
Test name
Test status
Simulation time	38106503 ps
CPU time	0.59 seconds
Started	Mar 17 01:45:21 PM PDT 24
Finished	Mar 17 01:45:21 PM PDT 24
Peak memory	197352 kb
Host	smart-f8e504e9-15d9-4833-b041-3a913edeb52b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82965857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_m alfunc.82965857
Directory	/workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/28.pwrmgr_escalation_timeout.21128814
Short name	T305
Test name
Test status
Simulation time	319882535 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:37 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	197488 kb
Host	smart-10b502f4-afda-4e23-8d64-643d3b625f04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21128814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.21128814
Directory	/workspace/28.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/28.pwrmgr_glitch.3252919133
Short name	T707
Test name
Test status
Simulation time	83822167 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:31 PM PDT 24
Finished	Mar 17 01:45:32 PM PDT 24
Peak memory	197524 kb
Host	smart-ec2dfd5a-b72e-4412-bbaf-701c597f691b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252919133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3252919133
Directory	/workspace/28.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/28.pwrmgr_global_esc.2093884581
Short name	T285
Test name
Test status
Simulation time	86296571 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:24 PM PDT 24
Peak memory	197792 kb
Host	smart-62484485-436f-4e8c-b183-58a0ab1b1942
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093884581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2093884581
Directory	/workspace/28.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/28.pwrmgr_lowpower_invalid.2279679472
Short name	T463
Test name
Test status
Simulation time	46357217 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:21 PM PDT 24
Finished	Mar 17 01:45:22 PM PDT 24
Peak memory	200720 kb
Host	smart-156ec0cf-1ceb-4046-a330-01c321f48081
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279679472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval id.2279679472
Directory	/workspace/28.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.1498117103
Short name	T881
Test name
Test status
Simulation time	52566817 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:20 PM PDT 24
Finished	Mar 17 01:45:21 PM PDT 24
Peak memory	197624 kb
Host	smart-8d33227f-abe1-4f23-9d55-fe310f3be42d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498117103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w akeup_race.1498117103
Directory	/workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/28.pwrmgr_reset.1054695675
Short name	T45
Test name
Test status
Simulation time	121377336 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:21 PM PDT 24
Finished	Mar 17 01:45:22 PM PDT 24
Peak memory	199424 kb
Host	smart-ecadf2d7-7c33-4cd6-bd3a-bf29d0ec3c4e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054695675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1054695675
Directory	/workspace/28.pwrmgr_reset/latest

Test location	/workspace/coverage/default/28.pwrmgr_reset_invalid.261017180
Short name	T393
Test name
Test status
Simulation time	122218342 ps
CPU time	0.86 seconds
Started	Mar 17 01:45:35 PM PDT 24
Finished	Mar 17 01:45:36 PM PDT 24
Peak memory	208816 kb
Host	smart-115bd1d6-9b38-4646-bbd8-9f57efe5b0ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261017180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.261017180
Directory	/workspace/28.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.3127143074
Short name	T640
Test name
Test status
Simulation time	163813124 ps
CPU time	1.04 seconds
Started	Mar 17 01:45:35 PM PDT 24
Finished	Mar 17 01:45:37 PM PDT 24
Peak memory	199496 kb
Host	smart-5d2e822f-fcc3-469d-959d-e6753773449b
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127143074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_ cm_ctrl_config_regwen.3127143074
Directory	/workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2209411795
Short name	T615
Test name
Test status
Simulation time	769876809 ps
CPU time	3.01 seconds
Started	Mar 17 01:45:22 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	200644 kb
Host	smart-f5b91e1a-fabc-40f9-ab0d-840f95d72270
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209411795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2209411795
Directory	/workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1529117181
Short name	T721
Test name
Test status
Simulation time	303905510 ps
CPU time	0.86 seconds
Started	Mar 17 01:45:31 PM PDT 24
Finished	Mar 17 01:45:32 PM PDT 24
Peak memory	198592 kb
Host	smart-15a39907-36c8-45c9-a3b5-5b34ba1bc18c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529117181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig _mubi.1529117181
Directory	/workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/28.pwrmgr_smoke.2109779024
Short name	T563
Test name
Test status
Simulation time	66978557 ps
CPU time	0.64 seconds
Started	Mar 17 01:45:19 PM PDT 24
Finished	Mar 17 01:45:20 PM PDT 24
Peak memory	197836 kb
Host	smart-75f30934-034d-4751-98af-4663d7f27651
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109779024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2109779024
Directory	/workspace/28.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/28.pwrmgr_stress_all.609846639
Short name	T15
Test name
Test status
Simulation time	280767589 ps
CPU time	1.64 seconds
Started	Mar 17 01:45:36 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	200692 kb
Host	smart-714eb7b3-ee5e-48f6-9b0d-d14243cf0dba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609846639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.609846639
Directory	/workspace/28.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2801454794
Short name	T118
Test name
Test status
Simulation time	13193338606 ps
CPU time	9.59 seconds
Started	Mar 17 01:45:37 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	200828 kb
Host	smart-93636161-3764-45a0-99f4-f24d7b398e07
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801454794 -assert nopos tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.2801454794
Directory	/workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.pwrmgr_wakeup.435470542
Short name	T808
Test name
Test status
Simulation time	285847610 ps
CPU time	0.86 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	198932 kb
Host	smart-3b8d2f69-d5b4-491a-a720-f1f1725741e3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435470542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.435470542
Directory	/workspace/28.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/28.pwrmgr_wakeup_reset.3383525345
Short name	T326
Test name
Test status
Simulation time	459084180 ps
CPU time	1.16 seconds
Started	Mar 17 01:45:19 PM PDT 24
Finished	Mar 17 01:45:21 PM PDT 24
Peak memory	200460 kb
Host	smart-aa2bf460-dbd7-424b-acdc-d2db515c18db
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383525345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.3383525345
Directory	/workspace/28.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/29.pwrmgr_aborted_low_power.1742628313
Short name	T598
Test name
Test status
Simulation time	176513033 ps
CPU time	0.78 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	198116 kb
Host	smart-b79a4016-8caa-4690-93b5-b02a3c5902d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742628313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.1742628313
Directory	/workspace/29.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.1163448219
Short name	T638
Test name
Test status
Simulation time	54934799 ps
CPU time	0.79 seconds
Started	Mar 17 01:45:38 PM PDT 24
Finished	Mar 17 01:45:39 PM PDT 24
Peak memory	198552 kb
Host	smart-a81ac927-5ab9-42a8-9d7f-efb7cbe1c5ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163448219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis able_rom_integrity_check.1163448219
Directory	/workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.112974506
Short name	T153
Test name
Test status
Simulation time	30950679 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:37 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	197472 kb
Host	smart-54439389-bb0c-4591-9ea8-1817d3526923
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112974506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_ malfunc.112974506
Directory	/workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/29.pwrmgr_escalation_timeout.1110008334
Short name	T706
Test name
Test status
Simulation time	165220890 ps
CPU time	1 seconds
Started	Mar 17 01:45:26 PM PDT 24
Finished	Mar 17 01:45:27 PM PDT 24
Peak memory	197536 kb
Host	smart-15f46c06-2d6c-492c-9f40-4d40c905d128
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110008334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1110008334
Directory	/workspace/29.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/29.pwrmgr_glitch.2988092240
Short name	T431
Test name
Test status
Simulation time	60253824 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:20 PM PDT 24
Finished	Mar 17 01:45:21 PM PDT 24
Peak memory	197512 kb
Host	smart-67449226-7cb8-48e1-9bc6-68cc5bde6559
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988092240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2988092240
Directory	/workspace/29.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/29.pwrmgr_global_esc.3599737475
Short name	T166
Test name
Test status
Simulation time	107163952 ps
CPU time	0.64 seconds
Started	Mar 17 01:45:21 PM PDT 24
Finished	Mar 17 01:45:22 PM PDT 24
Peak memory	197768 kb
Host	smart-51fa7d53-155d-4539-89fd-5fdc769b63dd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599737475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3599737475
Directory	/workspace/29.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/29.pwrmgr_lowpower_invalid.3615709970
Short name	T663
Test name
Test status
Simulation time	120764802 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:29 PM PDT 24
Finished	Mar 17 01:45:30 PM PDT 24
Peak memory	200736 kb
Host	smart-3e134ed9-88e9-4184-a44d-4288a52eeb49
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615709970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval id.3615709970
Directory	/workspace/29.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.1355085292
Short name	T231
Test name
Test status
Simulation time	82042423 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:37 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	197668 kb
Host	smart-8373e22f-09eb-4bbe-89a6-d4ae21f0dd36
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355085292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w akeup_race.1355085292
Directory	/workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/29.pwrmgr_reset.3076511464
Short name	T472
Test name
Test status
Simulation time	161355441 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:28 PM PDT 24
Finished	Mar 17 01:45:29 PM PDT 24
Peak memory	199404 kb
Host	smart-634c94d4-a597-44c8-8cf7-8c0d80cda957
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076511464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3076511464
Directory	/workspace/29.pwrmgr_reset/latest

Test location	/workspace/coverage/default/29.pwrmgr_reset_invalid.3791523474
Short name	T467
Test name
Test status
Simulation time	156301464 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:38 PM PDT 24
Finished	Mar 17 01:45:39 PM PDT 24
Peak memory	200644 kb
Host	smart-03c95631-9f63-45b8-87c5-43e817efa8ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791523474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3791523474
Directory	/workspace/29.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.994799326
Short name	T869
Test name
Test status
Simulation time	477090942 ps
CPU time	1.1 seconds
Started	Mar 17 01:45:34 PM PDT 24
Finished	Mar 17 01:45:35 PM PDT 24
Peak memory	200216 kb
Host	smart-cd4d538a-7a05-4619-a71c-4a4635370774
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994799326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_c m_ctrl_config_regwen.994799326
Directory	/workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3011092365
Short name	T894
Test name
Test status
Simulation time	854148364 ps
CPU time	2.4 seconds
Started	Mar 17 01:45:35 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	200620 kb
Host	smart-8e0e7e53-0cef-491a-9069-4a6791dff364
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011092365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3011092365
Directory	/workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.944050002
Short name	T210
Test name
Test status
Simulation time	954851388 ps
CPU time	2.32 seconds
Started	Mar 17 01:45:36 PM PDT 24
Finished	Mar 17 01:45:38 PM PDT 24
Peak memory	200580 kb
Host	smart-dcb26b12-5e79-4a23-b3ca-9fa7e272188f
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944050002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.944050002
Directory	/workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3440206194
Short name	T665
Test name
Test status
Simulation time	67482721 ps
CPU time	0.9 seconds
Started	Mar 17 01:45:25 PM PDT 24
Finished	Mar 17 01:45:26 PM PDT 24
Peak memory	198424 kb
Host	smart-df9e94db-482d-4db1-994f-2d83a629a717
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440206194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig _mubi.3440206194
Directory	/workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/29.pwrmgr_smoke.3831655839
Short name	T690
Test name
Test status
Simulation time	44334111 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:35 PM PDT 24
Finished	Mar 17 01:45:36 PM PDT 24
Peak memory	198760 kb
Host	smart-9e857acb-5699-4a3c-8a77-4fc3135dd996
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831655839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.3831655839
Directory	/workspace/29.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/29.pwrmgr_wakeup.2584288223
Short name	T668
Test name
Test status
Simulation time	462525939 ps
CPU time	0.93 seconds
Started	Mar 17 01:45:30 PM PDT 24
Finished	Mar 17 01:45:31 PM PDT 24
Peak memory	198956 kb
Host	smart-c6c3006e-81a5-4b6f-a911-5a9a61cd5fd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584288223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.2584288223
Directory	/workspace/29.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/29.pwrmgr_wakeup_reset.3836471795
Short name	T77
Test name
Test status
Simulation time	522986898 ps
CPU time	1.17 seconds
Started	Mar 17 01:45:31 PM PDT 24
Finished	Mar 17 01:45:32 PM PDT 24
Peak memory	200500 kb
Host	smart-42a088ff-4504-4fd4-a2db-907b5b907d97
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836471795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.3836471795
Directory	/workspace/29.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/3.pwrmgr_aborted_low_power.4268182657
Short name	T649
Test name
Test status
Simulation time	93218532 ps
CPU time	0.82 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	199324 kb
Host	smart-2772141b-f51e-403d-a77a-b270bc2300ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268182657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.4268182657
Directory	/workspace/3.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.690878824
Short name	T422
Test name
Test status
Simulation time	64515929 ps
CPU time	0.7 seconds
Started	Mar 17 01:44:14 PM PDT 24
Finished	Mar 17 01:44:15 PM PDT 24
Peak memory	198004 kb
Host	smart-ee21768f-e394-4b6f-8763-365715a67d2c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690878824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disab le_rom_integrity_check.690878824
Directory	/workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2106872069
Short name	T675
Test name
Test status
Simulation time	32401160 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	197380 kb
Host	smart-c0006d0f-0694-4f89-b792-5490050abbf2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106872069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_ malfunc.2106872069
Directory	/workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/3.pwrmgr_escalation_timeout.645525979
Short name	T11
Test name
Test status
Simulation time	161385930 ps
CPU time	0.98 seconds
Started	Mar 17 01:44:12 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	197524 kb
Host	smart-a7944aa9-6f52-4b0e-b5c4-76db0a571058
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645525979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.645525979
Directory	/workspace/3.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/3.pwrmgr_glitch.4041311729
Short name	T652
Test name
Test status
Simulation time	60240071 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:12 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	197500 kb
Host	smart-0faef4c7-32a7-427e-9d1e-56697cc771bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041311729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.4041311729
Directory	/workspace/3.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/3.pwrmgr_global_esc.582670874
Short name	T833
Test name
Test status
Simulation time	44143274 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:12 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	197448 kb
Host	smart-6e1dee22-0286-4058-91c2-3d38686136ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582670874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.582670874
Directory	/workspace/3.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/3.pwrmgr_lowpower_invalid.1254093760
Short name	T341
Test name
Test status
Simulation time	76041190 ps
CPU time	0.67 seconds
Started	Mar 17 01:44:16 PM PDT 24
Finished	Mar 17 01:44:17 PM PDT 24
Peak memory	200692 kb
Host	smart-1ab26c8c-1783-487e-9319-c15ef9a3cb20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254093760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali d.1254093760
Directory	/workspace/3.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.399519461
Short name	T730
Test name
Test status
Simulation time	82714755 ps
CPU time	0.79 seconds
Started	Mar 17 01:44:07 PM PDT 24
Finished	Mar 17 01:44:07 PM PDT 24
Peak memory	197588 kb
Host	smart-2093c698-d202-4609-be9e-7ae43ddd7474
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399519461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wak eup_race.399519461
Directory	/workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/3.pwrmgr_reset.3018087935
Short name	T728
Test name
Test status
Simulation time	147116691 ps
CPU time	0.75 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	198624 kb
Host	smart-9140ab98-8b26-4cb4-ac30-6801b085e8de
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018087935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.3018087935
Directory	/workspace/3.pwrmgr_reset/latest

Test location	/workspace/coverage/default/3.pwrmgr_reset_invalid.2412955601
Short name	T700
Test name
Test status
Simulation time	241684042 ps
CPU time	0.81 seconds
Started	Mar 17 01:44:22 PM PDT 24
Finished	Mar 17 01:44:23 PM PDT 24
Peak memory	208892 kb
Host	smart-bcb861e8-e764-46a0-92d8-d27999ac1f1e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412955601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2412955601
Directory	/workspace/3.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/3.pwrmgr_sec_cm.2102460718
Short name	T20
Test name
Test status
Simulation time	909215698 ps
CPU time	1.44 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	216376 kb
Host	smart-ce90fed0-5adb-4b0c-b92a-8e335d867917
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102460718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2102460718
Directory	/workspace/3.pwrmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.810394048
Short name	T850
Test name
Test status
Simulation time	154260054 ps
CPU time	1.05 seconds
Started	Mar 17 01:44:14 PM PDT 24
Finished	Mar 17 01:44:16 PM PDT 24
Peak memory	199116 kb
Host	smart-430194f5-52a3-4f2c-bd28-0cd533ee061a
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810394048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm _ctrl_config_regwen.810394048
Directory	/workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.488843765
Short name	T195
Test name
Test status
Simulation time	1025013996 ps
CPU time	2.61 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	200332 kb
Host	smart-8bfad412-9dd3-40c6-9f97-3d1cace886d6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488843765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.488843765
Directory	/workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1468610345
Short name	T180
Test name
Test status
Simulation time	845221727 ps
CPU time	3.24 seconds
Started	Mar 17 01:44:09 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	200632 kb
Host	smart-a8a68f0c-3f06-4195-a87d-9a7029538660
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468610345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1468610345
Directory	/workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3934603415
Short name	T243
Test name
Test status
Simulation time	88149325 ps
CPU time	0.83 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	199064 kb
Host	smart-15174f59-0de9-46bf-a906-ac5b7ddf1c9f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934603415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_ mubi.3934603415
Directory	/workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/3.pwrmgr_smoke.1519979657
Short name	T591
Test name
Test status
Simulation time	62681019 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	197824 kb
Host	smart-9e4196ea-6756-42e4-b169-8cdd0e52f405
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519979657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1519979657
Directory	/workspace/3.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/3.pwrmgr_wakeup.2387890796
Short name	T254
Test name
Test status
Simulation time	338666278 ps
CPU time	0.93 seconds
Started	Mar 17 01:44:10 PM PDT 24
Finished	Mar 17 01:44:11 PM PDT 24
Peak memory	198860 kb
Host	smart-0b67f914-7e02-404d-aa47-3f68605eda8c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387890796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.2387890796
Directory	/workspace/3.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/3.pwrmgr_wakeup_reset.1315575673
Short name	T150
Test name
Test status
Simulation time	92374434 ps
CPU time	0.68 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:14 PM PDT 24
Peak memory	198500 kb
Host	smart-4d858bfa-f7b6-4b97-b001-56e7096943c9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315575673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.1315575673
Directory	/workspace/3.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/30.pwrmgr_aborted_low_power.360655012
Short name	T165
Test name
Test status
Simulation time	43052204 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:38 PM PDT 24
Finished	Mar 17 01:45:39 PM PDT 24
Peak memory	197920 kb
Host	smart-677b6b73-69df-429b-9f70-5027fa44f40a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360655012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.360655012
Directory	/workspace/30.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3658328148
Short name	T741
Test name
Test status
Simulation time	28082729 ps
CPU time	0.64 seconds
Started	Mar 17 01:45:33 PM PDT 24
Finished	Mar 17 01:45:35 PM PDT 24
Peak memory	196676 kb
Host	smart-6b8c5832-ac88-44be-b520-3701143c24f9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658328148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst _malfunc.3658328148
Directory	/workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/30.pwrmgr_escalation_timeout.2388724858
Short name	T834
Test name
Test status
Simulation time	164882670 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:27 PM PDT 24
Finished	Mar 17 01:45:28 PM PDT 24
Peak memory	197544 kb
Host	smart-7f6faffc-d186-430c-bff2-8e62026a02db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388724858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.2388724858
Directory	/workspace/30.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/30.pwrmgr_glitch.2469318653
Short name	T415
Test name
Test status
Simulation time	144043702 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:25 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	196796 kb
Host	smart-cd4c3af0-ff54-40ae-b51b-a5d8da4bf60f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469318653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2469318653
Directory	/workspace/30.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/30.pwrmgr_global_esc.1797020382
Short name	T292
Test name
Test status
Simulation time	44421724 ps
CPU time	0.58 seconds
Started	Mar 17 01:45:24 PM PDT 24
Finished	Mar 17 01:45:25 PM PDT 24
Peak memory	197504 kb
Host	smart-88d50977-08d7-46cf-bf3c-a11c81f546af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797020382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1797020382
Directory	/workspace/30.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/30.pwrmgr_lowpower_invalid.916454153
Short name	T494
Test name
Test status
Simulation time	44680110 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:28 PM PDT 24
Finished	Mar 17 01:45:28 PM PDT 24
Peak memory	200832 kb
Host	smart-b6deaeed-a45d-4d8c-9151-3c979aa3321c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916454153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invali d.916454153
Directory	/workspace/30.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.1525139858
Short name	T573
Test name
Test status
Simulation time	36412324 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:41 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	197616 kb
Host	smart-6119d5c3-1bc6-42d8-8437-563f211e03ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525139858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w akeup_race.1525139858
Directory	/workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/30.pwrmgr_reset.3866528396
Short name	T687
Test name
Test status
Simulation time	47951095 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:26 PM PDT 24
Finished	Mar 17 01:45:27 PM PDT 24
Peak memory	197752 kb
Host	smart-b608c6dc-a24d-4590-837a-884051a80042
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866528396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.3866528396
Directory	/workspace/30.pwrmgr_reset/latest

Test location	/workspace/coverage/default/30.pwrmgr_reset_invalid.4179793445
Short name	T330
Test name
Test status
Simulation time	105714586 ps
CPU time	0.92 seconds
Started	Mar 17 01:45:39 PM PDT 24
Finished	Mar 17 01:45:40 PM PDT 24
Peak memory	208832 kb
Host	smart-c6a0e0b2-a3d0-4736-9065-7e9942efcd41
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179793445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.4179793445
Directory	/workspace/30.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.3853210697
Short name	T61
Test name
Test status
Simulation time	233918501 ps
CPU time	0.82 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	199436 kb
Host	smart-dfb9a495-86a6-4cf8-a199-9ceb81848968
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853210697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_ cm_ctrl_config_regwen.3853210697
Directory	/workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2212733692
Short name	T841
Test name
Test status
Simulation time	1057983434 ps
CPU time	2.67 seconds
Started	Mar 17 01:45:26 PM PDT 24
Finished	Mar 17 01:45:29 PM PDT 24
Peak memory	200484 kb
Host	smart-2d10d7dd-e447-47c4-a3a0-9dc97916a21d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212733692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2212733692
Directory	/workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3312399515
Short name	T824
Test name
Test status
Simulation time	1121196887 ps
CPU time	1.92 seconds
Started	Mar 17 01:45:26 PM PDT 24
Finished	Mar 17 01:45:28 PM PDT 24
Peak memory	200484 kb
Host	smart-8f3c6581-a1d3-41a6-9aaa-6a6f83760c0c
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312399515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3312399515
Directory	/workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.355443890
Short name	T35
Test name
Test status
Simulation time	145713635 ps
CPU time	0.88 seconds
Started	Mar 17 01:45:26 PM PDT 24
Finished	Mar 17 01:45:27 PM PDT 24
Peak memory	199056 kb
Host	smart-c41f3856-d200-4df3-82a9-b61457487a4c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355443890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_ mubi.355443890
Directory	/workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/30.pwrmgr_smoke.279742985
Short name	T286
Test name
Test status
Simulation time	31857754 ps
CPU time	0.69 seconds
Started	Mar 17 01:45:25 PM PDT 24
Finished	Mar 17 01:45:26 PM PDT 24
Peak memory	198672 kb
Host	smart-841c4c0c-3259-4d8b-87e6-5c67590bead8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279742985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.279742985
Directory	/workspace/30.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/30.pwrmgr_wakeup_reset.1375302828
Short name	T567
Test name
Test status
Simulation time	115873132 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:37 PM PDT 24
Finished	Mar 17 01:45:37 PM PDT 24
Peak memory	198752 kb
Host	smart-33c1ba36-98ac-4850-9b85-ac8b45976e79
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375302828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.1375302828
Directory	/workspace/30.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/31.pwrmgr_aborted_low_power.1832207379
Short name	T787
Test name
Test status
Simulation time	189042568 ps
CPU time	0.76 seconds
Started	Mar 17 01:45:25 PM PDT 24
Finished	Mar 17 01:45:26 PM PDT 24
Peak memory	198156 kb
Host	smart-43991465-6b5f-4c83-a45f-dcafe7bd195c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832207379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.1832207379
Directory	/workspace/31.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.2693411582
Short name	T336
Test name
Test status
Simulation time	67118812 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198512 kb
Host	smart-c18c6bf6-2a53-4a72-892e-13e6c30bf432
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693411582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis able_rom_integrity_check.2693411582
Directory	/workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2700382105
Short name	T44
Test name
Test status
Simulation time	47416892 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	197396 kb
Host	smart-964013df-6021-482d-97dd-3e2973d422c0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700382105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst _malfunc.2700382105
Directory	/workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/31.pwrmgr_escalation_timeout.4196875133
Short name	T178
Test name
Test status
Simulation time	2501480130 ps
CPU time	0.91 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	197564 kb
Host	smart-cb9883cc-b6b4-49c3-b6fc-04dbcd2d7322
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196875133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.4196875133
Directory	/workspace/31.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/31.pwrmgr_glitch.4094439070
Short name	T829
Test name
Test status
Simulation time	25414525 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	197492 kb
Host	smart-0f781385-269e-40ad-b87a-c4dc8f06befe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094439070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.4094439070
Directory	/workspace/31.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/31.pwrmgr_global_esc.4103434099
Short name	T289
Test name
Test status
Simulation time	38341983 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:52 PM PDT 24
Peak memory	197444 kb
Host	smart-8200894b-282b-4426-9278-33e2fd8b08f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103434099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.4103434099
Directory	/workspace/31.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/31.pwrmgr_lowpower_invalid.1724642319
Short name	T879
Test name
Test status
Simulation time	48106084 ps
CPU time	0.69 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	200508 kb
Host	smart-ff59db2d-8c86-45a9-be29-202bfc23b60e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724642319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval id.1724642319
Directory	/workspace/31.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.2050966748
Short name	T78
Test name
Test status
Simulation time	321506813 ps
CPU time	0.96 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198848 kb
Host	smart-559efe30-4dc4-42d8-95fb-d51535a8552b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050966748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w akeup_race.2050966748
Directory	/workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/31.pwrmgr_reset.2829009855
Short name	T526
Test name
Test status
Simulation time	61589142 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:38 PM PDT 24
Finished	Mar 17 01:45:39 PM PDT 24
Peak memory	198528 kb
Host	smart-e2862477-09eb-4422-a31f-946b2e3ee387
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829009855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.2829009855
Directory	/workspace/31.pwrmgr_reset/latest

Test location	/workspace/coverage/default/31.pwrmgr_reset_invalid.1842667444
Short name	T247
Test name
Test status
Simulation time	202581930 ps
CPU time	0.81 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	208840 kb
Host	smart-cb394b60-1d35-4e99-8129-8fc7258a12ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842667444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1842667444
Directory	/workspace/31.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1055393852
Short name	T842
Test name
Test status
Simulation time	574333354 ps
CPU time	1.01 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	200276 kb
Host	smart-813a7e54-4695-4eb4-9dfa-3f7963282591
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055393852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_ cm_ctrl_config_regwen.1055393852
Directory	/workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3842375118
Short name	T590
Test name
Test status
Simulation time	904842297 ps
CPU time	2.05 seconds
Started	Mar 17 01:45:26 PM PDT 24
Finished	Mar 17 01:45:29 PM PDT 24
Peak memory	200536 kb
Host	smart-e32e560d-36d7-4416-a98d-f9fee8946a80
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842375118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3842375118
Directory	/workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1921724223
Short name	T595
Test name
Test status
Simulation time	880564108 ps
CPU time	2.42 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	200504 kb
Host	smart-afe0af18-d911-49f1-9194-2cd736bca8ba
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921724223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1921724223
Directory	/workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.129690234
Short name	T294
Test name
Test status
Simulation time	69732763 ps
CPU time	1 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	198768 kb
Host	smart-52e82340-6441-4ad2-ab77-820cf3cebf84
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129690234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_ mubi.129690234
Directory	/workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/31.pwrmgr_smoke.499282507
Short name	T400
Test name
Test status
Simulation time	28213470 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:27 PM PDT 24
Finished	Mar 17 01:45:27 PM PDT 24
Peak memory	198008 kb
Host	smart-6635efcc-e541-4e20-bc88-0b4b1603743b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499282507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.499282507
Directory	/workspace/31.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/31.pwrmgr_wakeup_reset.935490349
Short name	T613
Test name
Test status
Simulation time	347116079 ps
CPU time	1.25 seconds
Started	Mar 17 01:45:27 PM PDT 24
Finished	Mar 17 01:45:28 PM PDT 24
Peak memory	200496 kb
Host	smart-82340404-d51e-4875-b17f-206952e6ae06
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935490349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.935490349
Directory	/workspace/31.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/32.pwrmgr_aborted_low_power.1205462173
Short name	T301
Test name
Test status
Simulation time	18706009 ps
CPU time	0.64 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:40 PM PDT 24
Peak memory	197908 kb
Host	smart-804b96d7-c02e-4500-8ed5-9c9ded3201a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205462173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1205462173
Directory	/workspace/32.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.2667419071
Short name	T432
Test name
Test status
Simulation time	62000497 ps
CPU time	0.88 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	198476 kb
Host	smart-999a8097-afcb-4005-acc1-717b43817ff9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667419071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis able_rom_integrity_check.2667419071
Directory	/workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2622992266
Short name	T600
Test name
Test status
Simulation time	37828462 ps
CPU time	0.59 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	197396 kb
Host	smart-c9fd02b1-2787-406a-a36b-bfe721fcf318
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622992266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst _malfunc.2622992266
Directory	/workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/32.pwrmgr_escalation_timeout.66034438
Short name	T602
Test name
Test status
Simulation time	628230801 ps
CPU time	0.95 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	197428 kb
Host	smart-427e62af-0fbf-42c0-ab15-102f28697253
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66034438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.66034438
Directory	/workspace/32.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/32.pwrmgr_glitch.1911159816
Short name	T251
Test name
Test status
Simulation time	43399004 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	197424 kb
Host	smart-7eaac82b-a0c8-46c4-8e76-f679a1af1d2f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911159816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.1911159816
Directory	/workspace/32.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/32.pwrmgr_global_esc.1759374047
Short name	T291
Test name
Test status
Simulation time	64108113 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	197504 kb
Host	smart-802319d2-025c-4867-abd6-0d1bd66e8c33
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759374047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1759374047
Directory	/workspace/32.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/32.pwrmgr_lowpower_invalid.2214704680
Short name	T349
Test name
Test status
Simulation time	46330099 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	200732 kb
Host	smart-5ece1346-0352-4b1f-80ef-6ed14357c00e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214704680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval id.2214704680
Directory	/workspace/32.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.981546505
Short name	T407
Test name
Test status
Simulation time	492957249 ps
CPU time	1 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	199160 kb
Host	smart-5008f951-357e-4b8a-93b8-3207240be8f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981546505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wa keup_race.981546505
Directory	/workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/32.pwrmgr_reset.150849527
Short name	T724
Test name
Test status
Simulation time	32901135 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	198544 kb
Host	smart-0a6aae72-2f87-4840-ac5e-d072e05900bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150849527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.150849527
Directory	/workspace/32.pwrmgr_reset/latest

Test location	/workspace/coverage/default/32.pwrmgr_reset_invalid.1758337357
Short name	T338
Test name
Test status
Simulation time	103353822 ps
CPU time	0.99 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	208904 kb
Host	smart-6c03b692-cca8-430d-820d-1e777f42cc99
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758337357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1758337357
Directory	/workspace/32.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2460932961
Short name	T703
Test name
Test status
Simulation time	870811176 ps
CPU time	3.19 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	200412 kb
Host	smart-4d9576af-8e31-4cf8-9da6-970ac01e376d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460932961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2460932961
Directory	/workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3248532854
Short name	T872
Test name
Test status
Simulation time	960861622 ps
CPU time	2.82 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	200552 kb
Host	smart-fc293fec-f7c3-4524-987f-17d61ccd0023
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248532854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3248532854
Directory	/workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.1641821902
Short name	T582
Test name
Test status
Simulation time	52827659 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	199008 kb
Host	smart-17e900f6-094a-42b4-a042-fe54e86ffdb9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641821902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig _mubi.1641821902
Directory	/workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/32.pwrmgr_smoke.3692807567
Short name	T347
Test name
Test status
Simulation time	36688945 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:46 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198740 kb
Host	smart-f96826a1-673f-4b6f-b525-9d6dcf1dcb8d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692807567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3692807567
Directory	/workspace/32.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/32.pwrmgr_wakeup_reset.2119687250
Short name	T423
Test name
Test status
Simulation time	323821239 ps
CPU time	1.19 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	200576 kb
Host	smart-0038597f-37b0-48c1-95e4-f021d7dc0830
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119687250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.2119687250
Directory	/workspace/32.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/33.pwrmgr_aborted_low_power.3128263465
Short name	T162
Test name
Test status
Simulation time	56732322 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	198008 kb
Host	smart-53186f4d-28b4-4238-88ea-b5a2e093d717
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128263465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.3128263465
Directory	/workspace/33.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3406028235
Short name	T323
Test name
Test status
Simulation time	73648651 ps
CPU time	0.79 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198484 kb
Host	smart-c454e0c8-ce62-4bf4-a4e8-eff89626e313
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406028235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis able_rom_integrity_check.3406028235
Directory	/workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2596195707
Short name	T308
Test name
Test status
Simulation time	28497779 ps
CPU time	0.64 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	197492 kb
Host	smart-0c47b95e-f171-431e-b966-aaa9e995e536
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596195707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst _malfunc.2596195707
Directory	/workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/33.pwrmgr_escalation_timeout.2600928571
Short name	T555
Test name
Test status
Simulation time	604270300 ps
CPU time	1.05 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	197524 kb
Host	smart-f5e9da8b-99f2-4393-b5ad-67ed48150bf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600928571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2600928571
Directory	/workspace/33.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/33.pwrmgr_glitch.3143690645
Short name	T558
Test name
Test status
Simulation time	48161060 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	196936 kb
Host	smart-74f5c098-f07c-4301-b969-cee3762946b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143690645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3143690645
Directory	/workspace/33.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/33.pwrmgr_global_esc.2954014342
Short name	T835
Test name
Test status
Simulation time	32012327 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	197744 kb
Host	smart-3cbbf893-9ae1-4092-958c-5517cdaf6655
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954014342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2954014342
Directory	/workspace/33.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/33.pwrmgr_lowpower_invalid.443877254
Short name	T90
Test name
Test status
Simulation time	69536882 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:41 PM PDT 24
Finished	Mar 17 01:45:42 PM PDT 24
Peak memory	200692 kb
Host	smart-c0f42044-5bd5-4775-9d44-ff6f7da42fa5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443877254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invali d.443877254
Directory	/workspace/33.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.1448987925
Short name	T263
Test name
Test status
Simulation time	357879770 ps
CPU time	0.93 seconds
Started	Mar 17 01:45:41 PM PDT 24
Finished	Mar 17 01:45:42 PM PDT 24
Peak memory	198956 kb
Host	smart-cd823f57-b64d-437a-9fc7-4a52ae9655bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448987925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_w akeup_race.1448987925
Directory	/workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/33.pwrmgr_reset.816265739
Short name	T631
Test name
Test status
Simulation time	73025245 ps
CPU time	0.96 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	199336 kb
Host	smart-b480379e-f052-4029-bc62-f84de3c8a7b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816265739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.816265739
Directory	/workspace/33.pwrmgr_reset/latest

Test location	/workspace/coverage/default/33.pwrmgr_reset_invalid.1897696093
Short name	T250
Test name
Test status
Simulation time	113423285 ps
CPU time	0.9 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	208836 kb
Host	smart-26b6ffb8-8ab0-4739-adf9-6134d7cbbfea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897696093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1897696093
Directory	/workspace/33.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.2066602658
Short name	T10
Test name
Test status
Simulation time	200740937 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	197976 kb
Host	smart-4d087e6f-97c1-4b31-bd06-603e57cb378d
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066602658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_ cm_ctrl_config_regwen.2066602658
Directory	/workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.499013121
Short name	T26
Test name
Test status
Simulation time	1018026112 ps
CPU time	2.02 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	200560 kb
Host	smart-07b7b529-7fc0-4a65-b958-32404be66ff6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499013121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.499013121
Directory	/workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4106040285
Short name	T628
Test name
Test status
Simulation time	1320452862 ps
CPU time	2.39 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	200540 kb
Host	smart-ccdf387e-2bf6-4648-b5c1-5c2f8c174112
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106040285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4106040285
Directory	/workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.998233454
Short name	T146
Test name
Test status
Simulation time	51440749 ps
CPU time	0.87 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	198616 kb
Host	smart-735ba52c-e8cb-452b-9c7c-14ea3c2c1f63
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998233454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_ mubi.998233454
Directory	/workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/33.pwrmgr_smoke.3140293186
Short name	T694
Test name
Test status
Simulation time	66797724 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:38 PM PDT 24
Finished	Mar 17 01:45:39 PM PDT 24
Peak memory	197812 kb
Host	smart-45b6f513-57d8-49c7-af84-ff29f2254fe4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140293186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3140293186
Directory	/workspace/33.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/33.pwrmgr_wakeup_reset.912758075
Short name	T313
Test name
Test status
Simulation time	303275447 ps
CPU time	1.49 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	200408 kb
Host	smart-69846f44-5d5a-4230-a90e-68d6fc5b2551
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912758075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.912758075
Directory	/workspace/33.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/34.pwrmgr_aborted_low_power.2511466490
Short name	T562
Test name
Test status
Simulation time	28287647 ps
CPU time	0.73 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	197956 kb
Host	smart-9dd602e9-3915-4e20-b252-6572b5a893a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511466490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2511466490
Directory	/workspace/34.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3425772789
Short name	T871
Test name
Test status
Simulation time	45621731 ps
CPU time	0.75 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	197944 kb
Host	smart-a89a3b88-ccd8-4434-985e-a759eadfa656
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425772789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis able_rom_integrity_check.3425772789
Directory	/workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1248580509
Short name	T608
Test name
Test status
Simulation time	48705797 ps
CPU time	0.58 seconds
Started	Mar 17 01:45:46 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	196708 kb
Host	smart-f8e097dc-b57b-4e17-9e7c-a345a866f1ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248580509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst _malfunc.1248580509
Directory	/workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/34.pwrmgr_escalation_timeout.3111557841
Short name	T812
Test name
Test status
Simulation time	562727746 ps
CPU time	0.95 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	197632 kb
Host	smart-cbfc3359-d8b5-410a-aed3-fbffb53efe52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111557841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3111557841
Directory	/workspace/34.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/34.pwrmgr_glitch.987124492
Short name	T18
Test name
Test status
Simulation time	43413567 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	197452 kb
Host	smart-e45b9369-ebdc-4ae6-a7e1-c94af3d1774e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987124492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.987124492
Directory	/workspace/34.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/34.pwrmgr_global_esc.2895693780
Short name	T743
Test name
Test status
Simulation time	71550992 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	197456 kb
Host	smart-76aeca45-6892-46b5-a9f4-45320473395f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895693780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.2895693780
Directory	/workspace/34.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/34.pwrmgr_lowpower_invalid.2681793800
Short name	T589
Test name
Test status
Simulation time	45814111 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:36 PM PDT 24
Finished	Mar 17 01:45:37 PM PDT 24
Peak memory	200700 kb
Host	smart-f3b5fabf-9c4f-4dfe-8adc-2bad0d15020d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681793800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval id.2681793800
Directory	/workspace/34.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/34.pwrmgr_reset.2938157826
Short name	T208
Test name
Test status
Simulation time	72898619 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	198444 kb
Host	smart-438e16ae-fcf9-43ee-ba45-172d940a207a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938157826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.2938157826
Directory	/workspace/34.pwrmgr_reset/latest

Test location	/workspace/coverage/default/34.pwrmgr_reset_invalid.2940422107
Short name	T28
Test name
Test status
Simulation time	100893912 ps
CPU time	0.92 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	208956 kb
Host	smart-7b5ff4fb-6f74-4fd6-8813-7debe3e83b5a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940422107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2940422107
Directory	/workspace/34.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.828518415
Short name	T713
Test name
Test status
Simulation time	333673785 ps
CPU time	1.05 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	200316 kb
Host	smart-5d5949ee-787c-4bd2-a04b-a23074f09613
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828518415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_c m_ctrl_config_regwen.828518415
Directory	/workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1311842069
Short name	T314
Test name
Test status
Simulation time	1153628343 ps
CPU time	2.3 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	200608 kb
Host	smart-8fb8ad92-77be-4cd9-b21a-b334194810de
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311842069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1311842069
Directory	/workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3611470908
Short name	T801
Test name
Test status
Simulation time	745692580 ps
CPU time	3.1 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	200596 kb
Host	smart-869ee25e-08e6-450a-940b-01b02cd732e9
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611470908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3611470908
Directory	/workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2840405985
Short name	T378
Test name
Test status
Simulation time	168739211 ps
CPU time	0.89 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	198716 kb
Host	smart-9564742c-ddf4-46dd-8b2a-88c2893bd3ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840405985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig _mubi.2840405985
Directory	/workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/34.pwrmgr_smoke.3742739536
Short name	T506
Test name
Test status
Simulation time	30498053 ps
CPU time	0.72 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	198660 kb
Host	smart-9dcf1414-5b98-418a-8f8d-598fcad5b433
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742739536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3742739536
Directory	/workspace/34.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/34.pwrmgr_stress_all.2416347006
Short name	T334
Test name
Test status
Simulation time	368591252 ps
CPU time	1.8 seconds
Started	Mar 17 01:45:58 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	200672 kb
Host	smart-c8d2b64b-b9b5-4eb1-8bc5-ce17a0984818
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416347006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.2416347006
Directory	/workspace/34.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/34.pwrmgr_wakeup.3309145043
Short name	T85
Test name
Test status
Simulation time	127195861 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	197872 kb
Host	smart-c1450c2d-a01f-4b45-9e89-de3a87957e6f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309145043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.3309145043
Directory	/workspace/34.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/34.pwrmgr_wakeup_reset.1448016818
Short name	T211
Test name
Test status
Simulation time	366744017 ps
CPU time	0.91 seconds
Started	Mar 17 01:45:46 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	199536 kb
Host	smart-e3c81559-3ede-4236-9e23-23f42896555d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448016818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1448016818
Directory	/workspace/34.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/35.pwrmgr_aborted_low_power.3007490633
Short name	T174
Test name
Test status
Simulation time	48441531 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198076 kb
Host	smart-c8156735-9ea1-4201-a620-f07526ef2791
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007490633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3007490633
Directory	/workspace/35.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.228527322
Short name	T510
Test name
Test status
Simulation time	60729005 ps
CPU time	0.84 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	198544 kb
Host	smart-125b4f29-7e16-4be0-8326-db426cdf7012
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228527322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa ble_rom_integrity_check.228527322
Directory	/workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1907520112
Short name	T747
Test name
Test status
Simulation time	32272782 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	197444 kb
Host	smart-bf664828-4cb0-4cce-9bd7-da2695910c5a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907520112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst _malfunc.1907520112
Directory	/workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/35.pwrmgr_escalation_timeout.578187725
Short name	T541
Test name
Test status
Simulation time	643707220 ps
CPU time	0.99 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	197448 kb
Host	smart-8cda4b0c-316d-4e97-80a2-cd9693e380fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578187725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.578187725
Directory	/workspace/35.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/35.pwrmgr_glitch.825147751
Short name	T670
Test name
Test status
Simulation time	44643307 ps
CPU time	0.65 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	197488 kb
Host	smart-1c76fe07-0c26-462e-a265-395d8e4b845f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825147751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.825147751
Directory	/workspace/35.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/35.pwrmgr_global_esc.3847827021
Short name	T683
Test name
Test status
Simulation time	44249021 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:52 PM PDT 24
Peak memory	197536 kb
Host	smart-d8c618e1-dd2a-4923-9fef-757e4d710838
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847827021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3847827021
Directory	/workspace/35.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/35.pwrmgr_lowpower_invalid.94437569
Short name	T382
Test name
Test status
Simulation time	44026286 ps
CPU time	0.7 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	200724 kb
Host	smart-27b66023-b8bf-4ff0-89cf-650a97ca03a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94437569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid .94437569
Directory	/workspace/35.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.3402206235
Short name	T544
Test name
Test status
Simulation time	50897530 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	198616 kb
Host	smart-05fac22a-f25b-4a20-8c7f-1751e3c2c544
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402206235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w akeup_race.3402206235
Directory	/workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/35.pwrmgr_reset.2920953235
Short name	T232
Test name
Test status
Simulation time	65736528 ps
CPU time	0.84 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	198492 kb
Host	smart-5375cf83-8511-4b8d-860d-6b933d58a33a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920953235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.2920953235
Directory	/workspace/35.pwrmgr_reset/latest

Test location	/workspace/coverage/default/35.pwrmgr_reset_invalid.892965347
Short name	T474
Test name
Test status
Simulation time	144640068 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:52 PM PDT 24
Peak memory	200688 kb
Host	smart-b6f959a7-228c-4ab0-ad92-18ac5f2492d1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892965347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.892965347
Directory	/workspace/35.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.3309012700
Short name	T259
Test name
Test status
Simulation time	345756262 ps
CPU time	1.01 seconds
Started	Mar 17 01:45:39 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	199320 kb
Host	smart-b7044cc7-c3d3-418b-ad0f-a11daa39a9de
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309012700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_ cm_ctrl_config_regwen.3309012700
Directory	/workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.154040488
Short name	T568
Test name
Test status
Simulation time	1137330406 ps
CPU time	2.31 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	200784 kb
Host	smart-ffb40446-aee4-4f08-909a-10cc75dd8bec
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154040488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.154040488
Directory	/workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.837331122
Short name	T828
Test name
Test status
Simulation time	1354428503 ps
CPU time	2.37 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	200680 kb
Host	smart-868f3d94-efea-4862-9533-9fb5cd01311f
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837331122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.837331122
Directory	/workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2445273851
Short name	T383
Test name
Test status
Simulation time	65464711 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:39 PM PDT 24
Finished	Mar 17 01:45:40 PM PDT 24
Peak memory	198748 kb
Host	smart-5645e8db-be6b-46d8-b6de-5b25d6dc962a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445273851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig _mubi.2445273851
Directory	/workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/35.pwrmgr_smoke.1398174961
Short name	T851
Test name
Test status
Simulation time	29728115 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	198748 kb
Host	smart-32631649-3e9b-443f-bf48-2bfa76c06316
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398174961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1398174961
Directory	/workspace/35.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/35.pwrmgr_stress_all.4179511034
Short name	T120
Test name
Test status
Simulation time	241963122 ps
CPU time	1.52 seconds
Started	Mar 17 01:45:39 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	200496 kb
Host	smart-831521f6-d7a0-4861-924a-62d77364b18a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179511034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.4179511034
Directory	/workspace/35.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/35.pwrmgr_wakeup.2520211468
Short name	T143
Test name
Test status
Simulation time	182815654 ps
CPU time	1.13 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	199104 kb
Host	smart-75cf7bcb-6b7d-43d4-8438-a985f0577029
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520211468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.2520211468
Directory	/workspace/35.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/35.pwrmgr_wakeup_reset.2457099103
Short name	T587
Test name
Test status
Simulation time	279760822 ps
CPU time	1.17 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	199752 kb
Host	smart-445a9d99-8183-402d-a9c6-a22e8b9212c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457099103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2457099103
Directory	/workspace/35.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/36.pwrmgr_aborted_low_power.491953428
Short name	T886
Test name
Test status
Simulation time	64488027 ps
CPU time	0.82 seconds
Started	Mar 17 01:45:58 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	199256 kb
Host	smart-97524deb-febb-4cf7-a862-c278e5013347
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491953428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.491953428
Directory	/workspace/36.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.1705097378
Short name	T409
Test name
Test status
Simulation time	88496038 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	198620 kb
Host	smart-62a89711-df10-44b9-87ad-228489fff6ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705097378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis able_rom_integrity_check.1705097378
Directory	/workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.548891896
Short name	T704
Test name
Test status
Simulation time	58635205 ps
CPU time	0.58 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	196676 kb
Host	smart-86c87b96-8327-46e0-9c76-650f8a960408
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548891896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_ malfunc.548891896
Directory	/workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/36.pwrmgr_escalation_timeout.2026575322
Short name	T867
Test name
Test status
Simulation time	165830724 ps
CPU time	1 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	197820 kb
Host	smart-3c6eb298-0057-4dbb-bb84-6763a03adb7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2026575322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.2026575322
Directory	/workspace/36.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/36.pwrmgr_glitch.873490822
Short name	T616
Test name
Test status
Simulation time	47165043 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	196852 kb
Host	smart-e053d771-fa12-4d74-825e-729fba09ce2c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873490822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.873490822
Directory	/workspace/36.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/36.pwrmgr_global_esc.159545723
Short name	T411
Test name
Test status
Simulation time	40490996 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	197860 kb
Host	smart-330e590b-27ca-4711-b044-26e55cf7afec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159545723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.159545723
Directory	/workspace/36.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/36.pwrmgr_lowpower_invalid.4096640079
Short name	T676
Test name
Test status
Simulation time	43088893 ps
CPU time	0.73 seconds
Started	Mar 17 01:45:58 PM PDT 24
Finished	Mar 17 01:45:59 PM PDT 24
Peak memory	200788 kb
Host	smart-8eaf06e4-63d1-4c12-9427-23b5bf35d5e7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096640079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval id.4096640079
Directory	/workspace/36.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.3587708194
Short name	T657
Test name
Test status
Simulation time	176998720 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:46 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	198504 kb
Host	smart-eeccb7d6-e4a6-4b85-80f4-c2aafc82b11e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587708194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w akeup_race.3587708194
Directory	/workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/36.pwrmgr_reset.718616222
Short name	T209
Test name
Test status
Simulation time	91894004 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	198596 kb
Host	smart-d923de52-dc17-411b-84ea-09d7dc64d087
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718616222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.718616222
Directory	/workspace/36.pwrmgr_reset/latest

Test location	/workspace/coverage/default/36.pwrmgr_reset_invalid.2637270069
Short name	T818
Test name
Test status
Simulation time	104524367 ps
CPU time	0.89 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	208920 kb
Host	smart-05d95a87-9402-4044-a9d7-c9e3fdc17534
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637270069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.2637270069
Directory	/workspace/36.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.1999621664
Short name	T40
Test name
Test status
Simulation time	206780882 ps
CPU time	1.04 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	200196 kb
Host	smart-840cf4b2-d413-46cf-8c3c-bda13bc295fc
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999621664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_ cm_ctrl_config_regwen.1999621664
Directory	/workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1364712328
Short name	T819
Test name
Test status
Simulation time	811063958 ps
CPU time	2.79 seconds
Started	Mar 17 01:45:46 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	200568 kb
Host	smart-b641aeab-08ef-407b-a817-bf8c09140f68
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364712328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1364712328
Directory	/workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1793656352
Short name	T179
Test name
Test status
Simulation time	1365834878 ps
CPU time	2.25 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	200584 kb
Host	smart-0115369c-42d2-4b8f-9a5d-055d8e681030
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793656352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1793656352
Directory	/workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3003581329
Short name	T522
Test name
Test status
Simulation time	71825527 ps
CPU time	0.9 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	198512 kb
Host	smart-c57a0019-38ab-4985-b06f-d58bc2827297
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003581329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig _mubi.3003581329
Directory	/workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/36.pwrmgr_smoke.3316424917
Short name	T213
Test name
Test status
Simulation time	28349173 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	198744 kb
Host	smart-4cdc1704-6831-4c48-b760-5d0a9726f7c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316424917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3316424917
Directory	/workspace/36.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/36.pwrmgr_wakeup.1235743330
Short name	T249
Test name
Test status
Simulation time	99628086 ps
CPU time	0.83 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	197760 kb
Host	smart-c8d07463-a027-432d-88ad-ca88e163b4c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235743330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.1235743330
Directory	/workspace/36.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/36.pwrmgr_wakeup_reset.346677426
Short name	T252
Test name
Test status
Simulation time	175423742 ps
CPU time	0.91 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	198708 kb
Host	smart-af9efe05-e43e-42b3-b44b-de2c14714bd9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346677426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.346677426
Directory	/workspace/36.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/37.pwrmgr_aborted_low_power.2840239144
Short name	T667
Test name
Test status
Simulation time	68185396 ps
CPU time	0.7 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	198036 kb
Host	smart-e96a3174-44e7-44ae-9fb8-714b05e39099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840239144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2840239144
Directory	/workspace/37.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.1534441082
Short name	T387
Test name
Test status
Simulation time	129153690 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:41 PM PDT 24
Finished	Mar 17 01:45:42 PM PDT 24
Peak memory	198080 kb
Host	smart-755ebf82-89e0-4099-b17d-2e79b4564c93
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534441082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis able_rom_integrity_check.1534441082
Directory	/workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.3410596671
Short name	T764
Test name
Test status
Simulation time	31911680 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	197436 kb
Host	smart-fcc75ba8-bc5a-4de0-9216-a56807835388
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410596671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst _malfunc.3410596671
Directory	/workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/37.pwrmgr_escalation_timeout.3303509581
Short name	T875
Test name
Test status
Simulation time	162775164 ps
CPU time	0.99 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	197508 kb
Host	smart-e76df288-36ec-4cb9-bcce-b4871dced652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303509581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.3303509581
Directory	/workspace/37.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/37.pwrmgr_glitch.990081507
Short name	T329
Test name
Test status
Simulation time	71034593 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	197472 kb
Host	smart-bb7d5b2a-e08c-473b-8def-5fb25a537ef7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990081507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.990081507
Directory	/workspace/37.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/37.pwrmgr_global_esc.1367216456
Short name	T655
Test name
Test status
Simulation time	40067502 ps
CPU time	0.58 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	197468 kb
Host	smart-daeea67a-1f72-4e03-b6a0-33592bf0ceaa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367216456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1367216456
Directory	/workspace/37.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/37.pwrmgr_lowpower_invalid.1282250258
Short name	T442
Test name
Test status
Simulation time	72726518 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	200676 kb
Host	smart-542df6eb-32f4-4360-984f-a66345f849da
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282250258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval id.1282250258
Directory	/workspace/37.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.1623488156
Short name	T445
Test name
Test status
Simulation time	315864756 ps
CPU time	0.98 seconds
Started	Mar 17 01:45:55 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	199108 kb
Host	smart-7e31b810-a940-4799-9550-f72c448e727e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623488156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w akeup_race.1623488156
Directory	/workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/37.pwrmgr_reset.3578316385
Short name	T525
Test name
Test status
Simulation time	295680020 ps
CPU time	0.86 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	199288 kb
Host	smart-4af740a3-d1d7-4170-8404-aee7d2c058d2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578316385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3578316385
Directory	/workspace/37.pwrmgr_reset/latest

Test location	/workspace/coverage/default/37.pwrmgr_reset_invalid.475257567
Short name	T172
Test name
Test status
Simulation time	178200519 ps
CPU time	0.8 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	200676 kb
Host	smart-d69a3594-6a25-4730-9344-f96e9cc1d45d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475257567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.475257567
Directory	/workspace/37.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1593800855
Short name	T862
Test name
Test status
Simulation time	1474988551 ps
CPU time	2.07 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	200444 kb
Host	smart-26a48ee7-5c5c-462b-b1be-92a621f9074a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593800855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1593800855
Directory	/workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3630490732
Short name	T188
Test name
Test status
Simulation time	812497679 ps
CPU time	2.84 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	200620 kb
Host	smart-6f9bef9a-018d-4775-a8a4-70a8063da68e
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630490732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3630490732
Directory	/workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2280050711
Short name	T214
Test name
Test status
Simulation time	70333292 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198772 kb
Host	smart-7c44a95f-a7b3-456d-8f91-2b5e50400e0d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280050711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig _mubi.2280050711
Directory	/workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/37.pwrmgr_smoke.748924667
Short name	T854
Test name
Test status
Simulation time	74981454 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:40 PM PDT 24
Finished	Mar 17 01:45:41 PM PDT 24
Peak memory	198700 kb
Host	smart-3392f12f-4c92-4cde-8ba6-4c6218250879
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748924667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.748924667
Directory	/workspace/37.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/37.pwrmgr_wakeup.3803492603
Short name	T469
Test name
Test status
Simulation time	232175902 ps
CPU time	0.82 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	197980 kb
Host	smart-9ca11efc-3c19-4312-9f39-d4f586371b87
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803492603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.3803492603
Directory	/workspace/37.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/37.pwrmgr_wakeup_reset.3859347497
Short name	T736
Test name
Test status
Simulation time	395168758 ps
CPU time	0.82 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:52 PM PDT 24
Peak memory	199504 kb
Host	smart-842d396f-d8d2-42a4-83d8-84d2fcc192c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859347497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.3859347497
Directory	/workspace/37.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/38.pwrmgr_aborted_low_power.2187315552
Short name	T666
Test name
Test status
Simulation time	25520660 ps
CPU time	0.72 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	198020 kb
Host	smart-1807b7c8-749e-43d2-ad28-d83f76d5b87c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187315552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2187315552
Directory	/workspace/38.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.458230790
Short name	T680
Test name
Test status
Simulation time	63928943 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	198560 kb
Host	smart-73ce77de-7491-4641-84d7-10cc92e367ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458230790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disa ble_rom_integrity_check.458230790
Directory	/workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2364231645
Short name	T365
Test name
Test status
Simulation time	43001764 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	196656 kb
Host	smart-b01afe6a-ecbc-41e0-b4c4-c3686150e8bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364231645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst _malfunc.2364231645
Directory	/workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/38.pwrmgr_escalation_timeout.1805284612
Short name	T369
Test name
Test status
Simulation time	641137989 ps
CPU time	0.95 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	197488 kb
Host	smart-a33fee78-c347-487f-b2eb-3ed3bd588fee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805284612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1805284612
Directory	/workspace/38.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/38.pwrmgr_glitch.2425815469
Short name	T897
Test name
Test status
Simulation time	49931667 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	197456 kb
Host	smart-85c1e18d-ef9a-4ace-8432-a9316183d483
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425815469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2425815469
Directory	/workspace/38.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/38.pwrmgr_global_esc.819956394
Short name	T322
Test name
Test status
Simulation time	30187946 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	197392 kb
Host	smart-949700fd-b53a-4ac0-a7b1-ad7e5d28a852
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819956394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.819956394
Directory	/workspace/38.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/38.pwrmgr_lowpower_invalid.29016875
Short name	T358
Test name
Test status
Simulation time	44008957 ps
CPU time	0.69 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	200700 kb
Host	smart-2998cc95-dab6-49c9-bd98-4108f5235aa2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29016875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid .29016875
Directory	/workspace/38.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.2593972596
Short name	T823
Test name
Test status
Simulation time	201875450 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	197920 kb
Host	smart-b3b43d94-5900-4728-a7ca-b4ae438f366a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593972596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w akeup_race.2593972596
Directory	/workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/38.pwrmgr_reset.107587291
Short name	T521
Test name
Test status
Simulation time	103393647 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	198480 kb
Host	smart-6dc7d113-65cd-4080-bbd0-93fde137bc18
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107587291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.107587291
Directory	/workspace/38.pwrmgr_reset/latest

Test location	/workspace/coverage/default/38.pwrmgr_reset_invalid.1316802787
Short name	T556
Test name
Test status
Simulation time	118375951 ps
CPU time	0.92 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	208756 kb
Host	smart-74c6a2cb-2da4-478f-af94-802574c5f42a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316802787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1316802787
Directory	/workspace/38.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2220631288
Short name	T386
Test name
Test status
Simulation time	314788750 ps
CPU time	1.05 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	199268 kb
Host	smart-00004209-7482-44aa-b307-8711c8b3c78d
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220631288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_ cm_ctrl_config_regwen.2220631288
Directory	/workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2315227620
Short name	T855
Test name
Test status
Simulation time	1030105244 ps
CPU time	2.34 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	200532 kb
Host	smart-2d881647-5397-4379-a76f-07cf19af907a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315227620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2315227620
Directory	/workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2397144245
Short name	T762
Test name
Test status
Simulation time	908920589 ps
CPU time	3.01 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	200588 kb
Host	smart-8cd12e0e-1733-474e-98f5-2280ad67f9d9
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397144245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2397144245
Directory	/workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3040508064
Short name	T565
Test name
Test status
Simulation time	51676727 ps
CPU time	0.88 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	198536 kb
Host	smart-eb902acf-23d5-4d40-aa21-3ab089e0d21a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040508064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig _mubi.3040508064
Directory	/workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/38.pwrmgr_smoke.4217154248
Short name	T91
Test name
Test status
Simulation time	49541728 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	198684 kb
Host	smart-8c64fb2b-bd17-4270-b641-bcbe1d8c411e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217154248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.4217154248
Directory	/workspace/38.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/38.pwrmgr_wakeup_reset.3989205120
Short name	T534
Test name
Test status
Simulation time	202232525 ps
CPU time	0.8 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	199096 kb
Host	smart-c06ac4e0-390a-4bc9-ac71-9e03ac06c751
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989205120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.3989205120
Directory	/workspace/38.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/39.pwrmgr_aborted_low_power.719314292
Short name	T580
Test name
Test status
Simulation time	20361268 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	197864 kb
Host	smart-a424848d-643b-4ada-8478-87dea9189bb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719314292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.719314292
Directory	/workspace/39.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.1250173916
Short name	T309
Test name
Test status
Simulation time	69241814 ps
CPU time	0.78 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	198416 kb
Host	smart-0fc6e1bb-cf72-4f70-9c68-4871886ca2b5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250173916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis able_rom_integrity_check.1250173916
Directory	/workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.947168939
Short name	T569
Test name
Test status
Simulation time	85545727 ps
CPU time	0.56 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	197348 kb
Host	smart-42a9f258-ccaf-4f26-a99b-70edec9c6c79
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947168939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_ malfunc.947168939
Directory	/workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/39.pwrmgr_escalation_timeout.2997421709
Short name	T340
Test name
Test status
Simulation time	353880375 ps
CPU time	1 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	197540 kb
Host	smart-cd0545eb-04fd-4cf9-8570-9b5b552c7561
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997421709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2997421709
Directory	/workspace/39.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/39.pwrmgr_glitch.748837407
Short name	T281
Test name
Test status
Simulation time	25195023 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	197416 kb
Host	smart-78f76d61-d5d7-4b72-a062-dea43b305b8a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748837407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.748837407
Directory	/workspace/39.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/39.pwrmgr_global_esc.1255212567
Short name	T786
Test name
Test status
Simulation time	51452168 ps
CPU time	0.61 seconds
Started	Mar 17 01:46:00 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	197544 kb
Host	smart-af44d514-c70c-46d2-9b46-e89447f8993f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255212567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1255212567
Directory	/workspace/39.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/39.pwrmgr_lowpower_invalid.2937150298
Short name	T748
Test name
Test status
Simulation time	43445276 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	200772 kb
Host	smart-0d281dfe-6041-48c3-9095-c9fa4e8fcc91
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937150298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval id.2937150298
Directory	/workspace/39.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.1726015308
Short name	T825
Test name
Test status
Simulation time	149486176 ps
CPU time	0.76 seconds
Started	Mar 17 01:45:55 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	197792 kb
Host	smart-81074928-7a56-4380-a3fd-b8c37dcd39c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726015308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w akeup_race.1726015308
Directory	/workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/39.pwrmgr_reset.1831785961
Short name	T192
Test name
Test status
Simulation time	38743483 ps
CPU time	0.64 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	197928 kb
Host	smart-11fd3c07-13cf-4425-b342-489a0e5dfdf9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831785961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1831785961
Directory	/workspace/39.pwrmgr_reset/latest

Test location	/workspace/coverage/default/39.pwrmgr_reset_invalid.2791663076
Short name	T152
Test name
Test status
Simulation time	149078840 ps
CPU time	0.88 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	208920 kb
Host	smart-0decbb68-cd83-4279-a513-32beb52ae33f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791663076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2791663076
Directory	/workspace/39.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1789101014
Short name	T599
Test name
Test status
Simulation time	944486577 ps
CPU time	2 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	200664 kb
Host	smart-0175835b-7359-4175-84c5-1896442dc733
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789101014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1789101014
Directory	/workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3029035966
Short name	T722
Test name
Test status
Simulation time	907955413 ps
CPU time	3.22 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:48 PM PDT 24
Peak memory	200632 kb
Host	smart-4ec5d372-5eaa-4927-a150-7dc3b96487a3
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029035966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3029035966
Directory	/workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2889192932
Short name	T566
Test name
Test status
Simulation time	67006430 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	198992 kb
Host	smart-ba8ad147-2e7c-4c86-901b-2aae8616e078
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889192932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig _mubi.2889192932
Directory	/workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/39.pwrmgr_smoke.572931411
Short name	T802
Test name
Test status
Simulation time	52941961 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	197748 kb
Host	smart-4c215ba2-2164-408e-b76f-bb1fc796876f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572931411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.572931411
Directory	/workspace/39.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/39.pwrmgr_wakeup_reset.2182661248
Short name	T443
Test name
Test status
Simulation time	116721522 ps
CPU time	1.01 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	198440 kb
Host	smart-4aa3057a-2102-40fc-b21e-cbbdf2ef6c75
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182661248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.2182661248
Directory	/workspace/39.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/4.pwrmgr_aborted_low_power.168241059
Short name	T36
Test name
Test status
Simulation time	119866594 ps
CPU time	0.83 seconds
Started	Mar 17 01:44:17 PM PDT 24
Finished	Mar 17 01:44:17 PM PDT 24
Peak memory	199136 kb
Host	smart-3f2b7c51-981c-495b-86f6-7124ebc1c2be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168241059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.168241059
Directory	/workspace/4.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.2468412548
Short name	T359
Test name
Test status
Simulation time	92402439 ps
CPU time	0.74 seconds
Started	Mar 17 01:44:15 PM PDT 24
Finished	Mar 17 01:44:16 PM PDT 24
Peak memory	198116 kb
Host	smart-ad37e6a0-57cd-40a3-a477-c15e1adb48ff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468412548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa ble_rom_integrity_check.2468412548
Directory	/workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1992327282
Short name	T895
Test name
Test status
Simulation time	33676463 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:17 PM PDT 24
Finished	Mar 17 01:44:17 PM PDT 24
Peak memory	196672 kb
Host	smart-26d78eb2-9e01-465f-84b9-9aedb29279d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992327282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_ malfunc.1992327282
Directory	/workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/4.pwrmgr_escalation_timeout.199246344
Short name	T742
Test name
Test status
Simulation time	167091074 ps
CPU time	1.01 seconds
Started	Mar 17 01:44:15 PM PDT 24
Finished	Mar 17 01:44:17 PM PDT 24
Peak memory	197836 kb
Host	smart-4c8f294d-8b63-477c-87fb-bb09cf7edf4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199246344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.199246344
Directory	/workspace/4.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/4.pwrmgr_glitch.178866927
Short name	T187
Test name
Test status
Simulation time	80350316 ps
CPU time	0.59 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	197432 kb
Host	smart-95e1053a-e819-4c15-bf38-e827e7cc13c8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178866927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.178866927
Directory	/workspace/4.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/4.pwrmgr_global_esc.3751108840
Short name	T611
Test name
Test status
Simulation time	66656348 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:15 PM PDT 24
Finished	Mar 17 01:44:16 PM PDT 24
Peak memory	197448 kb
Host	smart-cb2faaa8-d3c2-44b9-908d-82723d69ca1c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751108840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.3751108840
Directory	/workspace/4.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/4.pwrmgr_lowpower_invalid.1712596358
Short name	T584
Test name
Test status
Simulation time	41339518 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:14 PM PDT 24
Finished	Mar 17 01:44:15 PM PDT 24
Peak memory	200784 kb
Host	smart-96a5cb04-a20d-457e-8b58-f188f1d72abf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712596358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali d.1712596358
Directory	/workspace/4.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.3360509909
Short name	T891
Test name
Test status
Simulation time	291457039 ps
CPU time	1.05 seconds
Started	Mar 17 01:44:09 PM PDT 24
Finished	Mar 17 01:44:10 PM PDT 24
Peak memory	199152 kb
Host	smart-e15f5750-05e0-4106-8985-0ea1e89eb317
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360509909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa keup_race.3360509909
Directory	/workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/4.pwrmgr_reset.3423801475
Short name	T817
Test name
Test status
Simulation time	45446325 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	198528 kb
Host	smart-2506089e-8273-4f18-a1de-32746007fc96
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423801475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3423801475
Directory	/workspace/4.pwrmgr_reset/latest

Test location	/workspace/coverage/default/4.pwrmgr_sec_cm.3401418406
Short name	T31
Test name
Test status
Simulation time	476843124 ps
CPU time	1.14 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:14 PM PDT 24
Peak memory	216452 kb
Host	smart-84407385-2d56-4f16-897a-b345f21c40f3
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401418406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3401418406
Directory	/workspace/4.pwrmgr_sec_cm/latest

Test location	/workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1985427416
Short name	T604
Test name
Test status
Simulation time	439856700 ps
CPU time	1.12 seconds
Started	Mar 17 01:44:17 PM PDT 24
Finished	Mar 17 01:44:18 PM PDT 24
Peak memory	200228 kb
Host	smart-011ff655-227b-423e-9fd7-abbd20ba9a2a
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985427416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c m_ctrl_config_regwen.1985427416
Directory	/workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3339013201
Short name	T627
Test name
Test status
Simulation time	856433986 ps
CPU time	2.42 seconds
Started	Mar 17 01:44:15 PM PDT 24
Finished	Mar 17 01:44:18 PM PDT 24
Peak memory	200524 kb
Host	smart-aa2c9634-f691-47e8-941d-fae2bef88a3b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339013201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3339013201
Directory	/workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.868985815
Short name	T826
Test name
Test status
Simulation time	841541189 ps
CPU time	2.99 seconds
Started	Mar 17 01:44:12 PM PDT 24
Finished	Mar 17 01:44:15 PM PDT 24
Peak memory	200604 kb
Host	smart-a1f2e222-a317-4001-b56e-8cd1a7e9e9a0
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868985815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.868985815
Directory	/workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.4023111098
Short name	T419
Test name
Test status
Simulation time	73447351 ps
CPU time	0.96 seconds
Started	Mar 17 01:44:18 PM PDT 24
Finished	Mar 17 01:44:19 PM PDT 24
Peak memory	198952 kb
Host	smart-8549cf23-44db-4791-8958-8259955cc129
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023111098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_ mubi.4023111098
Directory	/workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/4.pwrmgr_smoke.1162539415
Short name	T240
Test name
Test status
Simulation time	41924860 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:16 PM PDT 24
Finished	Mar 17 01:44:17 PM PDT 24
Peak memory	198624 kb
Host	smart-8f1311cd-397b-4d15-bcdb-14e20970e91d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162539415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1162539415
Directory	/workspace/4.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/4.pwrmgr_stress_all.777821597
Short name	T48
Test name
Test status
Simulation time	2119536665 ps
CPU time	3.21 seconds
Started	Mar 17 01:44:14 PM PDT 24
Finished	Mar 17 01:44:17 PM PDT 24
Peak memory	200668 kb
Host	smart-10a36db9-a6ee-4703-bf43-b5f823c55dd7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777821597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.777821597
Directory	/workspace/4.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/4.pwrmgr_wakeup.3673603015
Short name	T266
Test name
Test status
Simulation time	61974574 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	197840 kb
Host	smart-48bdb43e-f4e3-4a88-989d-9475e829aed5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673603015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.3673603015
Directory	/workspace/4.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/4.pwrmgr_wakeup_reset.2527484918
Short name	T758
Test name
Test status
Simulation time	374251195 ps
CPU time	1.28 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	200604 kb
Host	smart-f4b81a31-774b-4b50-890d-d44879c2ebb8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527484918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.2527484918
Directory	/workspace/4.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/40.pwrmgr_aborted_low_power.2910124361
Short name	T576
Test name
Test status
Simulation time	19861699 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	197924 kb
Host	smart-d2f81621-ec83-466e-b04d-b389896940bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910124361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2910124361
Directory	/workspace/40.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2095762274
Short name	T319
Test name
Test status
Simulation time	77186927 ps
CPU time	0.76 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	198552 kb
Host	smart-59952fcc-02a7-4e65-926c-bc1d389e4aa1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095762274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis able_rom_integrity_check.2095762274
Directory	/workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.406966147
Short name	T782
Test name
Test status
Simulation time	36737293 ps
CPU time	0.58 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	197380 kb
Host	smart-a7ee200f-4bde-4087-9394-329adf49d0ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406966147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_ malfunc.406966147
Directory	/workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/40.pwrmgr_escalation_timeout.1362944278
Short name	T206
Test name
Test status
Simulation time	259755436 ps
CPU time	1 seconds
Started	Mar 17 01:45:59 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	197756 kb
Host	smart-da7ca0fb-af78-427a-935f-503f1002cef4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362944278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.1362944278
Directory	/workspace/40.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/40.pwrmgr_glitch.980077561
Short name	T354
Test name
Test status
Simulation time	60285695 ps
CPU time	0.58 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	197548 kb
Host	smart-faee8060-33e1-496e-a4dd-0fe26b496a6e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980077561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.980077561
Directory	/workspace/40.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/40.pwrmgr_global_esc.1297527338
Short name	T262
Test name
Test status
Simulation time	38190913 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	197824 kb
Host	smart-a7085a95-a854-4d86-a8ce-207e33903a1c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297527338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1297527338
Directory	/workspace/40.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/40.pwrmgr_lowpower_invalid.3201965260
Short name	T207
Test name
Test status
Simulation time	47358342 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:42 PM PDT 24
Finished	Mar 17 01:45:43 PM PDT 24
Peak memory	200780 kb
Host	smart-10f17c68-fa1d-41d8-9d27-1046cdca60b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201965260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval id.3201965260
Directory	/workspace/40.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.2472694654
Short name	T333
Test name
Test status
Simulation time	138834181 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:52 PM PDT 24
Peak memory	198480 kb
Host	smart-a0bca6a0-d6a8-4cad-a857-28cfbe051bc5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472694654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w akeup_race.2472694654
Directory	/workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/40.pwrmgr_reset.4216149726
Short name	T344
Test name
Test status
Simulation time	81347403 ps
CPU time	1.02 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	199372 kb
Host	smart-b99cd31b-97a3-472e-8500-f87135453280
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216149726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.4216149726
Directory	/workspace/40.pwrmgr_reset/latest

Test location	/workspace/coverage/default/40.pwrmgr_reset_invalid.2067463579
Short name	T227
Test name
Test status
Simulation time	220343118 ps
CPU time	0.8 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	208864 kb
Host	smart-e3d1b76a-60e5-42ef-a638-b0f2975130d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067463579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2067463579
Directory	/workspace/40.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.4191918776
Short name	T882
Test name
Test status
Simulation time	290844708 ps
CPU time	0.9 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	199356 kb
Host	smart-08bac2c9-f8cc-4f84-8dd1-b7b322e7df36
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191918776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_ cm_ctrl_config_regwen.4191918776
Directory	/workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3256102433
Short name	T684
Test name
Test status
Simulation time	901632935 ps
CPU time	2.05 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:59 PM PDT 24
Peak memory	200608 kb
Host	smart-b69c28ba-2caf-48d4-a6d4-a448aabb675b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256102433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3256102433
Directory	/workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1705487606
Short name	T877
Test name
Test status
Simulation time	911280254 ps
CPU time	3.19 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	200544 kb
Host	smart-95bc8716-7176-4dc0-a602-0dfc1ada774c
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705487606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1705487606
Directory	/workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.415224181
Short name	T788
Test name
Test status
Simulation time	103998106 ps
CPU time	0.93 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	198684 kb
Host	smart-e267b942-ee91-4338-9799-2e96fe570767
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415224181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_ mubi.415224181
Directory	/workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/40.pwrmgr_smoke.2916996596
Short name	T847
Test name
Test status
Simulation time	31532157 ps
CPU time	0.7 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	198668 kb
Host	smart-5cf85777-a7be-4302-b8cc-2b8d841d83c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916996596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2916996596
Directory	/workspace/40.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/40.pwrmgr_stress_all.3425024206
Short name	T840
Test name
Test status
Simulation time	130633590 ps
CPU time	0.92 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:52 PM PDT 24
Peak memory	199452 kb
Host	smart-8dcdfe45-b8c1-4033-b36d-44ae97dd6330
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425024206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.3425024206
Directory	/workspace/40.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/40.pwrmgr_wakeup_reset.122385003
Short name	T745
Test name
Test status
Simulation time	392616294 ps
CPU time	1.18 seconds
Started	Mar 17 01:45:44 PM PDT 24
Finished	Mar 17 01:45:45 PM PDT 24
Peak memory	200612 kb
Host	smart-876e764c-7de2-4d96-be67-29b86624fec2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122385003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.122385003
Directory	/workspace/40.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/41.pwrmgr_aborted_low_power.3568237161
Short name	T280
Test name
Test status
Simulation time	20714459 ps
CPU time	0.72 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	197836 kb
Host	smart-0f298f93-1bf7-4388-be93-cd90b23fdb00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568237161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.3568237161
Directory	/workspace/41.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.4265482949
Short name	T127
Test name
Test status
Simulation time	74876527 ps
CPU time	0.92 seconds
Started	Mar 17 01:45:41 PM PDT 24
Finished	Mar 17 01:45:42 PM PDT 24
Peak memory	199208 kb
Host	smart-cf6c1282-1246-4253-b12e-58316c467c13
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265482949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis able_rom_integrity_check.4265482949
Directory	/workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2549239623
Short name	T362
Test name
Test status
Simulation time	107807429 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:59 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	197372 kb
Host	smart-faa05b56-5a07-4c31-be77-bc6bb2090058
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549239623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst _malfunc.2549239623
Directory	/workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/41.pwrmgr_escalation_timeout.609140367
Short name	T586
Test name
Test status
Simulation time	319446300 ps
CPU time	0.96 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	197512 kb
Host	smart-685c8270-7011-4de5-bdee-fa449ab4519a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609140367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.609140367
Directory	/workspace/41.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/41.pwrmgr_glitch.83076283
Short name	T856
Test name
Test status
Simulation time	103306893 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	197572 kb
Host	smart-24158571-553b-4643-a112-f7d284c4ecfb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83076283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.83076283
Directory	/workspace/41.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/41.pwrmgr_global_esc.1217608184
Short name	T239
Test name
Test status
Simulation time	49357264 ps
CPU time	0.62 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	197740 kb
Host	smart-28fc6bad-ed02-4077-86d8-36a89f0af708
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217608184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1217608184
Directory	/workspace/41.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/41.pwrmgr_lowpower_invalid.1758924361
Short name	T656
Test name
Test status
Simulation time	45038140 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	200700 kb
Host	smart-8221f990-6f6c-4b10-bf3b-d6cf4a49f899
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758924361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval id.1758924361
Directory	/workspace/41.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/41.pwrmgr_reset.2278464562
Short name	T575
Test name
Test status
Simulation time	38956557 ps
CPU time	0.78 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	198552 kb
Host	smart-958aaaa4-2072-48d0-9f1e-dab002b919fd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278464562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2278464562
Directory	/workspace/41.pwrmgr_reset/latest

Test location	/workspace/coverage/default/41.pwrmgr_reset_invalid.488998721
Short name	T38
Test name
Test status
Simulation time	141209469 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:45 PM PDT 24
Finished	Mar 17 01:45:46 PM PDT 24
Peak memory	208888 kb
Host	smart-af7d48f5-f8dd-4580-8e49-d34c5ea07ee7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488998721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.488998721
Directory	/workspace/41.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2809189280
Short name	T164
Test name
Test status
Simulation time	93521937 ps
CPU time	0.88 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	198764 kb
Host	smart-4a69b8f6-8342-4308-b4e8-2a720c0605a3
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809189280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_ cm_ctrl_config_regwen.2809189280
Directory	/workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1384468748
Short name	T518
Test name
Test status
Simulation time	846789001 ps
CPU time	2.1 seconds
Started	Mar 17 01:45:59 PM PDT 24
Finished	Mar 17 01:46:02 PM PDT 24
Peak memory	200396 kb
Host	smart-37a1e52f-eaa4-4f58-bf22-f6e38ad573f3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384468748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1384468748
Directory	/workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2683280016
Short name	T244
Test name
Test status
Simulation time	836252729 ps
CPU time	3.22 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	200604 kb
Host	smart-bd2f5de1-96f4-4fb7-abe4-ea2d6b276661
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683280016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2683280016
Directory	/workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2294731282
Short name	T860
Test name
Test status
Simulation time	82916626 ps
CPU time	0.97 seconds
Started	Mar 17 01:45:43 PM PDT 24
Finished	Mar 17 01:45:44 PM PDT 24
Peak memory	198816 kb
Host	smart-97a817e6-b55d-43a9-a1ad-dea852733420
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294731282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig _mubi.2294731282
Directory	/workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/41.pwrmgr_smoke.1642042669
Short name	T360
Test name
Test status
Simulation time	41677159 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	197840 kb
Host	smart-b5a34259-2252-4c3e-97cd-5045b4d2a7bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642042669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.1642042669
Directory	/workspace/41.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/41.pwrmgr_wakeup.3626435960
Short name	T233
Test name
Test status
Simulation time	141534911 ps
CPU time	0.77 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	197684 kb
Host	smart-81b18a46-bf64-4936-ba8a-3f6b2ff5ef19
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626435960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.3626435960
Directory	/workspace/41.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/41.pwrmgr_wakeup_reset.52174443
Short name	T866
Test name
Test status
Simulation time	69468057 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	198660 kb
Host	smart-6e16f229-7637-4d33-a3d9-86bd0df8cedc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52174443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.52174443
Directory	/workspace/41.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/42.pwrmgr_aborted_low_power.3715558743
Short name	T253
Test name
Test status
Simulation time	23426854 ps
CPU time	0.69 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	197888 kb
Host	smart-ca488e10-7ceb-4943-be80-8825da1dd4c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715558743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3715558743
Directory	/workspace/42.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.1450760384
Short name	T527
Test name
Test status
Simulation time	55898625 ps
CPU time	0.78 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	198616 kb
Host	smart-ca6f831c-d538-4bf0-8e24-4ea8f22a9ed7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450760384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis able_rom_integrity_check.1450760384
Directory	/workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.828844838
Short name	T287
Test name
Test status
Simulation time	32724064 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	196740 kb
Host	smart-433697ad-ff03-4058-b8b0-f4b95ce7e602
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828844838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_ malfunc.828844838
Directory	/workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/42.pwrmgr_escalation_timeout.3882699588
Short name	T554
Test name
Test status
Simulation time	323156178 ps
CPU time	0.97 seconds
Started	Mar 17 01:45:58 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	197472 kb
Host	smart-e5208dec-3c89-40f8-b51a-ddfbd71db2ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882699588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3882699588
Directory	/workspace/42.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/42.pwrmgr_glitch.3240549476
Short name	T806
Test name
Test status
Simulation time	89119437 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	197416 kb
Host	smart-b993c3da-a565-405b-ace3-f2bef98581ba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240549476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.3240549476
Directory	/workspace/42.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/42.pwrmgr_global_esc.3495789129
Short name	T508
Test name
Test status
Simulation time	26106832 ps
CPU time	0.63 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	197492 kb
Host	smart-96c543e4-03dc-4d05-9d72-0c75addec2a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495789129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3495789129
Directory	/workspace/42.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/42.pwrmgr_lowpower_invalid.869121692
Short name	T404
Test name
Test status
Simulation time	120271927 ps
CPU time	0.66 seconds
Started	Mar 17 01:46:05 PM PDT 24
Finished	Mar 17 01:46:06 PM PDT 24
Peak memory	200760 kb
Host	smart-6be89cae-f8d8-4cc6-8808-a9cf060950e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869121692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invali d.869121692
Directory	/workspace/42.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.1060440
Short name	T710
Test name
Test status
Simulation time	264359962 ps
CPU time	0.68 seconds
Started	Mar 17 01:46:02 PM PDT 24
Finished	Mar 17 01:46:03 PM PDT 24
Peak memory	197704 kb
Host	smart-be27f15e-3235-45e6-a916-469667cb51d2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_ race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wake up_race.1060440
Directory	/workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/42.pwrmgr_reset.2844473258
Short name	T797
Test name
Test status
Simulation time	32349201 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:48 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	198588 kb
Host	smart-996af30f-aae9-48f1-9bb9-6bb5ab33d1fd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844473258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2844473258
Directory	/workspace/42.pwrmgr_reset/latest

Test location	/workspace/coverage/default/42.pwrmgr_reset_invalid.3291356890
Short name	T815
Test name
Test status
Simulation time	104748104 ps
CPU time	1 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:50 PM PDT 24
Peak memory	208892 kb
Host	smart-e7dff10e-4f61-4e60-8ab2-6a28d4b4a9a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291356890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3291356890
Directory	/workspace/42.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.3462813770
Short name	T236
Test name
Test status
Simulation time	169523579 ps
CPU time	0.84 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	199192 kb
Host	smart-fc45809b-e54c-4401-823a-e8daacc5881d
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462813770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_ cm_ctrl_config_regwen.3462813770
Directory	/workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2198143605
Short name	T671
Test name
Test status
Simulation time	830380214 ps
CPU time	3.42 seconds
Started	Mar 17 01:46:01 PM PDT 24
Finished	Mar 17 01:46:05 PM PDT 24
Peak memory	200604 kb
Host	smart-a471bdd1-81cd-449a-ba01-1036526be564
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198143605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2198143605
Directory	/workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.991508121
Short name	T477
Test name
Test status
Simulation time	902621373 ps
CPU time	3.26 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	200620 kb
Host	smart-9fb407f8-0e42-479d-8f44-76c77c77af99
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991508121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.991508121
Directory	/workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1683936400
Short name	T186
Test name
Test status
Simulation time	54770250 ps
CPU time	0.88 seconds
Started	Mar 17 01:46:04 PM PDT 24
Finished	Mar 17 01:46:05 PM PDT 24
Peak memory	198648 kb
Host	smart-f3e3e22b-f2dc-42f8-a2b7-c661388ec35b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683936400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig _mubi.1683936400
Directory	/workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/42.pwrmgr_smoke.4212793190
Short name	T274
Test name
Test status
Simulation time	36050815 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:59 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	197800 kb
Host	smart-8da206c7-4149-49f4-a19d-f3ef935febf0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212793190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.4212793190
Directory	/workspace/42.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/42.pwrmgr_stress_all.316384850
Short name	T215
Test name
Test status
Simulation time	3377021982 ps
CPU time	3.28 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:46:01 PM PDT 24
Peak memory	200724 kb
Host	smart-00debde1-2e4a-4819-99f0-0298cb519f0c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316384850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.316384850
Directory	/workspace/42.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/42.pwrmgr_wakeup.2024133478
Short name	T429
Test name
Test status
Simulation time	292225462 ps
CPU time	1.08 seconds
Started	Mar 17 01:45:59 PM PDT 24
Finished	Mar 17 01:46:01 PM PDT 24
Peak memory	199208 kb
Host	smart-35300ea3-8a72-4ca2-aa65-3745c1796f19
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024133478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2024133478
Directory	/workspace/42.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/42.pwrmgr_wakeup_reset.3055702811
Short name	T416
Test name
Test status
Simulation time	359310363 ps
CPU time	1.19 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	200440 kb
Host	smart-69ce8ac2-169d-43be-98c1-e295ea750caf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055702811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.3055702811
Directory	/workspace/42.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/43.pwrmgr_aborted_low_power.2447416613
Short name	T447
Test name
Test status
Simulation time	51095690 ps
CPU time	0.62 seconds
Started	Mar 17 01:46:03 PM PDT 24
Finished	Mar 17 01:46:04 PM PDT 24
Peak memory	197872 kb
Host	smart-79f31788-1c56-4415-b209-a64217faedc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447416613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2447416613
Directory	/workspace/43.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.2095931811
Short name	T325
Test name
Test status
Simulation time	65309722 ps
CPU time	0.77 seconds
Started	Mar 17 01:46:02 PM PDT 24
Finished	Mar 17 01:46:03 PM PDT 24
Peak memory	198084 kb
Host	smart-96fc7782-aa56-416b-8a65-4dd6358781b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095931811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis able_rom_integrity_check.2095931811
Directory	/workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1059764657
Short name	T156
Test name
Test status
Simulation time	28174114 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:52 PM PDT 24
Peak memory	197376 kb
Host	smart-d1f02965-e594-4202-a435-96b424cb762b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059764657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst _malfunc.1059764657
Directory	/workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/43.pwrmgr_escalation_timeout.1207294903
Short name	T757
Test name
Test status
Simulation time	325024283 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	197556 kb
Host	smart-e3735a79-c43d-47e6-bd52-253d3cd37710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207294903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.1207294903
Directory	/workspace/43.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/43.pwrmgr_glitch.3157870131
Short name	T361
Test name
Test status
Simulation time	37356779 ps
CPU time	0.67 seconds
Started	Mar 17 01:45:47 PM PDT 24
Finished	Mar 17 01:45:47 PM PDT 24
Peak memory	197516 kb
Host	smart-9c0ffa4f-8e15-40cf-b817-ecd53064f373
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157870131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.3157870131
Directory	/workspace/43.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/43.pwrmgr_global_esc.1295817334
Short name	T413
Test name
Test status
Simulation time	321815972 ps
CPU time	0.58 seconds
Started	Mar 17 01:46:00 PM PDT 24
Finished	Mar 17 01:46:01 PM PDT 24
Peak memory	197480 kb
Host	smart-c85d980c-4a61-45bb-80da-713bb9350455
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295817334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.1295817334
Directory	/workspace/43.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/43.pwrmgr_lowpower_invalid.2313340681
Short name	T766
Test name
Test status
Simulation time	42006231 ps
CPU time	0.73 seconds
Started	Mar 17 01:46:00 PM PDT 24
Finished	Mar 17 01:46:01 PM PDT 24
Peak memory	200704 kb
Host	smart-e3f00ba7-65ea-4a08-9fae-d715d99fdf23
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313340681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval id.2313340681
Directory	/workspace/43.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.2422189393
Short name	T749
Test name
Test status
Simulation time	179898012 ps
CPU time	0.8 seconds
Started	Mar 17 01:46:05 PM PDT 24
Finished	Mar 17 01:46:06 PM PDT 24
Peak memory	197708 kb
Host	smart-ccce8903-aefc-48da-8fde-6d027ab62bb3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422189393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w akeup_race.2422189393
Directory	/workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/43.pwrmgr_reset.932415507
Short name	T528
Test name
Test status
Simulation time	138673697 ps
CPU time	0.81 seconds
Started	Mar 17 01:46:02 PM PDT 24
Finished	Mar 17 01:46:03 PM PDT 24
Peak memory	197960 kb
Host	smart-0989de4d-f33e-4a9d-b127-158674ba39d6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932415507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.932415507
Directory	/workspace/43.pwrmgr_reset/latest

Test location	/workspace/coverage/default/43.pwrmgr_reset_invalid.1429026595
Short name	T837
Test name
Test status
Simulation time	160355034 ps
CPU time	0.85 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	208964 kb
Host	smart-8944fdfb-0e3e-46c4-9740-49c60f1171fe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429026595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1429026595
Directory	/workspace/43.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1215145491
Short name	T651
Test name
Test status
Simulation time	59043442 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:59 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	197920 kb
Host	smart-c81da879-13ed-4707-b146-e6ba750c189d
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215145491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_ cm_ctrl_config_regwen.1215145491
Directory	/workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.40012680
Short name	T654
Test name
Test status
Simulation time	857428835 ps
CPU time	3.31 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	200500 kb
Host	smart-255878a0-82de-4f09-8337-9359d637cb15
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40012680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test + UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.40012680
Directory	/workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1916511656
Short name	T434
Test name
Test status
Simulation time	1057470220 ps
CPU time	2.86 seconds
Started	Mar 17 01:45:52 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	200528 kb
Host	smart-1a034317-eb89-4161-9df2-f384bd6b92c0
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916511656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1916511656
Directory	/workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2467211113
Short name	T190
Test name
Test status
Simulation time	103394782 ps
CPU time	0.9 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	198784 kb
Host	smart-10ce3c37-e1af-49e2-ba24-e5341ef79126
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467211113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig _mubi.2467211113
Directory	/workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/43.pwrmgr_smoke.3767973089
Short name	T689
Test name
Test status
Simulation time	31956066 ps
CPU time	0.69 seconds
Started	Mar 17 01:46:05 PM PDT 24
Finished	Mar 17 01:46:06 PM PDT 24
Peak memory	198692 kb
Host	smart-c43ad296-a0dd-42fe-8041-dc8aa91acff7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767973089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3767973089
Directory	/workspace/43.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/43.pwrmgr_wakeup.2859312370
Short name	T800
Test name
Test status
Simulation time	59735049 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:49 PM PDT 24
Finished	Mar 17 01:45:49 PM PDT 24
Peak memory	198460 kb
Host	smart-a6e78135-5258-46db-a454-6c326c5aece3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859312370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.2859312370
Directory	/workspace/43.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/43.pwrmgr_wakeup_reset.4228704391
Short name	T746
Test name
Test status
Simulation time	334237913 ps
CPU time	1.01 seconds
Started	Mar 17 01:45:51 PM PDT 24
Finished	Mar 17 01:45:53 PM PDT 24
Peak memory	199368 kb
Host	smart-c2d4c529-1bfb-4ac6-bdac-fd21baf5da1a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228704391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.4228704391
Directory	/workspace/43.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/44.pwrmgr_aborted_low_power.1302552718
Short name	T733
Test name
Test status
Simulation time	54910190 ps
CPU time	0.74 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	198264 kb
Host	smart-d34db711-dd17-4cf4-8e4f-4342e46cffe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302552718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1302552718
Directory	/workspace/44.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.115384852
Short name	T711
Test name
Test status
Simulation time	67484110 ps
CPU time	0.9 seconds
Started	Mar 17 01:46:02 PM PDT 24
Finished	Mar 17 01:46:03 PM PDT 24
Peak memory	198512 kb
Host	smart-34c8b0fa-d65d-4f48-9d8f-9c9f17571da7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115384852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disa ble_rom_integrity_check.115384852
Directory	/workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2764012297
Short name	T424
Test name
Test status
Simulation time	27725874 ps
CPU time	0.63 seconds
Started	Mar 17 01:46:06 PM PDT 24
Finished	Mar 17 01:46:07 PM PDT 24
Peak memory	197460 kb
Host	smart-a844de6a-a6fe-4533-96cc-dd6eff32eb94
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764012297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst _malfunc.2764012297
Directory	/workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/44.pwrmgr_escalation_timeout.569763694
Short name	T184
Test name
Test status
Simulation time	338997246 ps
CPU time	0.99 seconds
Started	Mar 17 01:46:00 PM PDT 24
Finished	Mar 17 01:46:01 PM PDT 24
Peak memory	197548 kb
Host	smart-7fd33b48-38ff-4d13-bbcc-226ed2fe9cbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569763694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.569763694
Directory	/workspace/44.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/44.pwrmgr_glitch.2708327519
Short name	T1
Test name
Test status
Simulation time	87057911 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:55 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	197576 kb
Host	smart-b5ff813e-1142-43d9-b391-cd8277c56ef6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708327519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2708327519
Directory	/workspace/44.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/44.pwrmgr_global_esc.2362303162
Short name	T159
Test name
Test status
Simulation time	61241641 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:53 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	197440 kb
Host	smart-a96f199a-5a94-417e-80c4-4b28a6d634e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362303162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2362303162
Directory	/workspace/44.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/44.pwrmgr_lowpower_invalid.787936171
Short name	T303
Test name
Test status
Simulation time	39584991 ps
CPU time	0.69 seconds
Started	Mar 17 01:46:03 PM PDT 24
Finished	Mar 17 01:46:04 PM PDT 24
Peak memory	200724 kb
Host	smart-5d5346a1-5361-4253-bfe5-0ab72c6071fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787936171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invali d.787936171
Directory	/workspace/44.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.3603102904
Short name	T643
Test name
Test status
Simulation time	77653635 ps
CPU time	0.73 seconds
Started	Mar 17 01:46:03 PM PDT 24
Finished	Mar 17 01:46:04 PM PDT 24
Peak memory	197656 kb
Host	smart-e459c073-b341-4ba2-aae1-a31f6a9e2438
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603102904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_w akeup_race.3603102904
Directory	/workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/44.pwrmgr_reset.2760964948
Short name	T275
Test name
Test status
Simulation time	76986864 ps
CPU time	0.88 seconds
Started	Mar 17 01:45:50 PM PDT 24
Finished	Mar 17 01:45:51 PM PDT 24
Peak memory	199132 kb
Host	smart-6a7e814f-614c-4aa7-8cab-21a0624cb509
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760964948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2760964948
Directory	/workspace/44.pwrmgr_reset/latest

Test location	/workspace/coverage/default/44.pwrmgr_reset_invalid.2858247422
Short name	T785
Test name
Test status
Simulation time	148086507 ps
CPU time	0.82 seconds
Started	Mar 17 01:45:55 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	200764 kb
Host	smart-c86579b5-ddfc-40d7-a44d-8bbd9349c06b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858247422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.2858247422
Directory	/workspace/44.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.622169133
Short name	T863
Test name
Test status
Simulation time	2230075538 ps
CPU time	1.85 seconds
Started	Mar 17 01:46:02 PM PDT 24
Finished	Mar 17 01:46:04 PM PDT 24
Peak memory	200512 kb
Host	smart-afc02af4-f4e2-444c-b4a5-09dab1112479
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622169133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.622169133
Directory	/workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.864134506
Short name	T175
Test name
Test status
Simulation time	909008112 ps
CPU time	3.15 seconds
Started	Mar 17 01:46:06 PM PDT 24
Finished	Mar 17 01:46:10 PM PDT 24
Peak memory	200604 kb
Host	smart-cad0f0ff-ce54-458b-bb95-c658a3b439d2
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864134506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.864134506
Directory	/workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.549562555
Short name	T176
Test name
Test status
Simulation time	151911069 ps
CPU time	0.82 seconds
Started	Mar 17 01:46:01 PM PDT 24
Finished	Mar 17 01:46:02 PM PDT 24
Peak memory	198936 kb
Host	smart-8f19e5ff-1a37-410c-a847-4e662d909bce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549562555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_ mubi.549562555
Directory	/workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/44.pwrmgr_smoke.3427677753
Short name	T357
Test name
Test status
Simulation time	30112635 ps
CPU time	0.71 seconds
Started	Mar 17 01:46:01 PM PDT 24
Finished	Mar 17 01:46:02 PM PDT 24
Peak memory	198704 kb
Host	smart-b95308c1-95e7-4c4a-8c1e-b97548469ce8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427677753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.3427677753
Directory	/workspace/44.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/44.pwrmgr_wakeup.1657280064
Short name	T830
Test name
Test status
Simulation time	88917914 ps
CPU time	0.67 seconds
Started	Mar 17 01:46:04 PM PDT 24
Finished	Mar 17 01:46:05 PM PDT 24
Peak memory	197624 kb
Host	smart-21bfc863-b23a-4f1e-87b1-9421c531cd59
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657280064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.1657280064
Directory	/workspace/44.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/44.pwrmgr_wakeup_reset.1281556846
Short name	T653
Test name
Test status
Simulation time	151649607 ps
CPU time	1.06 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:45:58 PM PDT 24
Peak memory	199344 kb
Host	smart-6a124fb0-3d4b-49c8-8135-c6a86617085a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281556846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.1281556846
Directory	/workspace/44.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/45.pwrmgr_aborted_low_power.891938635
Short name	T246
Test name
Test status
Simulation time	27666468 ps
CPU time	0.75 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:54 PM PDT 24
Peak memory	198016 kb
Host	smart-3b1696bf-fd7c-4827-bc2f-992b841c1098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891938635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.891938635
Directory	/workspace/45.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.29021254
Short name	T134
Test name
Test status
Simulation time	64507214 ps
CPU time	0.86 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	198424 kb
Host	smart-d1869e57-6825-4c90-ba60-118d0f53c287
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disab le_rom_integrity_check.29021254
Directory	/workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.968658121
Short name	T339
Test name
Test status
Simulation time	38588227 ps
CPU time	0.6 seconds
Started	Mar 17 01:45:55 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	196680 kb
Host	smart-a5cfd476-f5f5-40b7-aaa4-3672f762dbf7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968658121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_ malfunc.968658121
Directory	/workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/45.pwrmgr_escalation_timeout.3138510109
Short name	T449
Test name
Test status
Simulation time	632133072 ps
CPU time	0.94 seconds
Started	Mar 17 01:45:55 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	197556 kb
Host	smart-80732604-a547-4a93-99e7-2eebe75e9c93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138510109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3138510109
Directory	/workspace/45.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/45.pwrmgr_glitch.3051440232
Short name	T149
Test name
Test status
Simulation time	44220335 ps
CPU time	0.61 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:56 PM PDT 24
Peak memory	197500 kb
Host	smart-a04ad7d5-91d6-4e50-872e-5e144c71e62f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051440232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3051440232
Directory	/workspace/45.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/45.pwrmgr_global_esc.1860474213
Short name	T622
Test name
Test status
Simulation time	80075213 ps
CPU time	0.63 seconds
Started	Mar 17 01:46:03 PM PDT 24
Finished	Mar 17 01:46:04 PM PDT 24
Peak memory	197524 kb
Host	smart-a6771977-915d-4eb0-9b8d-80d36160deb9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860474213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1860474213
Directory	/workspace/45.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/45.pwrmgr_lowpower_invalid.4213106914
Short name	T876
Test name
Test status
Simulation time	91231541 ps
CPU time	0.73 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:08 PM PDT 24
Peak memory	200772 kb
Host	smart-0422c9ed-0fa0-4a25-9c42-422577969daf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213106914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval id.4213106914
Directory	/workspace/45.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.3022416000
Short name	T276
Test name
Test status
Simulation time	46616996 ps
CPU time	0.71 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	198452 kb
Host	smart-a47e729c-e9db-4208-89d0-609bf9aa8313
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022416000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w akeup_race.3022416000
Directory	/workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/45.pwrmgr_reset.2580006768
Short name	T352
Test name
Test status
Simulation time	42814596 ps
CPU time	0.66 seconds
Started	Mar 17 01:45:56 PM PDT 24
Finished	Mar 17 01:45:57 PM PDT 24
Peak memory	197656 kb
Host	smart-d2607667-8f77-4654-8f27-fe85996a33f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580006768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2580006768
Directory	/workspace/45.pwrmgr_reset/latest

Test location	/workspace/coverage/default/45.pwrmgr_reset_invalid.4211112753
Short name	T297
Test name
Test status
Simulation time	198289575 ps
CPU time	0.79 seconds
Started	Mar 17 01:46:05 PM PDT 24
Finished	Mar 17 01:46:06 PM PDT 24
Peak memory	208660 kb
Host	smart-acb90e20-5fb0-489b-9fd7-f98dbde49490
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211112753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.4211112753
Directory	/workspace/45.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.356972633
Short name	T813
Test name
Test status
Simulation time	851200249 ps
CPU time	3.12 seconds
Started	Mar 17 01:45:57 PM PDT 24
Finished	Mar 17 01:46:00 PM PDT 24
Peak memory	200592 kb
Host	smart-2e538ac6-97f5-4fce-ba4c-c207e9c57d4f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356972633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.356972633
Directory	/workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2325212940
Short name	T515
Test name
Test status
Simulation time	860915424 ps
CPU time	3.34 seconds
Started	Mar 17 01:46:04 PM PDT 24
Finished	Mar 17 01:46:08 PM PDT 24
Peak memory	200540 kb
Host	smart-6b7647a9-026d-44ff-bd8a-dd5ae6242f15
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325212940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2325212940
Directory	/workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2089954827
Short name	T229
Test name
Test status
Simulation time	74291354 ps
CPU time	0.93 seconds
Started	Mar 17 01:46:02 PM PDT 24
Finished	Mar 17 01:46:03 PM PDT 24
Peak memory	198724 kb
Host	smart-559231a2-00b2-46de-8aef-2d1de5fbbcec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089954827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig _mubi.2089954827
Directory	/workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/45.pwrmgr_smoke.646592577
Short name	T848
Test name
Test status
Simulation time	30085210 ps
CPU time	0.68 seconds
Started	Mar 17 01:45:54 PM PDT 24
Finished	Mar 17 01:45:55 PM PDT 24
Peak memory	198672 kb
Host	smart-c82150ac-54bd-4bd0-a2bb-1db8bccc1088
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646592577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.646592577
Directory	/workspace/45.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/45.pwrmgr_wakeup_reset.1805768611
Short name	T6
Test name
Test status
Simulation time	146486347 ps
CPU time	0.78 seconds
Started	Mar 17 01:46:03 PM PDT 24
Finished	Mar 17 01:46:04 PM PDT 24
Peak memory	198660 kb
Host	smart-bd807332-39ed-46b6-b690-7bc9f63ad7b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805768611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1805768611
Directory	/workspace/45.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/46.pwrmgr_aborted_low_power.3127536950
Short name	T320
Test name
Test status
Simulation time	26121757 ps
CPU time	0.78 seconds
Started	Mar 17 01:46:27 PM PDT 24
Finished	Mar 17 01:46:28 PM PDT 24
Peak memory	197984 kb
Host	smart-64b7dd07-4cee-45df-b3a5-a4f58feb9be3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127536950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.3127536950
Directory	/workspace/46.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.72533285
Short name	T468
Test name
Test status
Simulation time	87807894 ps
CPU time	0.71 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	198548 kb
Host	smart-36b9769c-1c66-4515-97ad-3c3cef775c11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72533285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disab le_rom_integrity_check.72533285
Directory	/workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1675099886
Short name	T315
Test name
Test status
Simulation time	40397658 ps
CPU time	0.59 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:07 PM PDT 24
Peak memory	197408 kb
Host	smart-63662d63-e2d9-4f49-8091-1e19478d17ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675099886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst _malfunc.1675099886
Directory	/workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/46.pwrmgr_escalation_timeout.2711421914
Short name	T283
Test name
Test status
Simulation time	168888177 ps
CPU time	0.97 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:08 PM PDT 24
Peak memory	197776 kb
Host	smart-8f66715d-b552-4579-a98d-3f1a96cd84e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711421914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2711421914
Directory	/workspace/46.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/46.pwrmgr_glitch.2731054276
Short name	T408
Test name
Test status
Simulation time	59501915 ps
CPU time	0.72 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:08 PM PDT 24
Peak memory	197504 kb
Host	smart-f2b6d0c4-fba5-4e0e-bbdb-b1001b429977
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731054276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2731054276
Directory	/workspace/46.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/46.pwrmgr_global_esc.2920570720
Short name	T593
Test name
Test status
Simulation time	76041276 ps
CPU time	0.62 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	197748 kb
Host	smart-31ced0b3-3777-4e13-9eb6-366e5ed2076d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920570720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2920570720
Directory	/workspace/46.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/46.pwrmgr_lowpower_invalid.2414435554
Short name	T282
Test name
Test status
Simulation time	195716037 ps
CPU time	0.71 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:08 PM PDT 24
Peak memory	200772 kb
Host	smart-c02070ab-e2a0-4c88-a27a-f5c99fa2dbd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414435554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval id.2414435554
Directory	/workspace/46.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/46.pwrmgr_reset.3479418752
Short name	T664
Test name
Test status
Simulation time	70795287 ps
CPU time	1.02 seconds
Started	Mar 17 01:46:10 PM PDT 24
Finished	Mar 17 01:46:11 PM PDT 24
Peak memory	199188 kb
Host	smart-d29628ce-d351-4fad-b1b4-201be4a6a4ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479418752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3479418752
Directory	/workspace/46.pwrmgr_reset/latest

Test location	/workspace/coverage/default/46.pwrmgr_reset_invalid.2098648184
Short name	T200
Test name
Test status
Simulation time	124957820 ps
CPU time	0.9 seconds
Started	Mar 17 01:46:10 PM PDT 24
Finished	Mar 17 01:46:12 PM PDT 24
Peak memory	208852 kb
Host	smart-ca82ae3f-0ebd-4ae2-a673-c3fc18deeffe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098648184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2098648184
Directory	/workspace/46.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3824017707
Short name	T268
Test name
Test status
Simulation time	949381873 ps
CPU time	2.21 seconds
Started	Mar 17 01:46:08 PM PDT 24
Finished	Mar 17 01:46:11 PM PDT 24
Peak memory	200492 kb
Host	smart-1dc936f0-99a9-4976-b056-c68ba37e42a2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824017707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3824017707
Directory	/workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3250702909
Short name	T436
Test name
Test status
Simulation time	877388937 ps
CPU time	3.27 seconds
Started	Mar 17 01:46:25 PM PDT 24
Finished	Mar 17 01:46:29 PM PDT 24
Peak memory	200592 kb
Host	smart-0fe253de-2662-46eb-ad4b-5407c052bac1
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250702909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3250702909
Directory	/workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.794283767
Short name	T763
Test name
Test status
Simulation time	102693132 ps
CPU time	0.88 seconds
Started	Mar 17 01:46:14 PM PDT 24
Finished	Mar 17 01:46:15 PM PDT 24
Peak memory	198716 kb
Host	smart-7054af5a-0299-44c3-8911-5acb1733dad9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794283767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_ mubi.794283767
Directory	/workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/46.pwrmgr_smoke.2634990685
Short name	T380
Test name
Test status
Simulation time	33127872 ps
CPU time	0.68 seconds
Started	Mar 17 01:46:06 PM PDT 24
Finished	Mar 17 01:46:07 PM PDT 24
Peak memory	198664 kb
Host	smart-9381b864-5d00-4f65-9953-4ceb308b4118
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634990685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2634990685
Directory	/workspace/46.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/46.pwrmgr_stress_all.1493913515
Short name	T789
Test name
Test status
Simulation time	99240897 ps
CPU time	0.77 seconds
Started	Mar 17 01:46:09 PM PDT 24
Finished	Mar 17 01:46:10 PM PDT 24
Peak memory	199408 kb
Host	smart-97094ddc-374e-4772-9abd-ee9b06792507
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493913515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.1493913515
Directory	/workspace/46.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/46.pwrmgr_wakeup.4224245136
Short name	T471
Test name
Test status
Simulation time	240415905 ps
CPU time	1.16 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:08 PM PDT 24
Peak memory	199232 kb
Host	smart-f75a13bf-ae85-46e4-828b-e6dfe512f2b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224245136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.4224245136
Directory	/workspace/46.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/46.pwrmgr_wakeup_reset.3398050557
Short name	T539
Test name
Test status
Simulation time	235131753 ps
CPU time	1.3 seconds
Started	Mar 17 01:46:11 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	199572 kb
Host	smart-af00964a-c659-490d-86e4-186b2481e7ba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398050557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.3398050557
Directory	/workspace/46.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/47.pwrmgr_aborted_low_power.3828802287
Short name	T702
Test name
Test status
Simulation time	25787658 ps
CPU time	0.7 seconds
Started	Mar 17 01:46:08 PM PDT 24
Finished	Mar 17 01:46:09 PM PDT 24
Peak memory	197864 kb
Host	smart-2a84be72-c87e-4f2b-8aef-88a66379df6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828802287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3828802287
Directory	/workspace/47.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.2633035521
Short name	T821
Test name
Test status
Simulation time	58578194 ps
CPU time	0.86 seconds
Started	Mar 17 01:46:11 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	198508 kb
Host	smart-3cc66b56-eaae-4977-8a0d-1e213f7133f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633035521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis able_rom_integrity_check.2633035521
Directory	/workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1354190898
Short name	T300
Test name
Test status
Simulation time	59760597 ps
CPU time	0.61 seconds
Started	Mar 17 01:46:19 PM PDT 24
Finished	Mar 17 01:46:20 PM PDT 24
Peak memory	197440 kb
Host	smart-b2361774-6734-4db7-96ed-3bf43ea74842
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354190898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst _malfunc.1354190898
Directory	/workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/47.pwrmgr_escalation_timeout.1977098291
Short name	T160
Test name
Test status
Simulation time	166337239 ps
CPU time	0.97 seconds
Started	Mar 17 01:46:34 PM PDT 24
Finished	Mar 17 01:46:35 PM PDT 24
Peak memory	197500 kb
Host	smart-87b4fc42-a5a4-4c31-a57b-a86e2251d796
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977098291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1977098291
Directory	/workspace/47.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/47.pwrmgr_glitch.4184533154
Short name	T691
Test name
Test status
Simulation time	43488974 ps
CPU time	0.65 seconds
Started	Mar 17 01:46:09 PM PDT 24
Finished	Mar 17 01:46:10 PM PDT 24
Peak memory	196828 kb
Host	smart-245df9aa-90f6-411d-be99-87cbbd7191ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184533154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.4184533154
Directory	/workspace/47.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/47.pwrmgr_global_esc.1085985577
Short name	T317
Test name
Test status
Simulation time	34321705 ps
CPU time	0.63 seconds
Started	Mar 17 01:46:11 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	197548 kb
Host	smart-cdd30111-835b-4dce-86c4-76188e33a179
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085985577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.1085985577
Directory	/workspace/47.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.3661514828
Short name	T370
Test name
Test status
Simulation time	126323703 ps
CPU time	0.85 seconds
Started	Mar 17 01:46:01 PM PDT 24
Finished	Mar 17 01:46:01 PM PDT 24
Peak memory	198400 kb
Host	smart-a107171c-3252-4c6f-88f1-55f07fb13bdd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661514828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w akeup_race.3661514828
Directory	/workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/47.pwrmgr_reset.626212220
Short name	T321
Test name
Test status
Simulation time	233577330 ps
CPU time	0.96 seconds
Started	Mar 17 01:46:04 PM PDT 24
Finished	Mar 17 01:46:05 PM PDT 24
Peak memory	199396 kb
Host	smart-9ba63c13-3784-4a7e-840b-a6ee8fc73e03
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626212220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.626212220
Directory	/workspace/47.pwrmgr_reset/latest

Test location	/workspace/coverage/default/47.pwrmgr_reset_invalid.1776617671
Short name	T42
Test name
Test status
Simulation time	106555329 ps
CPU time	0.95 seconds
Started	Mar 17 01:46:13 PM PDT 24
Finished	Mar 17 01:46:14 PM PDT 24
Peak memory	208784 kb
Host	smart-e24ecdd8-d5ed-47b2-97b4-b205073047d1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776617671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1776617671
Directory	/workspace/47.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.978056807
Short name	T218
Test name
Test status
Simulation time	129663819 ps
CPU time	0.94 seconds
Started	Mar 17 01:46:06 PM PDT 24
Finished	Mar 17 01:46:07 PM PDT 24
Peak memory	199092 kb
Host	smart-24a825fe-32fb-483b-a632-964c15919e1f
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978056807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_c m_ctrl_config_regwen.978056807
Directory	/workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.215507484
Short name	T128
Test name
Test status
Simulation time	1294823098 ps
CPU time	2.25 seconds
Started	Mar 17 01:46:25 PM PDT 24
Finished	Mar 17 01:46:28 PM PDT 24
Peak memory	200496 kb
Host	smart-d058f5b0-e811-4940-904c-046605d1b2af
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215507484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.215507484
Directory	/workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2656941219
Short name	T699
Test name
Test status
Simulation time	851127333 ps
CPU time	3.2 seconds
Started	Mar 17 01:46:20 PM PDT 24
Finished	Mar 17 01:46:24 PM PDT 24
Peak memory	200656 kb
Host	smart-1b80420a-b058-41e8-8475-ca50d0d1df51
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656941219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2656941219
Directory	/workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3651957930
Short name	T147
Test name
Test status
Simulation time	57997103 ps
CPU time	0.79 seconds
Started	Mar 17 01:46:22 PM PDT 24
Finished	Mar 17 01:46:23 PM PDT 24
Peak memory	198684 kb
Host	smart-5b48e8fc-6164-491a-b31e-c05e6dfb09de
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651957930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig _mubi.3651957930
Directory	/workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/47.pwrmgr_smoke.1627573787
Short name	T538
Test name
Test status
Simulation time	82475555 ps
CPU time	0.65 seconds
Started	Mar 17 01:46:08 PM PDT 24
Finished	Mar 17 01:46:09 PM PDT 24
Peak memory	197952 kb
Host	smart-152fc4d6-42be-40f3-bb36-c9e001373ebb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627573787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1627573787
Directory	/workspace/47.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/47.pwrmgr_wakeup.730061493
Short name	T444
Test name
Test status
Simulation time	119839667 ps
CPU time	0.71 seconds
Started	Mar 17 01:46:01 PM PDT 24
Finished	Mar 17 01:46:02 PM PDT 24
Peak memory	198416 kb
Host	smart-605f3bc3-5b08-4478-997b-2acc72e607f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730061493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.730061493
Directory	/workspace/47.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/47.pwrmgr_wakeup_reset.1063307144
Short name	T205
Test name
Test status
Simulation time	56557063 ps
CPU time	0.67 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:08 PM PDT 24
Peak memory	198540 kb
Host	smart-efcde94c-e610-4fbc-a7df-8f62a313ce28
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063307144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.1063307144
Directory	/workspace/47.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/48.pwrmgr_aborted_low_power.277800912
Short name	T581
Test name
Test status
Simulation time	53919507 ps
CPU time	0.75 seconds
Started	Mar 17 01:46:13 PM PDT 24
Finished	Mar 17 01:46:14 PM PDT 24
Peak memory	198040 kb
Host	smart-645a3125-1ed4-427f-864e-6c43100b0072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277800912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.277800912
Directory	/workspace/48.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.2994849452
Short name	T769
Test name
Test status
Simulation time	61405821 ps
CPU time	0.72 seconds
Started	Mar 17 01:46:16 PM PDT 24
Finished	Mar 17 01:46:17 PM PDT 24
Peak memory	198548 kb
Host	smart-78852c14-3c24-423a-bc26-64b00fd224eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994849452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis able_rom_integrity_check.2994849452
Directory	/workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1074569393
Short name	T740
Test name
Test status
Simulation time	37301947 ps
CPU time	0.6 seconds
Started	Mar 17 01:46:20 PM PDT 24
Finished	Mar 17 01:46:22 PM PDT 24
Peak memory	196644 kb
Host	smart-f86774b4-87df-467d-9ea5-c20c508bffd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074569393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst _malfunc.1074569393
Directory	/workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/48.pwrmgr_escalation_timeout.1469873005
Short name	T478
Test name
Test status
Simulation time	170780154 ps
CPU time	1.01 seconds
Started	Mar 17 01:46:13 PM PDT 24
Finished	Mar 17 01:46:14 PM PDT 24
Peak memory	197448 kb
Host	smart-104c4cea-d3cf-440a-9ead-c50683a3ded0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469873005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1469873005
Directory	/workspace/48.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/48.pwrmgr_glitch.2846999998
Short name	T381
Test name
Test status
Simulation time	53845827 ps
CPU time	0.6 seconds
Started	Mar 17 01:46:06 PM PDT 24
Finished	Mar 17 01:46:07 PM PDT 24
Peak memory	197568 kb
Host	smart-4280e66e-2a42-4fc7-adf2-a73b341e8cad
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846999998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.2846999998
Directory	/workspace/48.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/48.pwrmgr_global_esc.1873111073
Short name	T583
Test name
Test status
Simulation time	48376748 ps
CPU time	0.62 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	197488 kb
Host	smart-c2a2733f-849e-4351-856a-68c37f9c2559
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873111073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.1873111073
Directory	/workspace/48.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/48.pwrmgr_lowpower_invalid.3354964320
Short name	T486
Test name
Test status
Simulation time	41880639 ps
CPU time	0.71 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:14 PM PDT 24
Peak memory	200756 kb
Host	smart-c7119d5a-d815-41f4-a9e4-7beeec2f017a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354964320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval id.3354964320
Directory	/workspace/48.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.2158742696
Short name	T8
Test name
Test status
Simulation time	45624975 ps
CPU time	0.74 seconds
Started	Mar 17 01:46:22 PM PDT 24
Finished	Mar 17 01:46:23 PM PDT 24
Peak memory	197876 kb
Host	smart-69a81ad5-9658-4348-99a2-7f361112be31
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158742696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w akeup_race.2158742696
Directory	/workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/48.pwrmgr_reset.1599902109
Short name	T491
Test name
Test status
Simulation time	74553796 ps
CPU time	1 seconds
Started	Mar 17 01:46:06 PM PDT 24
Finished	Mar 17 01:46:07 PM PDT 24
Peak memory	199144 kb
Host	smart-a44b90d4-5141-41b4-a0a9-65f0df526a9c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599902109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1599902109
Directory	/workspace/48.pwrmgr_reset/latest

Test location	/workspace/coverage/default/48.pwrmgr_reset_invalid.4253845655
Short name	T151
Test name
Test status
Simulation time	153344610 ps
CPU time	0.82 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:14 PM PDT 24
Peak memory	200732 kb
Host	smart-ca001c73-0e8b-4311-9e80-e985d68c9d98
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253845655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.4253845655
Directory	/workspace/48.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3177750853
Short name	T712
Test name
Test status
Simulation time	1087915264 ps
CPU time	1.92 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:15 PM PDT 24
Peak memory	200648 kb
Host	smart-4a58bf33-3967-4e05-8bc1-2c90542e82de
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177750853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3177750853
Directory	/workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2181150493
Short name	T682
Test name
Test status
Simulation time	870104587 ps
CPU time	3.29 seconds
Started	Mar 17 01:46:21 PM PDT 24
Finished	Mar 17 01:46:25 PM PDT 24
Peak memory	200608 kb
Host	smart-b58967a4-5e6a-4a90-82ba-4ba23746f8cf
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181150493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2181150493
Directory	/workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2010741618
Short name	T540
Test name
Test status
Simulation time	587153728 ps
CPU time	0.86 seconds
Started	Mar 17 01:46:07 PM PDT 24
Finished	Mar 17 01:46:09 PM PDT 24
Peak memory	198560 kb
Host	smart-b922be28-e97a-450f-98d1-7a5dc7db4445
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010741618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig _mubi.2010741618
Directory	/workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/48.pwrmgr_smoke.4253428280
Short name	T845
Test name
Test status
Simulation time	28899784 ps
CPU time	0.69 seconds
Started	Mar 17 01:46:20 PM PDT 24
Finished	Mar 17 01:46:22 PM PDT 24
Peak memory	198720 kb
Host	smart-1819f01f-b5d1-40f0-b513-187138a8870f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253428280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.4253428280
Directory	/workspace/48.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/48.pwrmgr_wakeup_reset.3051708732
Short name	T650
Test name
Test status
Simulation time	226959649 ps
CPU time	1.2 seconds
Started	Mar 17 01:46:13 PM PDT 24
Finished	Mar 17 01:46:15 PM PDT 24
Peak memory	199392 kb
Host	smart-2ca018dd-47c9-4cac-aba8-ede7194fe944
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051708732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.3051708732
Directory	/workspace/48.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/49.pwrmgr_aborted_low_power.1282559840
Short name	T552
Test name
Test status
Simulation time	112575308 ps
CPU time	0.76 seconds
Started	Mar 17 01:46:11 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	198164 kb
Host	smart-a3e33651-be17-4feb-b2fe-f4bcf76c450e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282559840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1282559840
Directory	/workspace/49.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.2590107534
Short name	T332
Test name
Test status
Simulation time	78301572 ps
CPU time	0.7 seconds
Started	Mar 17 01:46:13 PM PDT 24
Finished	Mar 17 01:46:14 PM PDT 24
Peak memory	198528 kb
Host	smart-c418b82c-7b3d-4980-9f22-10a361a679b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590107534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis able_rom_integrity_check.2590107534
Directory	/workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3450235418
Short name	T183
Test name
Test status
Simulation time	30644912 ps
CPU time	0.63 seconds
Started	Mar 17 01:46:35 PM PDT 24
Finished	Mar 17 01:46:35 PM PDT 24
Peak memory	197368 kb
Host	smart-a25a684a-c410-405e-8bd2-735846442a25
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450235418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst _malfunc.3450235418
Directory	/workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/49.pwrmgr_escalation_timeout.2349830442
Short name	T196
Test name
Test status
Simulation time	757841501 ps
CPU time	0.93 seconds
Started	Mar 17 01:46:15 PM PDT 24
Finished	Mar 17 01:46:16 PM PDT 24
Peak memory	197528 kb
Host	smart-5a4ed385-0103-4ea9-bc80-d7cb09d8ea01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349830442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.2349830442
Directory	/workspace/49.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/49.pwrmgr_glitch.2855919334
Short name	T437
Test name
Test status
Simulation time	42284815 ps
CPU time	0.6 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:18 PM PDT 24
Peak memory	197496 kb
Host	smart-291ef310-338b-42bf-9e86-1f88785d4689
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855919334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2855919334
Directory	/workspace/49.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/49.pwrmgr_global_esc.2217600502
Short name	T487
Test name
Test status
Simulation time	23113002 ps
CPU time	0.63 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	197464 kb
Host	smart-e56bf1dd-3ec7-460c-8f06-3cb082076ec2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217600502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2217600502
Directory	/workspace/49.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/49.pwrmgr_lowpower_invalid.1058779045
Short name	T524
Test name
Test status
Simulation time	43085648 ps
CPU time	0.73 seconds
Started	Mar 17 01:46:11 PM PDT 24
Finished	Mar 17 01:46:13 PM PDT 24
Peak memory	200796 kb
Host	smart-e6704043-7961-433f-80ec-a2321e39fa10
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058779045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval id.1058779045
Directory	/workspace/49.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.2576820132
Short name	T857
Test name
Test status
Simulation time	146303266 ps
CPU time	0.66 seconds
Started	Mar 17 01:46:27 PM PDT 24
Finished	Mar 17 01:46:28 PM PDT 24
Peak memory	197540 kb
Host	smart-af0d0c54-dc42-470f-97f7-7f9fe695af01
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576820132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_w akeup_race.2576820132
Directory	/workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/49.pwrmgr_reset.391462874
Short name	T579
Test name
Test status
Simulation time	65291549 ps
CPU time	0.91 seconds
Started	Mar 17 01:46:38 PM PDT 24
Finished	Mar 17 01:46:39 PM PDT 24
Peak memory	199264 kb
Host	smart-6816fb57-ef79-4fa6-95e1-55e5203154b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391462874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.391462874
Directory	/workspace/49.pwrmgr_reset/latest

Test location	/workspace/coverage/default/49.pwrmgr_reset_invalid.2116602162
Short name	T561
Test name
Test status
Simulation time	111302902 ps
CPU time	0.96 seconds
Started	Mar 17 01:46:23 PM PDT 24
Finished	Mar 17 01:46:24 PM PDT 24
Peak memory	208820 kb
Host	smart-f7db389f-33b0-4810-bcf7-d3befd62dc78
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116602162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2116602162
Directory	/workspace/49.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.1369053599
Short name	T368
Test name
Test status
Simulation time	307797013 ps
CPU time	1.14 seconds
Started	Mar 17 01:46:12 PM PDT 24
Finished	Mar 17 01:46:18 PM PDT 24
Peak memory	199328 kb
Host	smart-4e5263f8-e90a-4e45-bc0f-0eb39d6fc1ea
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369053599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_ cm_ctrl_config_regwen.1369053599
Directory	/workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1674486570
Short name	T414
Test name
Test status
Simulation time	1006837244 ps
CPU time	1.97 seconds
Started	Mar 17 01:46:28 PM PDT 24
Finished	Mar 17 01:46:30 PM PDT 24
Peak memory	200552 kb
Host	smart-bcc683e3-1be2-4bc7-9fcd-a04f0acd49e2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674486570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1674486570
Directory	/workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3692702903
Short name	T81
Test name
Test status
Simulation time	1178841335 ps
CPU time	2.42 seconds
Started	Mar 17 01:46:32 PM PDT 24
Finished	Mar 17 01:46:35 PM PDT 24
Peak memory	200412 kb
Host	smart-03ab83b2-a01d-4769-b56a-be27d82c2de9
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692702903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3692702903
Directory	/workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1259980335
Short name	T185
Test name
Test status
Simulation time	85486616 ps
CPU time	0.81 seconds
Started	Mar 17 01:46:35 PM PDT 24
Finished	Mar 17 01:46:36 PM PDT 24
Peak memory	198436 kb
Host	smart-0fe7afc0-2c03-4f2f-88e7-0d1f52befa23
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259980335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig _mubi.1259980335
Directory	/workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/49.pwrmgr_smoke.1970083287
Short name	T859
Test name
Test status
Simulation time	57304832 ps
CPU time	0.65 seconds
Started	Mar 17 01:46:35 PM PDT 24
Finished	Mar 17 01:46:35 PM PDT 24
Peak memory	197856 kb
Host	smart-6277289b-6ab9-4df1-b6d8-83e29e7b529b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970083287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1970083287
Directory	/workspace/49.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/5.pwrmgr_aborted_low_power.589967356
Short name	T688
Test name
Test status
Simulation time	29526061 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:11 PM PDT 24
Finished	Mar 17 01:44:12 PM PDT 24
Peak memory	197964 kb
Host	smart-65755ce5-dc1e-4e86-84d8-6c08566cd4ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589967356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.589967356
Directory	/workspace/5.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1067695138
Short name	T738
Test name
Test status
Simulation time	72769309 ps
CPU time	0.74 seconds
Started	Mar 17 01:44:17 PM PDT 24
Finished	Mar 17 01:44:17 PM PDT 24
Peak memory	198532 kb
Host	smart-c3ae3ec9-3866-4781-8110-14b6c049608d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067695138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa ble_rom_integrity_check.1067695138
Directory	/workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1119012073
Short name	T405
Test name
Test status
Simulation time	41368987 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:18 PM PDT 24
Finished	Mar 17 01:44:19 PM PDT 24
Peak memory	196712 kb
Host	smart-11f6da8c-1095-427a-87de-f75321cc884b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119012073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_ malfunc.1119012073
Directory	/workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/5.pwrmgr_escalation_timeout.3513213803
Short name	T816
Test name
Test status
Simulation time	169528595 ps
CPU time	1 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	197572 kb
Host	smart-3f0861da-38d3-4083-ba6a-b98b121c6859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513213803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.3513213803
Directory	/workspace/5.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/5.pwrmgr_glitch.4248165552
Short name	T513
Test name
Test status
Simulation time	41113598 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:18 PM PDT 24
Finished	Mar 17 01:44:19 PM PDT 24
Peak memory	197524 kb
Host	smart-b7a90f45-5a97-4bbb-909e-8030e0e68a48
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248165552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.4248165552
Directory	/workspace/5.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/5.pwrmgr_global_esc.259986526
Short name	T516
Test name
Test status
Simulation time	22035689 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:23 PM PDT 24
Finished	Mar 17 01:44:24 PM PDT 24
Peak memory	197532 kb
Host	smart-76b61caa-ceb0-40b7-85a1-5532cfc36f2b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259986526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.259986526
Directory	/workspace/5.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/5.pwrmgr_lowpower_invalid.2247897789
Short name	T171
Test name
Test status
Simulation time	281665103 ps
CPU time	0.65 seconds
Started	Mar 17 01:44:22 PM PDT 24
Finished	Mar 17 01:44:23 PM PDT 24
Peak memory	200804 kb
Host	smart-dbca3278-3cc4-44a2-aff2-4f0f61aa443d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247897789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali d.2247897789
Directory	/workspace/5.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.1784689036
Short name	T597
Test name
Test status
Simulation time	267903336 ps
CPU time	1.19 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	198952 kb
Host	smart-0853d5dd-3612-4385-9b46-260b996415d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784689036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa keup_race.1784689036
Directory	/workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/5.pwrmgr_reset.3217311540
Short name	T531
Test name
Test status
Simulation time	111119791 ps
CPU time	0.82 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:21 PM PDT 24
Peak memory	199212 kb
Host	smart-92a6bba3-0f93-4ce0-9b7e-6d27fee259d0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217311540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3217311540
Directory	/workspace/5.pwrmgr_reset/latest

Test location	/workspace/coverage/default/5.pwrmgr_reset_invalid.3154223914
Short name	T874
Test name
Test status
Simulation time	195264561 ps
CPU time	0.79 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	208844 kb
Host	smart-e39782b6-d023-4d23-b916-bbcddffd5e41
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154223914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.3154223914
Directory	/workspace/5.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.340024005
Short name	T500
Test name
Test status
Simulation time	259827134 ps
CPU time	1.28 seconds
Started	Mar 17 01:44:17 PM PDT 24
Finished	Mar 17 01:44:18 PM PDT 24
Peak memory	199572 kb
Host	smart-5fb33063-15f6-45ce-aedc-21be7676410b
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340024005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm _ctrl_config_regwen.340024005
Directory	/workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2198671121
Short name	T614
Test name
Test status
Simulation time	2135212588 ps
CPU time	2.11 seconds
Started	Mar 17 01:44:16 PM PDT 24
Finished	Mar 17 01:44:18 PM PDT 24
Peak memory	200516 kb
Host	smart-4e7f81e0-23ed-4e26-ae1f-56e0bc364862
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198671121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2198671121
Directory	/workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3112549282
Short name	T719
Test name
Test status
Simulation time	997945150 ps
CPU time	1.99 seconds
Started	Mar 17 01:44:18 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	200720 kb
Host	smart-e1af7d06-1f27-454f-ac02-526de4d14193
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112549282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3112549282
Directory	/workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2723797868
Short name	T293
Test name
Test status
Simulation time	266413174 ps
CPU time	0.84 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	198636 kb
Host	smart-0a126fdd-8e4d-4540-acd3-ac46f76853d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723797868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_ mubi.2723797868
Directory	/workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/5.pwrmgr_smoke.2609630221
Short name	T302
Test name
Test status
Simulation time	47301741 ps
CPU time	0.64 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	198708 kb
Host	smart-f89e4620-46e1-4087-93c8-d9e898ceef61
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609630221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.2609630221
Directory	/workspace/5.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/5.pwrmgr_stress_all.2052080626
Short name	T617
Test name
Test status
Simulation time	2894487434 ps
CPU time	3.92 seconds
Started	Mar 17 01:44:18 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	200692 kb
Host	smart-0689fc52-b1cb-4d7a-a695-464ab2f1790b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052080626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2052080626
Directory	/workspace/5.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/5.pwrmgr_wakeup_reset.1275695563
Short name	T512
Test name
Test status
Simulation time	49709032 ps
CPU time	0.76 seconds
Started	Mar 17 01:44:13 PM PDT 24
Finished	Mar 17 01:44:13 PM PDT 24
Peak memory	198668 kb
Host	smart-04625861-5f19-41fd-aa6d-76ca8104ea8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275695563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.1275695563
Directory	/workspace/5.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/6.pwrmgr_aborted_low_power.1315121394
Short name	T181
Test name
Test status
Simulation time	18626990 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:24 PM PDT 24
Finished	Mar 17 01:44:25 PM PDT 24
Peak memory	197472 kb
Host	smart-d167815c-c2d0-4d84-bb82-effda9b52eb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315121394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1315121394
Directory	/workspace/6.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.472466468
Short name	T543
Test name
Test status
Simulation time	60421917 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	198444 kb
Host	smart-bbeeacb7-a72a-412e-bdb3-709b14361a2b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472466468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disab le_rom_integrity_check.472466468
Directory	/workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1473999105
Short name	T889
Test name
Test status
Simulation time	58340940 ps
CPU time	0.59 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	197420 kb
Host	smart-826ba442-70ad-4f9a-8039-ca94a8c3560c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473999105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_ malfunc.1473999105
Directory	/workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/6.pwrmgr_escalation_timeout.4121625426
Short name	T373
Test name
Test status
Simulation time	168444875 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	197504 kb
Host	smart-db3aac90-12ab-4f34-8c76-beeb579bccd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121625426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.4121625426
Directory	/workspace/6.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/6.pwrmgr_glitch.3983687469
Short name	T553
Test name
Test status
Simulation time	34664966 ps
CPU time	0.61 seconds
Started	Mar 17 01:44:20 PM PDT 24
Finished	Mar 17 01:44:21 PM PDT 24
Peak memory	197428 kb
Host	smart-cb887457-90c6-4f3b-b0f0-162186bc8f5b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983687469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3983687469
Directory	/workspace/6.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/6.pwrmgr_global_esc.3109495249
Short name	T839
Test name
Test status
Simulation time	25414986 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:24 PM PDT 24
Finished	Mar 17 01:44:25 PM PDT 24
Peak memory	197436 kb
Host	smart-2986a766-1b5b-4c4a-89f7-988e36b88cf2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109495249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3109495249
Directory	/workspace/6.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/6.pwrmgr_lowpower_invalid.999982670
Short name	T410
Test name
Test status
Simulation time	45623033 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	200612 kb
Host	smart-a1f05bad-e0cd-488b-90ec-3783d36f7603
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999982670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid .999982670
Directory	/workspace/6.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/6.pwrmgr_reset.618500369
Short name	T296
Test name
Test status
Simulation time	46852366 ps
CPU time	0.78 seconds
Started	Mar 17 01:44:23 PM PDT 24
Finished	Mar 17 01:44:24 PM PDT 24
Peak memory	197888 kb
Host	smart-7c2f8483-772c-4684-b54c-e55e22ca842f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618500369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.618500369
Directory	/workspace/6.pwrmgr_reset/latest

Test location	/workspace/coverage/default/6.pwrmgr_reset_invalid.1946370881
Short name	T619
Test name
Test status
Simulation time	171692163 ps
CPU time	0.8 seconds
Started	Mar 17 01:44:20 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	208968 kb
Host	smart-3fa3a8c8-e06e-42db-b6d1-a24a939e9437
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946370881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1946370881
Directory	/workspace/6.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1423809880
Short name	T887
Test name
Test status
Simulation time	837738328 ps
CPU time	3 seconds
Started	Mar 17 01:44:21 PM PDT 24
Finished	Mar 17 01:44:24 PM PDT 24
Peak memory	200456 kb
Host	smart-fc49d459-2ba3-47e6-9c39-503c879c5509
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423809880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1423809880
Directory	/workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2934344244
Short name	T501
Test name
Test status
Simulation time	795111026 ps
CPU time	2.73 seconds
Started	Mar 17 01:44:22 PM PDT 24
Finished	Mar 17 01:44:24 PM PDT 24
Peak memory	200652 kb
Host	smart-ef748ae2-c30a-4a0b-885a-08f6bf75193a
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934344244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2934344244
Directory	/workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1107955470
Short name	T450
Test name
Test status
Simulation time	54385527 ps
CPU time	0.9 seconds
Started	Mar 17 01:44:20 PM PDT 24
Finished	Mar 17 01:44:21 PM PDT 24
Peak memory	198604 kb
Host	smart-99fcbfbf-53f4-4b10-b038-99c81497c6f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107955470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_ mubi.1107955470
Directory	/workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/6.pwrmgr_smoke.2821086835
Short name	T775
Test name
Test status
Simulation time	28654015 ps
CPU time	0.67 seconds
Started	Mar 17 01:44:22 PM PDT 24
Finished	Mar 17 01:44:22 PM PDT 24
Peak memory	197848 kb
Host	smart-3923bea2-558c-475b-bf37-6b9a10682c51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821086835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.2821086835
Directory	/workspace/6.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/6.pwrmgr_stress_all.3084886074
Short name	T674
Test name
Test status
Simulation time	143695606 ps
CPU time	0.95 seconds
Started	Mar 17 01:44:24 PM PDT 24
Finished	Mar 17 01:44:25 PM PDT 24
Peak memory	198132 kb
Host	smart-0672de1a-7c5f-4f38-8edb-bc7a8571956d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084886074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.3084886074
Directory	/workspace/6.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/6.pwrmgr_wakeup.4073453623
Short name	T686
Test name
Test status
Simulation time	213246140 ps
CPU time	0.84 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	197936 kb
Host	smart-31067666-a03b-471e-acb8-0db391f5726b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073453623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.4073453623
Directory	/workspace/6.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/6.pwrmgr_wakeup_reset.2407879184
Short name	T377
Test name
Test status
Simulation time	247392489 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:25 PM PDT 24
Finished	Mar 17 01:44:26 PM PDT 24
Peak memory	199576 kb
Host	smart-4a5629cc-689e-4161-87b3-7143ad0f33c9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407879184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.2407879184
Directory	/workspace/6.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/7.pwrmgr_aborted_low_power.1681593134
Short name	T256
Test name
Test status
Simulation time	60950827 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:26 PM PDT 24
Finished	Mar 17 01:44:27 PM PDT 24
Peak memory	197928 kb
Host	smart-0a95246a-617d-4eca-b48c-19727c02153e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681593134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1681593134
Directory	/workspace/7.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.918497332
Short name	T284
Test name
Test status
Simulation time	73719824 ps
CPU time	0.76 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	197752 kb
Host	smart-a870e53b-000c-48cc-8f1e-59530107d16b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918497332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab le_rom_integrity_check.918497332
Directory	/workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1912250931
Short name	T645
Test name
Test status
Simulation time	29083832 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:23 PM PDT 24
Finished	Mar 17 01:44:24 PM PDT 24
Peak memory	197460 kb
Host	smart-29ac22a2-3e51-45e0-974d-17e2e6bb0eef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912250931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_ malfunc.1912250931
Directory	/workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/7.pwrmgr_escalation_timeout.83785
Short name	T433
Test name
Test status
Simulation time	164642550 ps
CPU time	0.97 seconds
Started	Mar 17 01:44:30 PM PDT 24
Finished	Mar 17 01:44:31 PM PDT 24
Peak memory	197752 kb
Host	smart-4716ed53-91f7-458d-af4b-9721af0a20c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.83785
Directory	/workspace/7.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/7.pwrmgr_glitch.3973705528
Short name	T311
Test name
Test status
Simulation time	225926730 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:36 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	196724 kb
Host	smart-dedd4fd0-2d30-4522-ab0d-670ce17dc69f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973705528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3973705528
Directory	/workspace/7.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/7.pwrmgr_global_esc.1122743892
Short name	T372
Test name
Test status
Simulation time	22738186 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	197772 kb
Host	smart-253660fc-f8fc-42bd-b0d4-9cda87e392dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122743892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1122743892
Directory	/workspace/7.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/7.pwrmgr_lowpower_invalid.2459996900
Short name	T328
Test name
Test status
Simulation time	109516415 ps
CPU time	0.7 seconds
Started	Mar 17 01:44:30 PM PDT 24
Finished	Mar 17 01:44:31 PM PDT 24
Peak memory	200792 kb
Host	smart-12a96248-eb16-4311-b638-3f6de2f69497
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459996900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali d.2459996900
Directory	/workspace/7.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.3135168131
Short name	T629
Test name
Test status
Simulation time	131488465 ps
CPU time	0.77 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	197680 kb
Host	smart-fd1400dc-cbce-4226-ac9f-2fa9c71fc47e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135168131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wa keup_race.3135168131
Directory	/workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/7.pwrmgr_reset.617595828
Short name	T465
Test name
Test status
Simulation time	68639763 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:23 PM PDT 24
Finished	Mar 17 01:44:24 PM PDT 24
Peak memory	199276 kb
Host	smart-4557333f-02ec-4ad8-a9f7-d87c415d2902
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617595828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.617595828
Directory	/workspace/7.pwrmgr_reset/latest

Test location	/workspace/coverage/default/7.pwrmgr_reset_invalid.234521607
Short name	T425
Test name
Test status
Simulation time	102311488 ps
CPU time	1.09 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	208816 kb
Host	smart-a0ca1881-06f2-421e-bbfe-da82335a7616
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234521607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.234521607
Directory	/workspace/7.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.224465291
Short name	T439
Test name
Test status
Simulation time	892239640 ps
CPU time	3.4 seconds
Started	Mar 17 01:44:24 PM PDT 24
Finished	Mar 17 01:44:27 PM PDT 24
Peak memory	200600 kb
Host	smart-25da2ee6-6c2f-4781-9ca8-d822d2a75ac5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224465291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.224465291
Directory	/workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2101220681
Short name	T161
Test name
Test status
Simulation time	1231186832 ps
CPU time	2.25 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:21 PM PDT 24
Peak memory	200496 kb
Host	smart-4e78085d-6d5d-40e9-b927-7ebc6677a752
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101220681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2101220681
Directory	/workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2691354588
Short name	T798
Test name
Test status
Simulation time	271969758 ps
CPU time	0.84 seconds
Started	Mar 17 01:44:19 PM PDT 24
Finished	Mar 17 01:44:20 PM PDT 24
Peak memory	198724 kb
Host	smart-e8899c26-1512-4517-87fe-9ef39bb4f963
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691354588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_ mubi.2691354588
Directory	/workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/7.pwrmgr_smoke.726635808
Short name	T609
Test name
Test status
Simulation time	36029823 ps
CPU time	0.66 seconds
Started	Mar 17 01:44:20 PM PDT 24
Finished	Mar 17 01:44:21 PM PDT 24
Peak memory	197844 kb
Host	smart-b23ecc9e-204e-4590-9d84-b8fdc0330d8b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726635808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.726635808
Directory	/workspace/7.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/7.pwrmgr_wakeup_reset.2892403947
Short name	T836
Test name
Test status
Simulation time	301310578 ps
CPU time	0.83 seconds
Started	Mar 17 01:44:20 PM PDT 24
Finished	Mar 17 01:44:21 PM PDT 24
Peak memory	199284 kb
Host	smart-6fae647a-bde4-49a7-97ad-f4119c714ad2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892403947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2892403947
Directory	/workspace/7.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/8.pwrmgr_aborted_low_power.910813671
Short name	T483
Test name
Test status
Simulation time	45889298 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:34 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	197112 kb
Host	smart-c0bf20dd-79c2-440b-a995-9529b5f3c30d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910813671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.910813671
Directory	/workspace/8.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.2118829686
Short name	T418
Test name
Test status
Simulation time	80008515 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	197848 kb
Host	smart-b57c2820-237c-4a1e-b96c-ffe5028991b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118829686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa ble_rom_integrity_check.2118829686
Directory	/workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.619079700
Short name	T455
Test name
Test status
Simulation time	38358084 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	196872 kb
Host	smart-a640cbda-a490-47af-b48d-b290b4091d78
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619079700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_m alfunc.619079700
Directory	/workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/8.pwrmgr_escalation_timeout.11352393
Short name	T648
Test name
Test status
Simulation time	636134335 ps
CPU time	0.98 seconds
Started	Mar 17 01:44:26 PM PDT 24
Finished	Mar 17 01:44:27 PM PDT 24
Peak memory	197828 kb
Host	smart-9d0c5529-325d-46bb-9e42-aea4f966d221
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11352393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.11352393
Directory	/workspace/8.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/8.pwrmgr_glitch.2202170095
Short name	T729
Test name
Test status
Simulation time	47640515 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:34 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	195848 kb
Host	smart-d7b52448-a480-4e3d-9708-d174f24d6532
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202170095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2202170095
Directory	/workspace/8.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/8.pwrmgr_global_esc.2918801347
Short name	T578
Test name
Test status
Simulation time	24281056 ps
CPU time	0.63 seconds
Started	Mar 17 01:44:31 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	197476 kb
Host	smart-7309c4d5-ae03-4a55-a441-e28113c55668
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918801347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2918801347
Directory	/workspace/8.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/8.pwrmgr_lowpower_invalid.2629008707
Short name	T145
Test name
Test status
Simulation time	87623184 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:34 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	200716 kb
Host	smart-ebe5cfd5-8dea-4456-82b4-b6614a8026e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629008707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali d.2629008707
Directory	/workspace/8.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.3694554012
Short name	T799
Test name
Test status
Simulation time	255607279 ps
CPU time	1.05 seconds
Started	Mar 17 01:44:31 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	199068 kb
Host	smart-852fe642-8893-4ba3-bca0-db7c6901011d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694554012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa keup_race.3694554012
Directory	/workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/8.pwrmgr_reset.1142862933
Short name	T714
Test name
Test status
Simulation time	81738156 ps
CPU time	0.71 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	197740 kb
Host	smart-a232c208-ac23-43cc-8f6c-b89deb0f0f56
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142862933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1142862933
Directory	/workspace/8.pwrmgr_reset/latest

Test location	/workspace/coverage/default/8.pwrmgr_reset_invalid.2162799224
Short name	T888
Test name
Test status
Simulation time	127960576 ps
CPU time	0.86 seconds
Started	Mar 17 01:44:33 PM PDT 24
Finished	Mar 17 01:44:34 PM PDT 24
Peak memory	208848 kb
Host	smart-59f00c80-2a9b-43fc-8359-cc04fcdb9029
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162799224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2162799224
Directory	/workspace/8.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.1683913538
Short name	T852
Test name
Test status
Simulation time	240713823 ps
CPU time	0.8 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	198552 kb
Host	smart-776c7d74-7ef8-40e4-a79e-6afd1f6620c2
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683913538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c m_ctrl_config_regwen.1683913538
Directory	/workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1643739919
Short name	T271
Test name
Test status
Simulation time	927047128 ps
CPU time	2.08 seconds
Started	Mar 17 01:44:30 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	200484 kb
Host	smart-5df5f63e-f841-493d-8117-7aa284c24680
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643739919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1643739919
Directory	/workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1828872737
Short name	T634
Test name
Test status
Simulation time	1052610823 ps
CPU time	2.11 seconds
Started	Mar 17 01:44:29 PM PDT 24
Finished	Mar 17 01:44:31 PM PDT 24
Peak memory	200572 kb
Host	smart-8ec8a0fa-2648-46ec-a9bb-8d668dc88a61
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828872737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1828872737
Directory	/workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2511348218
Short name	T846
Test name
Test status
Simulation time	111351419 ps
CPU time	0.92 seconds
Started	Mar 17 01:44:34 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	198704 kb
Host	smart-0368c2cc-6f43-4f83-ab2a-fc8371db9614
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511348218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_ mubi.2511348218
Directory	/workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/8.pwrmgr_smoke.2027353108
Short name	T509
Test name
Test status
Simulation time	41933451 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:29 PM PDT 24
Finished	Mar 17 01:44:30 PM PDT 24
Peak memory	197804 kb
Host	smart-f566bc29-1545-48fd-a7d2-9096323538bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027353108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2027353108
Directory	/workspace/8.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/8.pwrmgr_wakeup.2597595049
Short name	T144
Test name
Test status
Simulation time	100851138 ps
CPU time	0.72 seconds
Started	Mar 17 01:44:31 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	198476 kb
Host	smart-268e1349-7f9e-4a66-b417-4927ea28a4e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597595049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.2597595049
Directory	/workspace/8.pwrmgr_wakeup/latest

Test location	/workspace/coverage/default/8.pwrmgr_wakeup_reset.788622862
Short name	T299
Test name
Test status
Simulation time	129469933 ps
CPU time	0.89 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:39 PM PDT 24
Peak memory	198684 kb
Host	smart-57253b6e-083b-443f-92a6-c273101ac06d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788622862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.788622862
Directory	/workspace/8.pwrmgr_wakeup_reset/latest

Test location	/workspace/coverage/default/9.pwrmgr_aborted_low_power.1337975517
Short name	T820
Test name
Test status
Simulation time	27233121 ps
CPU time	0.75 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	198084 kb
Host	smart-b4125d99-ac6b-4885-9371-72919fbbd946
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337975517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.1337975517
Directory	/workspace/9.pwrmgr_aborted_low_power/latest

Test location	/workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2368202773
Short name	T523
Test name
Test status
Simulation time	94955051 ps
CPU time	0.78 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	198560 kb
Host	smart-0a7b6d5a-9ebe-4753-b880-09c8ed546359
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368202773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa ble_rom_integrity_check.2368202773
Directory	/workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.711237887
Short name	T794
Test name
Test status
Simulation time	79180523 ps
CPU time	0.6 seconds
Started	Mar 17 01:44:30 PM PDT 24
Finished	Mar 17 01:44:31 PM PDT 24
Peak memory	197412 kb
Host	smart-6f574217-17fe-4531-bac3-549a13b2c197
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711237887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_m alfunc.711237887
Directory	/workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspace/coverage/default/9.pwrmgr_escalation_timeout.3769098754
Short name	T692
Test name
Test status
Simulation time	732562965 ps
CPU time	1.08 seconds
Started	Mar 17 01:44:37 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	197464 kb
Host	smart-abae0ded-0c61-4a28-b5ac-1736ddb4aff7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769098754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3769098754
Directory	/workspace/9.pwrmgr_escalation_timeout/latest

Test location	/workspace/coverage/default/9.pwrmgr_glitch.229218402
Short name	T34
Test name
Test status
Simulation time	38146577 ps
CPU time	0.62 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	197508 kb
Host	smart-225649b2-f098-4691-84af-cbf3e650d189
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229218402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.229218402
Directory	/workspace/9.pwrmgr_glitch/latest

Test location	/workspace/coverage/default/9.pwrmgr_global_esc.3256497046
Short name	T624
Test name
Test status
Simulation time	28832590 ps
CPU time	0.59 seconds
Started	Mar 17 01:44:38 PM PDT 24
Finished	Mar 17 01:44:38 PM PDT 24
Peak memory	197820 kb
Host	smart-fcd1b05b-9ddc-4edc-888e-1ad4c72a896c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256497046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3256497046
Directory	/workspace/9.pwrmgr_global_esc/latest

Test location	/workspace/coverage/default/9.pwrmgr_lowpower_invalid.340851492
Short name	T630
Test name
Test status
Simulation time	43267773 ps
CPU time	0.73 seconds
Started	Mar 17 01:44:33 PM PDT 24
Finished	Mar 17 01:44:34 PM PDT 24
Peak memory	200704 kb
Host	smart-21c241fc-40bd-4eba-8f9c-295f2ebe19d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340851492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid .340851492
Directory	/workspace/9.pwrmgr_lowpower_invalid/latest

Test location	/workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.1227308605
Short name	T793
Test name
Test status
Simulation time	192925717 ps
CPU time	0.83 seconds
Started	Mar 17 01:44:34 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	198460 kb
Host	smart-bacf30b6-3e33-4cd4-834b-d89c86f5408a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227308605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa keup_race.1227308605
Directory	/workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspace/coverage/default/9.pwrmgr_reset.4134549616
Short name	T217
Test name
Test status
Simulation time	53705396 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:36 PM PDT 24
Finished	Mar 17 01:44:37 PM PDT 24
Peak memory	197916 kb
Host	smart-c60e84a2-4654-4428-9c85-66e00b8fc05b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134549616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.4134549616
Directory	/workspace/9.pwrmgr_reset/latest

Test location	/workspace/coverage/default/9.pwrmgr_reset_invalid.1194992721
Short name	T536
Test name
Test status
Simulation time	169913923 ps
CPU time	0.8 seconds
Started	Mar 17 01:44:29 PM PDT 24
Finished	Mar 17 01:44:30 PM PDT 24
Peak memory	208964 kb
Host	smart-c6ca5b20-7659-4ca0-9845-c3ddb28484bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194992721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1194992721
Directory	/workspace/9.pwrmgr_reset_invalid/latest

Test location	/workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.2874049354
Short name	T883
Test name
Test status
Simulation time	314409208 ps
CPU time	1.01 seconds
Started	Mar 17 01:44:35 PM PDT 24
Finished	Mar 17 01:44:36 PM PDT 24
Peak memory	200272 kb
Host	smart-ba62fc9d-5d0b-4e0d-97f3-e1d89b2dbf18
User	root
Command	/workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874049354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_ config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_c m_ctrl_config_regwen.2874049354
Directory	/workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1910079860
Short name	T861
Test name
Test status
Simulation time	840148844 ps
CPU time	2.92 seconds
Started	Mar 17 01:44:34 PM PDT 24
Finished	Mar 17 01:44:37 PM PDT 24
Peak memory	200656 kb
Host	smart-0a39cff1-c299-4412-a9e3-551a195e261f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910079860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1910079860
Directory	/workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.371898224
Short name	T458
Test name
Test status
Simulation time	897096981 ps
CPU time	2.59 seconds
Started	Mar 17 01:44:33 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	200636 kb
Host	smart-49858e4e-4bf1-48c8-af14-c3da00e0a6ca
User	root
Command	/workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371898224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.371898224
Directory	/workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1158328374
Short name	T843
Test name
Test status
Simulation time	255264448 ps
CPU time	0.87 seconds
Started	Mar 17 01:44:31 PM PDT 24
Finished	Mar 17 01:44:32 PM PDT 24
Peak memory	198716 kb
Host	smart-e6f83fa5-6ef6-4412-9d0b-15cb987bb279
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158328374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_ mubi.1158328374
Directory	/workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspace/coverage/default/9.pwrmgr_smoke.4181574684
Short name	T803
Test name
Test status
Simulation time	117139561 ps
CPU time	0.69 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	197816 kb
Host	smart-4f569c3a-effc-4652-bcea-4cbcea42d28c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181574684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.4181574684
Directory	/workspace/9.pwrmgr_smoke/latest

Test location	/workspace/coverage/default/9.pwrmgr_stress_all.276840400
Short name	T83
Test name
Test status
Simulation time	4444516064 ps
CPU time	5.2 seconds
Started	Mar 17 01:44:29 PM PDT 24
Finished	Mar 17 01:44:35 PM PDT 24
Peak memory	200728 kb
Host	smart-3f7ea948-6013-4c43-841e-9952391c86e9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276840400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.276840400
Directory	/workspace/9.pwrmgr_stress_all/latest

Test location	/workspace/coverage/default/9.pwrmgr_wakeup_reset.2099421192
Short name	T822
Test name
Test status
Simulation time	299994703 ps
CPU time	0.94 seconds
Started	Mar 17 01:44:32 PM PDT 24
Finished	Mar 17 01:44:33 PM PDT 24
Peak memory	199324 kb
Host	smart-1ae666de-91aa-4ca8-83d8-a01404e654b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099421192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.2099421192
Directory	/workspace/9.pwrmgr_wakeup_reset/latest

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