Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	190441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

73095

1

T1

396

T3

191

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132707	1			T1	901		T2	1		T3	430
values[0x0]	65006	1			T1	519		T3	207		T8	15
values[0x1]	65823	1			T1	481		T3	208		T8	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

113511

1

T1

707

T3

323

T7

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	824	1			T1	4		T3	4		T8	1
valid_sources[0x01]	757	1			T1	6		T3	3		T22	5
valid_sources[0x02]	887	1			T1	6		T3	4		T22	2
valid_sources[0x03]	759	1			T1	3		T3	5		T11	2
valid_sources[0x04]	903	1			T1	5		T3	4		T22	5
valid_sources[0x05]	906	1			T1	17		T3	7		T22	1
valid_sources[0x06]	769	1			T1	15		T3	3		T7	1
valid_sources[0x07]	1211	1			T1	5		T3	2		T4	21
valid_sources[0x08]	789	1			T1	13		T3	5		T11	2
valid_sources[0x09]	690	1			T3	5		T11	2		T22	2
valid_sources[0x0a]	1034	1			T1	18		T3	6		T22	2
valid_sources[0x0b]	1045	1			T1	10		T3	2		T22	6
valid_sources[0x0c]	1623	1			T1	15		T3	2		T9	1
valid_sources[0x0d]	857	1			T1	3		T3	5		T8	1
valid_sources[0x0e]	907	1			T1	4		T3	2		T11	3
valid_sources[0x0f]	812	1			T1	9		T3	4		T22	1
valid_sources[0x10]	767	1			T1	5		T3	4		T22	3
valid_sources[0x11]	935	1			T1	2		T3	4		T11	5
valid_sources[0x12]	675	1			T9	2		T11	1		T22	2
valid_sources[0x13]	717	1			T1	5		T3	4		T22	4
valid_sources[0x14]	953	1			T1	13		T3	4		T9	1
valid_sources[0x15]	796	1			T1	7		T3	5		T8	1
valid_sources[0x16]	806	1			T1	1		T3	3		T9	1
valid_sources[0x17]	744	1			T1	2		T3	3		T22	5
valid_sources[0x18]	882	1			T1	1		T3	1		T11	1
valid_sources[0x19]	930	1			T1	8		T3	3		T22	3
valid_sources[0x1a]	1677	1			T1	2		T3	6		T9	1
valid_sources[0x1b]	738	1			T1	15		T3	3		T10	1
valid_sources[0x1c]	894	1			T1	14		T3	5		T9	1
valid_sources[0x1d]	792	1			T1	1		T3	7		T8	1
valid_sources[0x1e]	3813	1			T3	4		T9	1		T22	3
valid_sources[0x1f]	2669	1			T1	6		T3	3		T22	5
valid_sources[0x20]	976	1			T1	3		T3	2		T11	1
valid_sources[0x21]	1170	1			T1	12		T10	2		T22	2
valid_sources[0x22]	950	1			T1	2		T3	3		T29	1
valid_sources[0x23]	802	1			T1	7		T3	4		T8	1
valid_sources[0x24]	1016	1			T1	11		T3	6		T22	3
valid_sources[0x25]	866	1			T1	5		T3	4		T22	1
valid_sources[0x26]	747	1			T1	20		T3	4		T10	5
valid_sources[0x27]	1127	1			T1	4		T3	4		T22	1
valid_sources[0x28]	749	1			T1	16		T3	1		T8	2
valid_sources[0x29]	910	1			T1	5		T3	4		T8	1
valid_sources[0x2a]	1686	1			T1	15		T3	4		T22	3
valid_sources[0x2b]	769	1			T1	12		T3	2		T22	8
valid_sources[0x2c]	842	1			T1	16		T3	6		T22	5
valid_sources[0x2d]	790	1			T3	5		T11	4		T22	2
valid_sources[0x2e]	733	1			T1	5		T3	4		T9	2
valid_sources[0x2f]	1799	1			T3	4		T22	3		T31	2
valid_sources[0x30]	869	1			T1	5		T3	5		T8	1
valid_sources[0x31]	1016	1			T3	4		T22	4		T26	1
valid_sources[0x32]	845	1			T1	3		T3	3		T22	3
valid_sources[0x33]	735	1			T3	4		T22	2		T32	2
valid_sources[0x34]	662	1			T1	2		T3	4		T8	1
valid_sources[0x35]	734	1			T1	4		T3	4		T8	1
valid_sources[0x36]	777	1			T1	40		T3	3		T11	1
valid_sources[0x37]	796	1			T1	5		T3	2		T22	3
valid_sources[0x38]	729	1			T3	1		T26	1		T31	1
valid_sources[0x39]	776	1			T1	7		T3	1		T22	4
valid_sources[0x3a]	997	1			T1	15		T3	2		T11	4
valid_sources[0x3b]	832	1			T1	12		T3	7		T11	5
valid_sources[0x3c]	707	1			T22	4		T29	1		T32	6
valid_sources[0x3d]	1665	1			T1	29		T3	5		T11	1
valid_sources[0x3e]	793	1			T1	7		T3	5		T8	1
valid_sources[0x3f]	1707	1			T1	8		T3	3		T10	9
valid_sources[0x40]	1645	1			T1	3		T3	3		T22	2
valid_sources[0x41]	748	1			T1	8		T3	3		T22	6
valid_sources[0x42]	834	1			T1	12		T3	6		T22	9
valid_sources[0x43]	976	1			T1	1		T3	2		T22	2
valid_sources[0x44]	1101	1			T3	5		T22	3		T15	5
valid_sources[0x45]	1654	1			T1	2		T3	2		T11	3
valid_sources[0x46]	794	1			T1	9		T3	1		T11	4
valid_sources[0x47]	1353	1			T1	4		T3	5		T11	2
valid_sources[0x48]	1615	1			T1	3		T9	1		T11	3
valid_sources[0x49]	942	1			T1	4		T3	4		T8	4
valid_sources[0x4a]	639	1			T1	9		T3	1		T22	1
valid_sources[0x4b]	1634	1			T1	11		T3	4		T10	11
valid_sources[0x4c]	828	1			T1	15		T3	3		T8	1
valid_sources[0x4d]	771	1			T1	11		T3	3		T9	1
valid_sources[0x4e]	11136	1			T3	3		T11	3		T22	2
valid_sources[0x4f]	805	1			T1	15		T3	2		T8	1
valid_sources[0x50]	894	1			T1	3		T3	4		T10	5
valid_sources[0x51]	921	1			T1	8		T3	7		T8	2
valid_sources[0x52]	871	1			T1	22		T3	9		T22	3
valid_sources[0x53]	977	1			T1	5		T3	3		T8	2
valid_sources[0x54]	1648	1			T1	13		T3	1		T22	5
valid_sources[0x55]	842	1			T1	7		T3	1		T8	1
valid_sources[0x56]	760	1			T1	1		T3	4		T22	3
valid_sources[0x57]	786	1			T1	1		T3	3		T9	1
valid_sources[0x58]	799	1			T1	9		T3	2		T11	2
valid_sources[0x59]	762	1			T1	9		T3	3		T9	1
valid_sources[0x5a]	798	1			T3	2		T8	1		T9	1
valid_sources[0x5b]	679	1			T1	2		T3	1		T22	7
valid_sources[0x5c]	977	1			T1	8		T3	1		T11	3
valid_sources[0x5d]	953	1			T1	17		T3	7		T22	4
valid_sources[0x5e]	1566	1			T1	1		T3	2		T8	1
valid_sources[0x5f]	790	1			T1	12		T3	4		T8	2
valid_sources[0x60]	1607	1			T3	4		T11	2		T22	3
valid_sources[0x61]	752	1			T1	2		T3	4		T22	1
valid_sources[0x62]	805	1			T1	4		T3	3		T8	1
valid_sources[0x63]	782	1			T1	9		T3	2		T11	1
valid_sources[0x64]	965	1			T3	5		T10	6		T22	3
valid_sources[0x65]	912	1			T1	6		T3	5		T22	4
valid_sources[0x66]	867	1			T1	4		T3	1		T22	4
valid_sources[0x67]	1764	1			T1	5		T3	3		T8	1
valid_sources[0x68]	844	1			T1	22		T3	2		T22	4
valid_sources[0x69]	1255	1			T1	15		T3	3		T22	2
valid_sources[0x6a]	716	1			T1	7		T3	1		T9	1
valid_sources[0x6b]	1628	1			T1	10		T3	5		T11	2
valid_sources[0x6c]	832	1			T1	10		T3	2		T22	6
valid_sources[0x6d]	760	1			T1	12		T9	2		T22	3
valid_sources[0x6e]	724	1			T1	1		T3	4		T11	1
valid_sources[0x6f]	835	1			T1	2		T3	2		T8	1
valid_sources[0x70]	1186	1			T1	10		T3	6		T10	2
valid_sources[0x71]	832	1			T1	6		T3	1		T8	1
valid_sources[0x72]	777	1			T1	6		T3	5		T8	1
valid_sources[0x73]	735	1			T1	13		T3	2		T11	2
valid_sources[0x74]	902	1			T1	18		T3	5		T8	1
valid_sources[0x75]	2054	1			T1	15		T3	7		T9	2
valid_sources[0x76]	969	1			T1	5		T3	3		T11	1
valid_sources[0x77]	743	1			T3	3		T8	1		T22	2
valid_sources[0x78]	1745	1			T1	15		T3	3		T9	1
valid_sources[0x79]	720	1			T1	9		T3	3		T11	1
valid_sources[0x7a]	852	1			T1	10		T3	3		T22	5
valid_sources[0x7b]	972	1			T1	6		T3	4		T22	4
valid_sources[0x7c]	863	1			T1	7		T3	4		T22	2
valid_sources[0x7d]	834	1			T1	1		T3	2		T8	1
valid_sources[0x7e]	3648	1			T1	2		T3	6		T22	1
valid_sources[0x7f]	1103	1			T1	1		T3	6		T22	4
valid_sources[0x80]	797	1			T1	5		T3	5		T22	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33016

1

T1

159

T3

90

T7

1

values[0x0]

all_enables

biggest_size

25391

1

T1

159

T3

62

T8

6

values[0x1]

all_enables

biggest_size

14688

1

T1

78

T3

39

T8

5