SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35073 | 1 | T12 | 403 | T22 | 295 | T60 | 299 | ||||
others[1] | 35082 | 1 | T12 | 429 | T22 | 316 | T60 | 302 | ||||
others[2] | 34922 | 1 | T12 | 371 | T21 | 2 | T22 | 303 | ||||
others[3] | 58410 | 1 | T12 | 671 | T22 | 484 | T115 | 1 | ||||
false | 8686 | 1 | T1 | 94 | T3 | 38 | T9 | 3 | ||||
true | 14874 | 1 | T1 | 109 | T2 | 1 | T3 | 46 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35181 | 1 | T12 | 390 | T22 | 319 | T60 | 312 | ||||
others[1] | 35117 | 1 | T12 | 429 | T22 | 306 | T60 | 291 | ||||
others[2] | 35002 | 1 | T12 | 414 | T22 | 294 | T115 | 1 | ||||
others[3] | 58293 | 1 | T12 | 639 | T22 | 489 | T60 | 496 | ||||
false | 6936 | 1 | T1 | 47 | T3 | 19 | T9 | 3 | ||||
true | 13188 | 1 | T1 | 62 | T2 | 1 | T3 | 27 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 412 | 1 | T1 | 3 | T3 | 2 | T10 | 1 | ||||
others[1] | 414 | 1 | T1 | 1 | T10 | 1 | T11 | 1 | ||||
others[2] | 413 | 1 | T10 | 1 | T11 | 1 | T32 | 3 | ||||
others[3] | 656 | 1 | T10 | 1 | T11 | 2 | T27 | 2 | ||||
false | 5812 | 1 | T1 | 35 | T2 | 1 | T3 | 24 | ||||
true | 1376 | 1 | T1 | 16 | T3 | 14 | T9 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |