Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T35,T36

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	8307498	3274	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	8307498	129572	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	8307498	2989280	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	8307498	129601	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	8307498	3274	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	8307498	129572	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	8307498	2989280	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	8307498	129601	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	3274	0	0
T1	45968	24	0	0
T2	15135	0	0	0
T3	14144	9	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	21	0	0
T22	0	19	0	0
T25	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	129572	0	0
T1	45968	399	0	0
T2	15135	0	0	0
T3	14144	129	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	359	0	0
T22	0	409	0	0
T25	0	113	0	0
T32	0	14	0	0
T35	0	163	0	0
T36	0	143	0	0
T58	0	10	0	0
T59	0	14	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	2989280	0	0
T1	45968	18342	0	0
T2	15135	0	0	0
T3	14144	3989	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	483	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	4164	0	0
T15	0	91	0	0
T22	0	8556	0	0
T25	0	2815	0	0
T31	0	763	0	0
T35	0	138	0	0
T58	0	1316	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	129601	0	0
T1	45968	399	0	0
T2	15135	0	0	0
T3	14144	129	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	359	0	0
T22	0	409	0	0
T25	0	113	0	0
T32	0	14	0	0
T35	0	163	0	0
T36	0	143	0	0
T58	0	10	0	0
T59	0	14	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	3274	0	0
T1	45968	24	0	0
T2	15135	0	0	0
T3	14144	9	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	21	0	0
T22	0	19	0	0
T25	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	129572	0	0
T1	45968	399	0	0
T2	15135	0	0	0
T3	14144	129	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	359	0	0
T22	0	409	0	0
T25	0	113	0	0
T32	0	14	0	0
T35	0	163	0	0
T36	0	143	0	0
T58	0	10	0	0
T59	0	14	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	2989280	0	0
T1	45968	18342	0	0
T2	15135	0	0	0
T3	14144	3989	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	483	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	4164	0	0
T15	0	91	0	0
T22	0	8556	0	0
T25	0	2815	0	0
T31	0	763	0	0
T35	0	138	0	0
T58	0	1316	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	129601	0	0
T1	45968	399	0	0
T2	15135	0	0	0
T3	14144	129	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	359	0	0
T22	0	409	0	0
T25	0	113	0	0
T32	0	14	0	0
T35	0	163	0	0
T36	0	143	0	0
T58	0	10	0	0
T59	0	14	0	0