Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8906528	12288	0	0
intr_enable_rd_A	8906528	17276	0	0
reset_en_rd_A	8906528	1896	0	0
reset_en_regwen_rd_A	8906528	1467	0	0
wake_info_capture_dis_rd_A	8906528	1612	0	0
wakeup_en_rd_A	8906528	3031	0	0
wakeup_en_regwen_rd_A	8906528	1540	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8906528	12288	0	0
T18	108413	6	0	0
T19	0	4	0	0
T20	0	2	0	0
T37	0	4	0	0
T38	0	5	0	0
T39	0	3	0	0
T40	0	322	0	0
T51	0	5	0	0
T54	0	7	0	0
T103	0	3	0	0
T104	833	0	0	0
T105	2808	0	0	0
T106	18100	0	0	0
T107	2926	0	0	0
T108	27639	0	0	0
T109	3228	0	0	0
T110	15833	0	0	0
T111	7386	0	0	0
T112	9305	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8906528	17276	0	0
T1	45968	454	0	0
T2	15135	0	0	0
T3	14144	0	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	8	0	0
T10	2898	0	0	0
T11	7791	52	0	0
T12	9866	0	0	0
T22	0	164	0	0
T25	0	11	0	0
T31	0	66	0	0
T58	0	1	0	0
T59	0	12	0	0
T113	0	30	0	0
T114	0	58	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8906528	1896	0	0
T18	108413	6	0	0
T38	0	78	0	0
T39	0	72	0	0
T51	0	40	0	0
T55	0	3	0	0
T65	0	3	0	0
T67	0	51	0	0
T81	0	501	0	0
T82	0	136	0	0
T84	0	42	0	0
T104	833	0	0	0
T105	2808	0	0	0
T106	18100	0	0	0
T107	2926	0	0	0
T108	27639	0	0	0
T109	3228	0	0	0
T110	15833	0	0	0
T111	7386	0	0	0
T112	9305	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8906528	1467	0	0
T18	108413	11	0	0
T38	0	36	0	0
T39	0	62	0	0
T40	0	20	0	0
T51	0	35	0	0
T55	0	2	0	0
T65	0	16	0	0
T81	0	408	0	0
T82	0	84	0	0
T84	0	21	0	0
T104	833	0	0	0
T105	2808	0	0	0
T106	18100	0	0	0
T107	2926	0	0	0
T108	27639	0	0	0
T109	3228	0	0	0
T110	15833	0	0	0
T111	7386	0	0	0
T112	9305	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8906528	1612	0	0
T18	108413	11	0	0
T38	0	38	0	0
T39	0	27	0	0
T40	0	3	0	0
T51	0	36	0	0
T54	0	7	0	0
T55	0	3	0	0
T81	0	488	0	0
T82	0	82	0	0
T84	0	42	0	0
T104	833	0	0	0
T105	2808	0	0	0
T106	18100	0	0	0
T107	2926	0	0	0
T108	27639	0	0	0
T109	3228	0	0	0
T110	15833	0	0	0
T111	7386	0	0	0
T112	9305	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8906528	3031	0	0
T18	108413	5	0	0
T38	0	154	0	0
T39	0	109	0	0
T40	0	11	0	0
T51	0	131	0	0
T65	0	53	0	0
T67	0	128	0	0
T81	0	480	0	0
T82	0	101	0	0
T84	0	28	0	0
T104	833	0	0	0
T105	2808	0	0	0
T106	18100	0	0	0
T107	2926	0	0	0
T108	27639	0	0	0
T109	3228	0	0	0
T110	15833	0	0	0
T111	7386	0	0	0
T112	9305	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8906528	1540	0	0
T18	108413	13	0	0
T38	0	36	0	0
T39	0	19	0	0
T40	0	12	0	0
T51	0	46	0	0
T54	0	8	0	0
T55	0	12	0	0
T81	0	401	0	0
T82	0	109	0	0
T84	0	39	0	0
T104	833	0	0	0
T105	2808	0	0	0
T106	18100	0	0	0
T107	2926	0	0	0
T108	27639	0	0	0
T109	3228	0	0	0
T110	15833	0	0	0
T111	7386	0	0	0
T112	9305	0	0	0