Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	8307498	20285	0	0
IoStatusRise_A	8307498	22562	0	0
MainStatusFall_A	8307498	20285	0	0
MainStatusRise_A	8307498	22562	0	0
UsbStatusFall_A	8307498	13541	0	0
UsbStatusRise_A	8307498	15571	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	20285	0	0
T1	45968	177	0	0
T2	15135	3	0	0
T3	14144	75	0	0
T4	45755	60	0	0
T7	1737	0	0	0
T8	2256	4	0	0
T9	3247	7	0	0
T10	2898	18	0	0
T11	7791	28	0	0
T12	9866	89	0	0
T21	0	5	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	22562	0	0
T1	45968	192	0	0
T2	15135	4	0	0
T3	14144	83	0	0
T4	45755	101	0	0
T7	1737	6	0	0
T8	2256	5	0	0
T9	3247	8	0	0
T10	2898	20	0	0
T11	7791	29	0	0
T12	9866	91	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	20285	0	0
T1	45968	177	0	0
T2	15135	3	0	0
T3	14144	75	0	0
T4	45755	60	0	0
T7	1737	0	0	0
T8	2256	4	0	0
T9	3247	7	0	0
T10	2898	18	0	0
T11	7791	28	0	0
T12	9866	89	0	0
T21	0	5	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	22562	0	0
T1	45968	192	0	0
T2	15135	4	0	0
T3	14144	83	0	0
T4	45755	101	0	0
T7	1737	6	0	0
T8	2256	5	0	0
T9	3247	8	0	0
T10	2898	20	0	0
T11	7791	29	0	0
T12	9866	91	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	13541	0	0
T1	45968	122	0	0
T2	15135	3	0	0
T3	14144	48	0	0
T4	45755	60	0	0
T7	1737	0	0	0
T8	2256	2	0	0
T9	3247	7	0	0
T10	2898	18	0	0
T11	7791	28	0	0
T12	9866	52	0	0
T21	0	5	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	15571	0	0
T1	45968	134	0	0
T2	15135	4	0	0
T3	14144	53	0	0
T4	45755	101	0	0
T7	1737	6	0	0
T8	2256	3	0	0
T9	3247	8	0	0
T10	2898	20	0	0
T11	7791	29	0	0
T12	9866	54	0	0