Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	8307498	22212	0	0
RomAllowCheckGoodState_A	8307498	22262	0	0
RomBlockActiveState_A	8307498	26411	0	0
RomBlockCheckGoodState_A	8307498	303899	0	0
RomIntgChkDisFalse_A	8307498	7948161	0	0
RomIntgChkDisTrue_A	8307498	118966	0	0
RstreqChkEsctimeout_A	8307498	1637	0	0
RstreqChkFsmterm_A	8307498	160	0	0
RstreqChkGlbesc_A	8307498	1641	0	0
RstreqChkMainpd_A	8307498	465179	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	22212	0	0
T1	45968	192	0	0
T2	15135	4	0	0
T3	14144	83	0	0
T4	45755	101	0	0
T7	1737	6	0	0
T8	2256	5	0	0
T9	3247	8	0	0
T10	2898	13	0	0
T11	7791	29	0	0
T12	9866	91	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	22262	0	0
T1	45968	192	0	0
T2	15135	4	0	0
T3	14144	83	0	0
T4	45755	101	0	0
T7	1737	6	0	0
T8	2256	5	0	0
T9	3247	8	0	0
T10	2898	14	0	0
T11	7791	29	0	0
T12	9866	91	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	26411	0	0
T9	3247	446	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	0	0	0
T21	1789	175	0	0
T22	21437	11	0	0
T25	7283	0	0	0
T26	2977	0	0	0
T30	3160	0	0	0
T35	3045	0	0	0
T60	0	17	0	0
T115	0	587	0	0
T116	0	17	0	0
T117	0	372	0	0
T118	0	281	0	0
T119	0	225	0	0
T120	0	14	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	303899	0	0
T1	45968	1077	0	0
T2	15135	0	0	0
T3	14144	437	0	0
T4	45755	0	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	233	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	617	0	0
T21	0	34	0	0
T22	0	1090	0	0
T25	0	115	0	0
T60	0	1428	0	0
T115	0	396	0	0
T121	0	4161	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	7948161	0	0
T1	45968	44791	0	0
T2	15135	15065	0	0
T3	14144	13500	0	0
T4	45755	39550	0	0
T7	1737	1295	0	0
T8	2256	2160	0	0
T9	3247	1879	0	0
T10	2898	1887	0	0
T11	7791	7723	0	0
T12	9866	9742	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	118966	0	0
T9	3247	1268	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	0	0	0
T21	1789	34	0	0
T22	21437	359	0	0
T25	7283	0	0	0
T26	2977	0	0	0
T30	3160	0	0	0
T35	3045	0	0	0
T60	0	931	0	0
T115	0	127	0	0
T117	0	973	0	0
T118	0	534	0	0
T122	0	2336	0	0
T123	0	1731	0	0
T124	0	13951	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	1637	0	0
T1	45968	12	0	0
T2	15135	1	0	0
T3	14144	11	0	0
T4	45755	20	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	2	0	0
T10	2898	6	0	0
T11	7791	11	0	0
T12	9866	0	0	0
T21	0	1	0	0
T27	0	6	0	0
T30	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	160	0	0
T4	45755	40	0	0
T5	0	20	0	0
T6	0	20	0	0
T8	2256	0	0	0
T9	3247	0	0	0
T10	2898	0	0	0
T11	7791	0	0	0
T12	9866	0	0	0
T21	1789	0	0	0
T22	21437	0	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	7283	0	0	0
T26	2977	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	1641	0	0
T1	45968	12	0	0
T2	15135	1	0	0
T3	14144	11	0	0
T4	45755	20	0	0
T7	1737	0	0	0
T8	2256	0	0	0
T9	3247	2	0	0
T10	2898	6	0	0
T11	7791	11	0	0
T12	9866	0	0	0
T21	0	1	0	0
T27	0	6	0	0
T30	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8307498	465179	0	0
T1	45968	1167	0	0
T2	15135	0	0	0
T3	14144	437	0	0
T4	45755	0	0	0
T7	1737	27	0	0
T8	2256	0	0	0
T9	3247	567	0	0
T10	2898	97	0	0
T11	7791	1199	0	0
T12	9866	869	0	0
T21	0	76	0	0
T22	0	1298	0	0
T25	0	439	0	0