Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30554

1

T2

58

T4

2

T5

12

auto[1]

28799

1

T2

42

T5

14

T6

48

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30122

1

T2

48

T4

2

T5

18

auto[1]

29231

1

T2

52

T5

8

T6

46

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29113

1

T2

60

T5

12

T6

48

auto[1]

30240

1

T2

40

T4

2

T5

14

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33721

1

T2

50

T4

1

T5

13

auto[1]

25632

1

T2

50

T4

1

T5

13

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28820

1

T2

50

T5

14

T6

66

auto[1]

30533

1

T2

50

T4

2

T5

12

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29964

1

T2

56

T4

2

T5

20

auto[1]

29389

1

T2

44

T5

6

T6

52

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1077

1

T2

1

T6

1

T8

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

829

1

T2

1

T6

1

T8

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1015

1

T2

1

T5

2

T6

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

779

1

T2

1

T5

2

T6

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1024

1

T2

4

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

791

1

T2

4

T6

1

T15

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1647

1

T2

3

T4

1

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1398

1

T2

3

T4

1

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1032

1

T2

1

T6

1

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

756

1

T2

1

T6

1

T8

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1023

1

T2

1

T5

1

T6

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

762

1

T2

1

T5

1

T6

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1071

1

T2

3

T6

1

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

829

1

T2

3

T6

1

T8

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1074

1

T2

2

T6

2

T8

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

797

1

T2

2

T6

2

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1002

1

T2

1

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

752

1

T2

1

T6

1

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

998

1

T2

3

T5

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

758

1

T2

3

T5

1

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1060

1

T2

3

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

817

1

T2

3

T6

1

T8

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1044

1

T5

1

T8

5

T15

15

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

808

1

T5

1

T8

2

T15

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1115

1

T2

2

T6

8

T8

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

835

1

T2

2

T6

8

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1031

1

T2

2

T6

2

T8

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

766

1

T2

2

T6

2

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1023

1

T2

2

T6

1

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

773

1

T2

2

T6

1

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1074

1

T7

1

T8

5

T44

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

794

1

T8

2

T44

2

T15

21

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1015

1

T2

1

T6

3

T8

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

749

1

T2

1

T6

3

T8

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1009

1

T2

2

T6

5

T8

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

753

1

T2

2

T6

5

T8

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1004

1

T2

1

T5

3

T7

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

784

1

T2

1

T5

3

T15

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

993

1

T2

2

T5

1

T6

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

758

1

T2

2

T5

1

T6

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1005

1

T2

2

T5

1

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

764

1

T2

2

T5

1

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1000

1

T6

1

T7

1

T8

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

761

1

T6

1

T8

1

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1050

1

T6

1

T7

1

T8

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

801

1

T6

1

T8

2

T15

17

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1021

1

T6

1

T7

1

T8

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

751

1

T6

1

T8

2

T15

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

970

1

T2

1

T5

1

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

737

1

T2

1

T5

1

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1030

1

T2

1

T6

1

T8

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

768

1

T2

1

T6

1

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1013

1

T2

3

T8

4

T15

14

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

759

1

T2

3

T8

3

T15

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1047

1

T2

1

T6

2

T7

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

776

1

T2

1

T6

2

T8

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1056

1

T2

5

T5

1

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

772

1

T2

5

T5

1

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1080

1

T2

1

T6

1

T8

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

821

1

T2

1

T6

1

T8

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1043

1

T6

1

T8

2

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

805

1

T6

1

T8

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1075

1

T2

1

T6

1

T8

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

829

1

T2

1

T6

1

T8

3