Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	485325	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183665

1

T1

22

T2

30

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	347396	1			T1	182		T2	182		T3	51
values[0x0]	160775	1			T1	27		T2	30		T3	31
values[0x1]	160819	1			T1	35		T2	32		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	384302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

284688

1

T1

74

T2

89

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2513	1			T1	1		T14	20		T76	1
valid_sources[0x01]	2436	1			T1	1		T7	1		T12	12
valid_sources[0x02]	2964	1			T1	4		T2	17		T14	15
valid_sources[0x03]	11505	1			T1	2		T2	1		T31	20
valid_sources[0x04]	2283	1			T14	21		T77	2		T170	4
valid_sources[0x05]	2145	1			T14	22		T25	4		T77	1
valid_sources[0x06]	2328	1			T1	1		T14	27		T25	1
valid_sources[0x07]	3811	1			T7	2		T29	1		T14	18
valid_sources[0x08]	3109	1			T1	1		T14	22		T76	1
valid_sources[0x09]	2693	1			T1	1		T10	1		T14	26
valid_sources[0x0a]	2261	1			T7	1		T14	16		T15	14
valid_sources[0x0b]	2904	1			T1	3		T4	9		T14	20
valid_sources[0x0c]	4020	1			T14	21		T25	7		T171	2
valid_sources[0x0d]	2731	1			T1	2		T14	20		T77	1
valid_sources[0x0e]	2215	1			T14	13		T25	5		T77	1
valid_sources[0x0f]	5935	1			T1	2		T2	6		T14	7
valid_sources[0x10]	2949	1			T1	2		T2	6		T12	12
valid_sources[0x11]	2597	1			T14	20		T15	4		T37	1
valid_sources[0x12]	2217	1			T12	14		T14	17		T25	2
valid_sources[0x13]	2854	1			T2	2		T4	3		T14	13
valid_sources[0x14]	2700	1			T14	15		T77	1		T24	2
valid_sources[0x15]	5382	1			T14	18		T171	6		T15	22
valid_sources[0x16]	2118	1			T4	1		T14	16		T77	1
valid_sources[0x17]	2286	1			T14	21		T23	30		T15	64
valid_sources[0x18]	2138	1			T1	3		T14	27		T15	11
valid_sources[0x19]	3399	1			T1	6		T2	2		T7	2
valid_sources[0x1a]	2081	1			T14	15		T171	1		T15	21
valid_sources[0x1b]	8622	1			T2	9		T29	13		T14	22
valid_sources[0x1c]	2509	1			T1	4		T12	12		T14	10
valid_sources[0x1d]	2123	1			T14	17		T77	1		T15	32
valid_sources[0x1e]	2204	1			T14	12		T171	3		T15	24
valid_sources[0x1f]	2117	1			T14	18		T172	3		T170	4
valid_sources[0x20]	2459	1			T1	1		T7	2		T29	1
valid_sources[0x21]	2541	1			T14	20		T24	1		T34	6
valid_sources[0x22]	2519	1			T1	1		T14	15		T171	1
valid_sources[0x23]	2304	1			T1	3		T8	2		T29	7
valid_sources[0x24]	3373	1			T12	12		T31	45		T14	24
valid_sources[0x25]	2536	1			T1	3		T10	1		T14	15
valid_sources[0x26]	2077	1			T1	2		T4	5		T7	1
valid_sources[0x27]	3393	1			T14	22		T171	8		T38	3
valid_sources[0x28]	2384	1			T2	5		T8	5		T14	20
valid_sources[0x29]	3780	1			T7	1		T14	23		T34	4
valid_sources[0x2a]	2345	1			T1	4		T2	5		T7	1
valid_sources[0x2b]	2248	1			T4	1		T7	1		T14	17
valid_sources[0x2c]	2236	1			T7	1		T14	21		T23	59
valid_sources[0x2d]	2654	1			T7	1		T29	6		T14	19
valid_sources[0x2e]	2329	1			T1	4		T2	5		T14	27
valid_sources[0x2f]	2133	1			T7	1		T14	22		T76	2
valid_sources[0x30]	2272	1			T14	19		T77	2		T34	13
valid_sources[0x31]	2326	1			T14	16		T24	1		T173	1
valid_sources[0x32]	2284	1			T29	2		T14	18		T76	1
valid_sources[0x33]	2222	1			T1	2		T14	26		T171	1
valid_sources[0x34]	2286	1			T2	8		T29	2		T14	16
valid_sources[0x35]	2468	1			T1	1		T14	14		T77	1
valid_sources[0x36]	2034	1			T14	17		T171	3		T15	11
valid_sources[0x37]	2228	1			T1	1		T29	9		T14	18
valid_sources[0x38]	2324	1			T14	26		T25	1		T76	1
valid_sources[0x39]	2502	1			T31	6		T14	19		T25	4
valid_sources[0x3a]	2396	1			T1	3		T29	5		T31	72
valid_sources[0x3b]	2100	1			T7	1		T14	22		T171	3
valid_sources[0x3c]	2120	1			T1	2		T14	11		T77	1
valid_sources[0x3d]	2218	1			T1	1		T2	5		T7	1
valid_sources[0x3e]	2273	1			T2	5		T10	1		T14	22
valid_sources[0x3f]	2214	1			T1	1		T4	4		T7	1
valid_sources[0x40]	2201	1			T1	2		T7	1		T14	17
valid_sources[0x41]	2408	1			T1	4		T14	13		T171	6
valid_sources[0x42]	2438	1			T1	3		T14	20		T171	2
valid_sources[0x43]	4090	1			T1	3		T2	3		T14	13
valid_sources[0x44]	2863	1			T29	8		T14	22		T25	1
valid_sources[0x45]	2695	1			T1	1		T2	3		T14	15
valid_sources[0x46]	2143	1			T12	13		T29	15		T14	26
valid_sources[0x47]	2511	1			T12	25		T14	13		T23	61
valid_sources[0x48]	2215	1			T1	3		T2	14		T14	18
valid_sources[0x49]	2289	1			T1	1		T14	20		T77	1
valid_sources[0x4a]	2103	1			T14	21		T25	1		T77	1
valid_sources[0x4b]	2260	1			T2	3		T14	17		T171	1
valid_sources[0x4c]	2240	1			T1	2		T29	5		T14	20
valid_sources[0x4d]	2260	1			T1	1		T4	3		T7	1
valid_sources[0x4e]	2247	1			T31	2		T14	17		T170	1
valid_sources[0x4f]	2233	1			T1	3		T14	26		T18	1
valid_sources[0x50]	2271	1			T1	4		T12	34		T14	14
valid_sources[0x51]	2271	1			T1	1		T14	22		T77	1
valid_sources[0x52]	2148	1			T7	1		T14	12		T23	25
valid_sources[0x53]	2387	1			T1	1		T14	16		T40	1
valid_sources[0x54]	2779	1			T14	13		T77	1		T171	1
valid_sources[0x55]	2015	1			T1	1		T4	1		T14	17
valid_sources[0x56]	4002	1			T14	14		T25	5		T77	1
valid_sources[0x57]	2189	1			T1	3		T7	1		T29	6
valid_sources[0x58]	2268	1			T29	1		T14	31		T77	1
valid_sources[0x59]	2633	1			T1	1		T14	18		T23	72
valid_sources[0x5a]	2957	1			T1	1		T2	4		T4	1
valid_sources[0x5b]	2613	1			T8	1		T14	15		T170	3
valid_sources[0x5c]	2982	1			T1	1		T14	11		T15	5
valid_sources[0x5d]	3028	1			T1	2		T30	22		T14	16
valid_sources[0x5e]	2566	1			T14	30		T40	11		T174	3
valid_sources[0x5f]	3309	1			T7	1		T14	23		T25	3
valid_sources[0x60]	2165	1			T2	7		T14	28		T77	1
valid_sources[0x61]	3817	1			T14	16		T24	1		T15	57
valid_sources[0x62]	2115	1			T14	20		T77	2		T76	1
valid_sources[0x63]	2128	1			T14	26		T11	1		T77	1
valid_sources[0x64]	2168	1			T14	17		T77	1		T171	1
valid_sources[0x65]	3267	1			T12	22		T14	17		T25	1
valid_sources[0x66]	2009	1			T1	1		T8	1		T14	19
valid_sources[0x67]	2239	1			T2	9		T14	24		T15	8
valid_sources[0x68]	2781	1			T2	5		T29	7		T14	16
valid_sources[0x69]	2135	1			T1	3		T14	11		T171	7
valid_sources[0x6a]	2196	1			T14	15		T15	15		T38	1
valid_sources[0x6b]	3104	1			T1	1		T7	1		T14	26
valid_sources[0x6c]	3173	1			T14	30		T24	1		T15	16
valid_sources[0x6d]	2248	1			T14	16		T15	3		T37	1
valid_sources[0x6e]	2086	1			T1	1		T2	6		T4	1
valid_sources[0x6f]	2238	1			T29	5		T14	13		T24	1
valid_sources[0x70]	2319	1			T7	1		T8	2		T14	12
valid_sources[0x71]	2436	1			T1	4		T14	12		T15	43
valid_sources[0x72]	3007	1			T29	5		T14	13		T171	1
valid_sources[0x73]	2314	1			T7	1		T14	23		T25	2
valid_sources[0x74]	2299	1			T1	1		T7	1		T14	17
valid_sources[0x75]	2222	1			T1	2		T5	1		T14	18
valid_sources[0x76]	2112	1			T10	1		T29	2		T14	26
valid_sources[0x77]	2127	1			T14	23		T77	1		T171	1
valid_sources[0x78]	2647	1			T1	2		T4	8		T14	25
valid_sources[0x79]	2265	1			T8	1		T12	12		T14	22
valid_sources[0x7a]	2516	1			T2	2		T14	13		T25	1
valid_sources[0x7b]	2286	1			T1	1		T14	18		T25	4
valid_sources[0x7c]	2339	1			T14	16		T23	33		T15	26
valid_sources[0x7d]	2969	1			T1	2		T14	23		T23	90
valid_sources[0x7e]	2451	1			T14	18		T25	1		T37	1
valid_sources[0x7f]	2446	1			T7	1		T14	19		T77	1
valid_sources[0x80]	2092	1			T2	2		T7	1		T14	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

91899

1

T1

11

T2

18

T3

12

values[0x0]

all_enables

biggest_size

59603

1

T1

7

T2

8

T3

13

values[0x1]

all_enables

biggest_size

32163

1

T1

4

T2

4

T3

6