Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T28,T30

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	21763774	5857	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	21763774	233691	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	21763774	9077951	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	21763774	233690	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	21763774	5857	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	21763774	233691	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	21763774	9077951	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	21763774	233690	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	5857	0	0
T7	2932	1	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	1	0	0
T13	1583	0	0	0
T14	0	16	0	0
T23	0	24	0	0
T28	1671	1	0	0
T29	14267	0	0	0
T30	1971	1	0	0
T31	5031	0	0	0
T32	0	23	0	0
T39	0	5	0	0
T75	0	1	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	233691	0	0
T7	2932	186	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	11	0	0
T13	1583	0	0	0
T14	0	508	0	0
T23	0	1458	0	0
T28	1671	110	0	0
T29	14267	0	0	0
T30	1971	123	0	0
T31	5031	0	0	0
T32	0	753	0	0
T39	0	52	0	0
T75	0	12	0	0
T76	0	10	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	9077951	0	0
T3	2887	1678	0	0
T4	2091	0	0	0
T5	15698	0	0	0
T6	5295	1456	0	0
T7	2932	142	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	0	22043	0	0
T13	1583	0	0	0
T14	0	49870	0	0
T28	1671	87	0	0
T29	0	8051	0	0
T30	0	106	0	0
T31	0	4429	0	0
T32	0	19627	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	233690	0	0
T7	2932	186	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	11	0	0
T13	1583	0	0	0
T14	0	508	0	0
T23	0	1458	0	0
T28	1671	110	0	0
T29	14267	0	0	0
T30	1971	123	0	0
T31	5031	0	0	0
T32	0	753	0	0
T39	0	52	0	0
T75	0	12	0	0
T76	0	10	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	5857	0	0
T7	2932	1	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	1	0	0
T13	1583	0	0	0
T14	0	16	0	0
T23	0	24	0	0
T28	1671	1	0	0
T29	14267	0	0	0
T30	1971	1	0	0
T31	5031	0	0	0
T32	0	23	0	0
T39	0	5	0	0
T75	0	1	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	233691	0	0
T7	2932	186	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	11	0	0
T13	1583	0	0	0
T14	0	508	0	0
T23	0	1458	0	0
T28	1671	110	0	0
T29	14267	0	0	0
T30	1971	123	0	0
T31	5031	0	0	0
T32	0	753	0	0
T39	0	52	0	0
T75	0	12	0	0
T76	0	10	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	9077951	0	0
T3	2887	1678	0	0
T4	2091	0	0	0
T5	15698	0	0	0
T6	5295	1456	0	0
T7	2932	142	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	0	22043	0	0
T13	1583	0	0	0
T14	0	49870	0	0
T28	1671	87	0	0
T29	0	8051	0	0
T30	0	106	0	0
T31	0	4429	0	0
T32	0	19627	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	233690	0	0
T7	2932	186	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	11	0	0
T13	1583	0	0	0
T14	0	508	0	0
T23	0	1458	0	0
T28	1671	110	0	0
T29	14267	0	0	0
T30	1971	123	0	0
T31	5031	0	0	0
T32	0	753	0	0
T39	0	52	0	0
T75	0	12	0	0
T76	0	10	0	0