Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22341164	15208	0	0
intr_enable_rd_A	22341164	29138	0	0
reset_en_rd_A	22341164	2012	0	0
reset_en_regwen_rd_A	22341164	1987	0	0
wake_info_capture_dis_rd_A	22341164	2014	0	0
wakeup_en_rd_A	22341164	2894	0	0
wakeup_en_regwen_rd_A	22341164	1865	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22341164	15208	0	0
T11	990	0	0	0
T14	135672	1	0	0
T16	992	0	0	0
T17	1101	0	0	0
T18	2363	0	0	0
T21	0	13	0	0
T22	0	8	0	0
T23	58057	0	0	0
T25	3127	0	0	0
T32	33853	0	0	0
T39	6198	0	0	0
T43	0	25	0	0
T77	2392	0	0	0
T80	0	12	0	0
T81	0	5	0	0
T126	0	13	0	0
T127	0	2	0	0
T128	0	4	0	0
T129	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22341164	29138	0	0
T1	3845	52	0	0
T2	7258	94	0	0
T3	2887	25	0	0
T4	2091	8	0	0
T5	15698	0	0	0
T6	5295	0	0	0
T7	2932	0	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	0	255	0	0
T24	0	12	0	0
T25	0	43	0	0
T34	0	59	0	0
T39	0	46	0	0
T130	0	18	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22341164	2012	0	0
T22	109836	7	0	0
T47	0	37	0	0
T64	0	35	0	0
T80	0	6	0	0
T82	0	8	0	0
T126	163791	0	0	0
T129	0	10	0	0
T131	0	28	0	0
T132	0	8	0	0
T133	0	12	0	0
T134	0	37	0	0
T135	2270	0	0	0
T136	5501	0	0	0
T137	56493	0	0	0
T138	15479	0	0	0
T139	7009	0	0	0
T140	1403	0	0	0
T141	3731	0	0	0
T142	255462	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22341164	1987	0	0
T22	109836	4	0	0
T47	0	15	0	0
T64	0	19	0	0
T80	0	10	0	0
T82	0	12	0	0
T119	0	18	0	0
T126	163791	0	0	0
T129	0	8	0	0
T131	0	15	0	0
T132	0	11	0	0
T133	0	17	0	0
T135	2270	0	0	0
T136	5501	0	0	0
T137	56493	0	0	0
T138	15479	0	0	0
T139	7009	0	0	0
T140	1403	0	0	0
T141	3731	0	0	0
T142	255462	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22341164	2014	0	0
T47	0	16	0	0
T64	0	19	0	0
T80	482882	12	0	0
T82	0	4	0	0
T119	0	20	0	0
T129	0	8	0	0
T131	0	9	0	0
T132	0	9	0	0
T133	0	9	0	0
T143	0	1	0	0
T144	1686	0	0	0
T145	2697	0	0	0
T146	4064	0	0	0
T147	10968	0	0	0
T148	15328	0	0	0
T149	6435	0	0	0
T150	3258	0	0	0
T151	2807	0	0	0
T152	3197	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22341164	2894	0	0
T22	109836	1	0	0
T47	0	23	0	0
T64	0	51	0	0
T80	0	6	0	0
T82	0	8	0	0
T126	163791	0	0	0
T129	0	9	0	0
T131	0	19	0	0
T132	0	29	0	0
T133	0	55	0	0
T134	0	17	0	0
T135	2270	0	0	0
T136	5501	0	0	0
T137	56493	0	0	0
T138	15479	0	0	0
T139	7009	0	0	0
T140	1403	0	0	0
T141	3731	0	0	0
T142	255462	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22341164	1865	0	0
T22	109836	9	0	0
T47	0	32	0	0
T64	0	25	0	0
T80	0	4	0	0
T82	0	2	0	0
T119	0	13	0	0
T126	163791	0	0	0
T129	0	6	0	0
T131	0	9	0	0
T132	0	13	0	0
T133	0	5	0	0
T135	2270	0	0	0
T136	5501	0	0	0
T137	56493	0	0	0
T138	15479	0	0	0
T139	7009	0	0	0
T140	1403	0	0	0
T141	3731	0	0	0
T142	255462	0	0	0