Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	21763774	56226	0	0
RomAllowCheckGoodState_A	21763774	56276	0	0
RomBlockActiveState_A	21763774	29128	0	0
RomBlockCheckGoodState_A	21763774	431830	0	0
RomIntgChkDisFalse_A	21763774	21078106	0	0
RomIntgChkDisTrue_A	21763774	180956	0	0
RstreqChkEsctimeout_A	21763774	4172	0	0
RstreqChkFsmterm_A	21763774	140	0	0
RstreqChkGlbesc_A	21763774	4174	0	0
RstreqChkMainpd_A	21763774	883662	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	56226	0	0
T1	3845	2	0	0
T2	7258	4	0	0
T3	2887	9	0	0
T4	2091	8	0	0
T5	15698	2	0	0
T6	5295	6	0	0
T7	2932	5	0	0
T8	1304	3	0	0
T9	15660	5	0	0
T10	12146	51	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	56276	0	0
T1	3845	2	0	0
T2	7258	4	0	0
T3	2887	9	0	0
T4	2091	8	0	0
T5	15698	2	0	0
T6	5295	6	0	0
T7	2932	5	0	0
T8	1304	3	0	0
T9	15660	5	0	0
T10	12146	51	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	29128	0	0
T4	2091	295	0	0
T5	15698	0	0	0
T6	5295	0	0	0
T7	2932	0	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	0	0	0
T13	1583	0	0	0
T24	0	549	0	0
T28	1671	0	0	0
T35	0	32	0	0
T37	0	136	0	0
T136	0	1353	0	0
T153	0	320	0	0
T154	0	754	0	0
T155	0	1408	0	0
T156	0	143	0	0
T157	0	6	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	431830	0	0
T4	2091	111	0	0
T5	15698	0	0	0
T6	5295	0	0	0
T7	2932	0	0	0
T8	1304	23	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	0	0	0
T13	1583	0	0	0
T14	0	780	0	0
T15	0	782	0	0
T23	0	4088	0	0
T24	0	373	0	0
T28	1671	0	0	0
T32	0	2306	0	0
T34	0	367	0	0
T35	0	1180	0	0
T39	0	274	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	21078106	0	0
T1	3845	3751	0	0
T2	7258	7191	0	0
T3	2887	2828	0	0
T4	2091	1852	0	0
T5	15698	15630	0	0
T6	5295	5245	0	0
T7	2932	2602	0	0
T8	1304	1246	0	0
T9	15660	15570	0	0
T10	12146	9045	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	180956	0	0
T4	2091	79	0	0
T5	15698	0	0	0
T6	5295	0	0	0
T7	2932	0	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	0	0	0
T13	1583	0	0	0
T23	0	1929	0	0
T24	0	218	0	0
T28	1671	0	0	0
T35	0	979	0	0
T37	0	37	0	0
T153	0	544	0	0
T154	0	1103	0	0
T155	0	1707	0	0
T158	0	1893	0	0
T159	0	2081	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	4172	0	0
T4	2091	3	0	0
T5	15698	1	0	0
T6	5295	0	0	0
T7	2932	0	0	0
T8	1304	0	0	0
T9	15660	1	0	0
T10	12146	10	0	0
T11	0	1	0	0
T12	42443	0	0	0
T13	1583	3	0	0
T14	0	45	0	0
T24	0	1	0	0
T25	0	8	0	0
T28	1671	0	0	0
T33	0	6	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	140	0	0
T10	12146	20	0	0
T12	42443	0	0	0
T13	1583	0	0	0
T14	135672	0	0	0
T16	992	0	0	0
T19	0	20	0	0
T20	0	40	0	0
T26	0	40	0	0
T27	0	20	0	0
T28	1671	0	0	0
T29	14267	0	0	0
T30	1971	0	0	0
T31	5031	0	0	0
T32	33853	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	4174	0	0
T4	2091	3	0	0
T5	15698	1	0	0
T6	5295	0	0	0
T7	2932	0	0	0
T8	1304	0	0	0
T9	15660	1	0	0
T10	12146	10	0	0
T11	0	1	0	0
T12	42443	0	0	0
T13	1583	3	0	0
T14	0	45	0	0
T24	0	1	0	0
T25	0	8	0	0
T28	1671	0	0	0
T33	0	6	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21763774	883662	0	0
T4	2091	233	0	0
T5	15698	0	0	0
T6	5295	0	0	0
T7	2932	0	0	0
T8	1304	0	0	0
T9	15660	0	0	0
T10	12146	0	0	0
T12	42443	0	0	0
T13	1583	0	0	0
T14	0	2023	0	0
T16	0	23	0	0
T17	0	12	0	0
T18	0	25	0	0
T23	0	6650	0	0
T24	0	179	0	0
T25	0	182	0	0
T28	1671	0	0	0
T32	0	2653	0	0
T33	0	104	0	0