Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29784

1

T3

30

T5

6

T6

6

auto[1]

28604

1

T3

30

T5

14

T6

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29906

1

T3

33

T5

6

T6

4

auto[1]

28482

1

T3

27

T5

14

T6

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28399

1

T3

32

T5

12

T6

2

auto[1]

29989

1

T3

28

T5

8

T6

6

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33551

1

T3

47

T5

10

T6

4

auto[1]

24837

1

T3

13

T5

10

T6

4

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28514

1

T3

28

T5

10

T6

2

auto[1]

29874

1

T3

32

T5

10

T6

6

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29650

1

T3

31

T5

4

T6

6

auto[1]

28738

1

T3

29

T5

16

T6

2

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1020

1

T3

4

T10

6

T20

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

748

1

T3

1

T10

4

T20

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1047

1

T3

2

T10

2

T14

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

744

1

T3

1

T10

1

T14

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1006

1

T3

2

T7

1

T10

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

748

1

T7

1

T10

3

T20

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1696

1

T3

1

T10

4

T20

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1417

1

T10

4

T20

1

T27

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1027

1

T3

2

T5

1

T10

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

759

1

T3

1

T5

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1030

1

T10

1

T20

1

T15

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

734

1

T10

1

T20

1

T14

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

986

1

T3

1

T7

1

T10

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

705

1

T7

1

T10

2

T20

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1063

1

T3

2

T6

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

801

1

T3

2

T6

1

T20

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1034

1

T10

2

T20

2

T14

14

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

758

1

T10

2

T20

2

T14

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

966

1

T10

3

T20

2

T15

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

724

1

T10

2

T20

2

T14

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

988

1

T3

1

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

714

1

T3

1

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1050

1

T3

3

T6

1

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

759

1

T6

1

T10

2

T20

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1036

1

T10

2

T20

1

T27

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

766

1

T10

2

T20

1

T27

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1044

1

T3

1

T5

1

T10

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

768

1

T3

1

T5

1

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1019

1

T3

3

T5

1

T10

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

777

1

T3

1

T5

1

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1077

1

T10

1

T20

2

T15

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

773

1

T10

1

T20

2

T14

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1061

1

T3

2

T10

1

T20

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

777

1

T10

1

T20

1

T14

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

978

1

T6

1

T7

1

T10

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

715

1

T6

1

T7

1

T10

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1035

1

T3

2

T10

2

T20

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

759

1

T10

1

T20

2

T14

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1054

1

T3

2

T10

3

T20

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

797

1

T10

1

T20

2

T27

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1024

1

T3

1

T5

1

T20

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

747

1

T5

1

T20

2

T14

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1032

1

T3

1

T10

3

T20

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

755

1

T10

1

T20

1

T14

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1056

1

T3

4

T10

1

T20

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

764

1

T20

4

T14

4

T72

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1054

1

T3

2

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

767

1

T5

1

T7

1

T10

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1014

1

T3

1

T5

1

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

751

1

T5

1

T10

2

T27

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1063

1

T3

3

T20

1

T14

14

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

795

1

T3

2

T20

1

T14

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1013

1

T5

1

T10

3

T20

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

738

1

T5

1

T10

2

T20

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

969

1

T3

2

T10

2

T20

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

712

1

T3

1

T10

1

T20

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1025

1

T3

2

T20

1

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

779

1

T3

2

T20

1

T14

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1033

1

T3

1

T5

1

T10

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

760

1

T5

1

T10

2

T20

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1015

1

T3

1

T5

1

T10

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

750

1

T5

1

T10

2

T14

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1036

1

T3

1

T5

1

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

776

1

T5

1

T7

1

T20

1