| T818 |
/workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3176002013 |
|
|
Mar 26 02:56:47 PM PDT 24 |
Mar 26 02:56:48 PM PDT 24 |
28197623 ps |
| T819 |
/workspace/coverage/default/13.pwrmgr_lowpower_invalid.1943653037 |
|
|
Mar 26 02:55:43 PM PDT 24 |
Mar 26 02:55:45 PM PDT 24 |
46650782 ps |
| T820 |
/workspace/coverage/default/23.pwrmgr_reset.1162382074 |
|
|
Mar 26 02:55:51 PM PDT 24 |
Mar 26 02:55:52 PM PDT 24 |
90754798 ps |
| T821 |
/workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2442239826 |
|
|
Mar 26 02:56:40 PM PDT 24 |
Mar 26 02:56:41 PM PDT 24 |
30506544 ps |
| T822 |
/workspace/coverage/default/22.pwrmgr_wakeup.2282979748 |
|
|
Mar 26 02:56:09 PM PDT 24 |
Mar 26 02:56:11 PM PDT 24 |
254823875 ps |
| T17 |
/workspace/coverage/default/1.pwrmgr_sec_cm.885310658 |
|
|
Mar 26 02:54:55 PM PDT 24 |
Mar 26 02:54:58 PM PDT 24 |
650493795 ps |
| T823 |
/workspace/coverage/default/47.pwrmgr_wakeup.3106285129 |
|
|
Mar 26 02:57:23 PM PDT 24 |
Mar 26 02:57:24 PM PDT 24 |
157309592 ps |
| T824 |
/workspace/coverage/default/45.pwrmgr_aborted_low_power.2679333296 |
|
|
Mar 26 02:56:54 PM PDT 24 |
Mar 26 02:56:55 PM PDT 24 |
60421210 ps |
| T825 |
/workspace/coverage/default/39.pwrmgr_smoke.1072022411 |
|
|
Mar 26 02:56:37 PM PDT 24 |
Mar 26 02:56:38 PM PDT 24 |
44490882 ps |
| T826 |
/workspace/coverage/default/44.pwrmgr_wakeup.2552899415 |
|
|
Mar 26 02:56:59 PM PDT 24 |
Mar 26 02:57:01 PM PDT 24 |
67147222 ps |
| T827 |
/workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3205175091 |
|
|
Mar 26 02:55:43 PM PDT 24 |
Mar 26 02:55:45 PM PDT 24 |
310187879 ps |
| T828 |
/workspace/coverage/default/44.pwrmgr_wakeup_reset.1219223499 |
|
|
Mar 26 02:57:06 PM PDT 24 |
Mar 26 02:57:08 PM PDT 24 |
137698397 ps |
| T829 |
/workspace/coverage/default/47.pwrmgr_reset_invalid.3180707859 |
|
|
Mar 26 02:57:16 PM PDT 24 |
Mar 26 02:57:17 PM PDT 24 |
163917839 ps |
| T830 |
/workspace/coverage/default/17.pwrmgr_glitch.1069170969 |
|
|
Mar 26 02:55:48 PM PDT 24 |
Mar 26 02:55:49 PM PDT 24 |
50963312 ps |
| T831 |
/workspace/coverage/default/44.pwrmgr_stress_all.3489667031 |
|
|
Mar 26 02:57:19 PM PDT 24 |
Mar 26 02:57:26 PM PDT 24 |
2277585614 ps |
| T832 |
/workspace/coverage/default/41.pwrmgr_aborted_low_power.885734928 |
|
|
Mar 26 02:56:40 PM PDT 24 |
Mar 26 02:56:41 PM PDT 24 |
156343527 ps |
| T833 |
/workspace/coverage/default/38.pwrmgr_glitch.1925113798 |
|
|
Mar 26 02:57:14 PM PDT 24 |
Mar 26 02:57:15 PM PDT 24 |
60248186 ps |
| T834 |
/workspace/coverage/default/47.pwrmgr_reset.2403384362 |
|
|
Mar 26 02:57:04 PM PDT 24 |
Mar 26 02:57:05 PM PDT 24 |
69393006 ps |
| T835 |
/workspace/coverage/default/12.pwrmgr_aborted_low_power.563332893 |
|
|
Mar 26 02:55:41 PM PDT 24 |
Mar 26 02:55:42 PM PDT 24 |
48683224 ps |
| T836 |
/workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2676463800 |
|
|
Mar 26 02:56:36 PM PDT 24 |
Mar 26 02:56:36 PM PDT 24 |
48311965 ps |
| T837 |
/workspace/coverage/default/17.pwrmgr_lowpower_invalid.4227158268 |
|
|
Mar 26 02:55:44 PM PDT 24 |
Mar 26 02:55:45 PM PDT 24 |
88619751 ps |
| T838 |
/workspace/coverage/default/10.pwrmgr_reset_invalid.34404324 |
|
|
Mar 26 02:55:37 PM PDT 24 |
Mar 26 02:55:38 PM PDT 24 |
100560049 ps |
| T839 |
/workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4102491707 |
|
|
Mar 26 02:56:26 PM PDT 24 |
Mar 26 02:56:29 PM PDT 24 |
1673101917 ps |
| T840 |
/workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2807726390 |
|
|
Mar 26 02:57:30 PM PDT 24 |
Mar 26 02:57:32 PM PDT 24 |
1169751699 ps |
| T841 |
/workspace/coverage/default/0.pwrmgr_lowpower_invalid.3006487472 |
|
|
Mar 26 02:55:11 PM PDT 24 |
Mar 26 02:55:12 PM PDT 24 |
51520428 ps |
| T842 |
/workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3150637203 |
|
|
Mar 26 02:56:10 PM PDT 24 |
Mar 26 02:56:11 PM PDT 24 |
144435954 ps |
| T843 |
/workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2378515814 |
|
|
Mar 26 02:56:24 PM PDT 24 |
Mar 26 02:56:25 PM PDT 24 |
31567749 ps |
| T844 |
/workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2040955582 |
|
|
Mar 26 02:56:39 PM PDT 24 |
Mar 26 02:56:40 PM PDT 24 |
167491030 ps |
| T845 |
/workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.123977736 |
|
|
Mar 26 02:56:41 PM PDT 24 |
Mar 26 02:56:43 PM PDT 24 |
1234714728 ps |
| T846 |
/workspace/coverage/default/18.pwrmgr_smoke.2494189020 |
|
|
Mar 26 02:55:42 PM PDT 24 |
Mar 26 02:55:43 PM PDT 24 |
28746297 ps |
| T847 |
/workspace/coverage/default/18.pwrmgr_escalation_timeout.3399955806 |
|
|
Mar 26 02:56:15 PM PDT 24 |
Mar 26 02:56:18 PM PDT 24 |
1016459878 ps |
| T848 |
/workspace/coverage/default/25.pwrmgr_aborted_low_power.1339668594 |
|
|
Mar 26 02:56:14 PM PDT 24 |
Mar 26 02:56:15 PM PDT 24 |
19043494 ps |
| T849 |
/workspace/coverage/default/15.pwrmgr_escalation_timeout.1891221270 |
|
|
Mar 26 02:55:46 PM PDT 24 |
Mar 26 02:55:47 PM PDT 24 |
312898285 ps |
| T850 |
/workspace/coverage/default/33.pwrmgr_reset.1691746320 |
|
|
Mar 26 02:56:36 PM PDT 24 |
Mar 26 02:56:37 PM PDT 24 |
54645030 ps |
| T851 |
/workspace/coverage/default/1.pwrmgr_global_esc.210491383 |
|
|
Mar 26 02:55:00 PM PDT 24 |
Mar 26 02:55:00 PM PDT 24 |
115206473 ps |
| T852 |
/workspace/coverage/default/16.pwrmgr_escalation_timeout.3814958423 |
|
|
Mar 26 02:55:42 PM PDT 24 |
Mar 26 02:55:44 PM PDT 24 |
314791944 ps |
| T853 |
/workspace/coverage/default/8.pwrmgr_wakeup.2702054626 |
|
|
Mar 26 02:55:12 PM PDT 24 |
Mar 26 02:55:13 PM PDT 24 |
270547395 ps |
| T854 |
/workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.755963549 |
|
|
Mar 26 02:55:21 PM PDT 24 |
Mar 26 02:55:24 PM PDT 24 |
1077655624 ps |
| T855 |
/workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.55147092 |
|
|
Mar 26 02:56:31 PM PDT 24 |
Mar 26 02:56:32 PM PDT 24 |
105847813 ps |
| T856 |
/workspace/coverage/default/1.pwrmgr_wakeup_reset.4163906669 |
|
|
Mar 26 02:55:02 PM PDT 24 |
Mar 26 02:55:08 PM PDT 24 |
268460961 ps |
| T857 |
/workspace/coverage/default/45.pwrmgr_reset.4283837846 |
|
|
Mar 26 02:57:14 PM PDT 24 |
Mar 26 02:57:16 PM PDT 24 |
85822380 ps |
| T858 |
/workspace/coverage/default/42.pwrmgr_escalation_timeout.145223875 |
|
|
Mar 26 02:57:10 PM PDT 24 |
Mar 26 02:57:12 PM PDT 24 |
159496884 ps |
| T859 |
/workspace/coverage/default/25.pwrmgr_smoke.1502656886 |
|
|
Mar 26 02:56:13 PM PDT 24 |
Mar 26 02:56:15 PM PDT 24 |
57926105 ps |
| T860 |
/workspace/coverage/default/14.pwrmgr_lowpower_invalid.1475588015 |
|
|
Mar 26 02:55:43 PM PDT 24 |
Mar 26 02:55:43 PM PDT 24 |
53075451 ps |
| T861 |
/workspace/coverage/default/14.pwrmgr_wakeup_reset.3551586640 |
|
|
Mar 26 02:55:43 PM PDT 24 |
Mar 26 02:55:45 PM PDT 24 |
245724214 ps |
| T862 |
/workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.3117822389 |
|
|
Mar 26 02:55:49 PM PDT 24 |
Mar 26 02:55:50 PM PDT 24 |
59894880 ps |
| T863 |
/workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.3847020577 |
|
|
Mar 26 02:56:36 PM PDT 24 |
Mar 26 02:56:37 PM PDT 24 |
137553833 ps |
| T864 |
/workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1090356314 |
|
|
Mar 26 02:55:42 PM PDT 24 |
Mar 26 02:55:43 PM PDT 24 |
121956261 ps |
| T865 |
/workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3611632328 |
|
|
Mar 26 02:55:03 PM PDT 24 |
Mar 26 02:55:04 PM PDT 24 |
117749475 ps |
| T178 |
/workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.1076850964 |
|
|
Mar 26 02:57:03 PM PDT 24 |
Mar 26 02:57:04 PM PDT 24 |
84421089 ps |
| T866 |
/workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.3918741691 |
|
|
Mar 26 02:56:49 PM PDT 24 |
Mar 26 02:56:50 PM PDT 24 |
313003855 ps |
| T867 |
/workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.1491351947 |
|
|
Mar 26 02:55:42 PM PDT 24 |
Mar 26 02:55:44 PM PDT 24 |
62012214 ps |
| T868 |
/workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1206427922 |
|
|
Mar 26 02:56:44 PM PDT 24 |
Mar 26 02:56:47 PM PDT 24 |
923807947 ps |
| T869 |
/workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.1094675988 |
|
|
Mar 26 02:56:00 PM PDT 24 |
Mar 26 02:56:01 PM PDT 24 |
39631336 ps |
| T870 |
/workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.260904587 |
|
|
Mar 26 02:56:38 PM PDT 24 |
Mar 26 02:56:42 PM PDT 24 |
803079951 ps |
| T871 |
/workspace/coverage/default/27.pwrmgr_stress_all.4072628060 |
|
|
Mar 26 02:56:31 PM PDT 24 |
Mar 26 02:56:34 PM PDT 24 |
338968150 ps |
| T872 |
/workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.4008643349 |
|
|
Mar 26 02:56:39 PM PDT 24 |
Mar 26 02:56:41 PM PDT 24 |
234672003 ps |
| T873 |
/workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.897689530 |
|
|
Mar 26 02:56:21 PM PDT 24 |
Mar 26 02:56:22 PM PDT 24 |
86130395 ps |
| T874 |
/workspace/coverage/default/31.pwrmgr_wakeup_reset.820259734 |
|
|
Mar 26 02:56:35 PM PDT 24 |
Mar 26 02:56:35 PM PDT 24 |
182538752 ps |
| T875 |
/workspace/coverage/default/15.pwrmgr_smoke.2182427180 |
|
|
Mar 26 02:55:42 PM PDT 24 |
Mar 26 02:55:43 PM PDT 24 |
31672932 ps |
| T876 |
/workspace/coverage/default/0.pwrmgr_stress_all.2301114500 |
|
|
Mar 26 02:54:54 PM PDT 24 |
Mar 26 02:54:58 PM PDT 24 |
1281468143 ps |
| T877 |
/workspace/coverage/default/43.pwrmgr_glitch.406175773 |
|
|
Mar 26 02:56:56 PM PDT 24 |
Mar 26 02:56:57 PM PDT 24 |
60600482 ps |
| T878 |
/workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2767038984 |
|
|
Mar 26 02:56:38 PM PDT 24 |
Mar 26 02:56:39 PM PDT 24 |
474245224 ps |
| T879 |
/workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.981992620 |
|
|
Mar 26 02:56:22 PM PDT 24 |
Mar 26 02:56:34 PM PDT 24 |
2925911006 ps |
| T880 |
/workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.944240516 |
|
|
Mar 26 02:56:37 PM PDT 24 |
Mar 26 02:56:47 PM PDT 24 |
7948874484 ps |
| T881 |
/workspace/coverage/default/31.pwrmgr_stress_all.4288488119 |
|
|
Mar 26 02:56:34 PM PDT 24 |
Mar 26 02:56:37 PM PDT 24 |
1547817629 ps |
| T882 |
/workspace/coverage/default/34.pwrmgr_wakeup.3321947911 |
|
|
Mar 26 02:56:41 PM PDT 24 |
Mar 26 02:56:42 PM PDT 24 |
296057178 ps |
| T883 |
/workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3364861636 |
|
|
Mar 26 02:56:01 PM PDT 24 |
Mar 26 02:56:04 PM PDT 24 |
1275635769 ps |
| T884 |
/workspace/coverage/default/44.pwrmgr_escalation_timeout.3079335901 |
|
|
Mar 26 02:56:54 PM PDT 24 |
Mar 26 02:56:55 PM PDT 24 |
308184340 ps |
| T885 |
/workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3503019419 |
|
|
Mar 26 02:54:55 PM PDT 24 |
Mar 26 02:54:56 PM PDT 24 |
38435399 ps |
| T886 |
/workspace/coverage/default/28.pwrmgr_smoke.1825201314 |
|
|
Mar 26 02:56:33 PM PDT 24 |
Mar 26 02:56:34 PM PDT 24 |
33156450 ps |
| T887 |
/workspace/coverage/default/42.pwrmgr_reset_invalid.2751128 |
|
|
Mar 26 02:56:58 PM PDT 24 |
Mar 26 02:56:59 PM PDT 24 |
127122296 ps |
| T888 |
/workspace/coverage/default/41.pwrmgr_global_esc.2418799310 |
|
|
Mar 26 02:56:44 PM PDT 24 |
Mar 26 02:56:45 PM PDT 24 |
123378702 ps |
| T889 |
/workspace/coverage/default/24.pwrmgr_reset.1127879852 |
|
|
Mar 26 02:56:17 PM PDT 24 |
Mar 26 02:56:19 PM PDT 24 |
48583444 ps |
| T890 |
/workspace/coverage/default/28.pwrmgr_escalation_timeout.2983088022 |
|
|
Mar 26 02:56:28 PM PDT 24 |
Mar 26 02:56:30 PM PDT 24 |
311933529 ps |
| T891 |
/workspace/coverage/default/48.pwrmgr_wakeup.3620375069 |
|
|
Mar 26 02:57:14 PM PDT 24 |
Mar 26 02:57:15 PM PDT 24 |
68692048 ps |
| T892 |
/workspace/coverage/default/11.pwrmgr_wakeup.1884559248 |
|
|
Mar 26 02:55:43 PM PDT 24 |
Mar 26 02:55:44 PM PDT 24 |
217076625 ps |
| T182 |
/workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3348716255 |
|
|
Mar 26 02:57:04 PM PDT 24 |
Mar 26 02:57:05 PM PDT 24 |
57775016 ps |
| T893 |
/workspace/coverage/default/36.pwrmgr_stress_all.3181510145 |
|
|
Mar 26 02:56:46 PM PDT 24 |
Mar 26 02:56:48 PM PDT 24 |
819123898 ps |
| T894 |
/workspace/coverage/default/26.pwrmgr_stress_all.3538494319 |
|
|
Mar 26 02:56:12 PM PDT 24 |
Mar 26 02:56:17 PM PDT 24 |
1643621768 ps |
| T895 |
/workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3568679176 |
|
|
Mar 26 02:56:51 PM PDT 24 |
Mar 26 02:56:52 PM PDT 24 |
31683575 ps |
| T896 |
/workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3005913473 |
|
|
Mar 26 02:56:19 PM PDT 24 |
Mar 26 02:56:21 PM PDT 24 |
1095660590 ps |
| T897 |
/workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.2098498668 |
|
|
Mar 26 02:56:01 PM PDT 24 |
Mar 26 02:56:03 PM PDT 24 |
190229643 ps |
| T898 |
/workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.726558904 |
|
|
Mar 26 02:56:32 PM PDT 24 |
Mar 26 02:56:33 PM PDT 24 |
94276458 ps |
| T899 |
/workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1273412898 |
|
|
Mar 26 02:57:07 PM PDT 24 |
Mar 26 02:57:08 PM PDT 24 |
172104259 ps |
| T900 |
/workspace/coverage/default/36.pwrmgr_global_esc.332595511 |
|
|
Mar 26 02:56:33 PM PDT 24 |
Mar 26 02:56:34 PM PDT 24 |
34897000 ps |
| T901 |
/workspace/coverage/default/48.pwrmgr_global_esc.759644609 |
|
|
Mar 26 02:57:17 PM PDT 24 |
Mar 26 02:57:18 PM PDT 24 |
62766505 ps |
| T902 |
/workspace/coverage/default/2.pwrmgr_global_esc.771297864 |
|
|
Mar 26 02:55:04 PM PDT 24 |
Mar 26 02:55:04 PM PDT 24 |
36278553 ps |
| T903 |
/workspace/coverage/default/14.pwrmgr_wakeup.664198390 |
|
|
Mar 26 02:55:48 PM PDT 24 |
Mar 26 02:55:49 PM PDT 24 |
291644964 ps |
| T904 |
/workspace/coverage/default/4.pwrmgr_escalation_timeout.679683257 |
|
|
Mar 26 02:55:21 PM PDT 24 |
Mar 26 02:55:22 PM PDT 24 |
325549655 ps |
| T905 |
/workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3535342104 |
|
|
Mar 26 02:56:12 PM PDT 24 |
Mar 26 02:56:13 PM PDT 24 |
27905283 ps |
| T906 |
/workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.647188391 |
|
|
Mar 26 02:57:15 PM PDT 24 |
Mar 26 02:57:16 PM PDT 24 |
110640736 ps |
| T907 |
/workspace/coverage/default/21.pwrmgr_wakeup_reset.2158850189 |
|
|
Mar 26 02:55:48 PM PDT 24 |
Mar 26 02:55:50 PM PDT 24 |
236063822 ps |
| T908 |
/workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.157049068 |
|
|
Mar 26 02:56:20 PM PDT 24 |
Mar 26 02:56:21 PM PDT 24 |
135423992 ps |
| T909 |
/workspace/coverage/default/0.pwrmgr_wakeup_reset.2094691029 |
|
|
Mar 26 02:54:49 PM PDT 24 |
Mar 26 02:54:50 PM PDT 24 |
300546812 ps |
| T910 |
/workspace/coverage/default/43.pwrmgr_escalation_timeout.2958379707 |
|
|
Mar 26 02:57:01 PM PDT 24 |
Mar 26 02:57:02 PM PDT 24 |
631770406 ps |
| T911 |
/workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.2919578047 |
|
|
Mar 26 02:55:02 PM PDT 24 |
Mar 26 02:55:03 PM PDT 24 |
117488851 ps |
| T912 |
/workspace/coverage/default/6.pwrmgr_stress_all.2106507748 |
|
|
Mar 26 02:55:18 PM PDT 24 |
Mar 26 02:55:21 PM PDT 24 |
637852547 ps |
| T913 |
/workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1645206915 |
|
|
Mar 26 02:56:37 PM PDT 24 |
Mar 26 02:56:38 PM PDT 24 |
78504667 ps |
| T914 |
/workspace/coverage/default/1.pwrmgr_reset_invalid.1559981347 |
|
|
Mar 26 02:54:58 PM PDT 24 |
Mar 26 02:54:59 PM PDT 24 |
169636067 ps |
| T915 |
/workspace/coverage/default/27.pwrmgr_smoke.3732859524 |
|
|
Mar 26 02:56:07 PM PDT 24 |
Mar 26 02:56:08 PM PDT 24 |
31414595 ps |
| T916 |
/workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.879971977 |
|
|
Mar 26 02:57:04 PM PDT 24 |
Mar 26 02:57:05 PM PDT 24 |
28700483 ps |
| T917 |
/workspace/coverage/default/36.pwrmgr_smoke.4097201367 |
|
|
Mar 26 02:56:38 PM PDT 24 |
Mar 26 02:56:39 PM PDT 24 |
33692930 ps |
| T918 |
/workspace/coverage/default/32.pwrmgr_wakeup.3057215861 |
|
|
Mar 26 02:56:43 PM PDT 24 |
Mar 26 02:56:45 PM PDT 24 |
403167973 ps |
| T919 |
/workspace/coverage/default/11.pwrmgr_smoke.3327831548 |
|
|
Mar 26 02:55:40 PM PDT 24 |
Mar 26 02:55:41 PM PDT 24 |
78564599 ps |
| T920 |
/workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.3100349973 |
|
|
Mar 26 02:57:09 PM PDT 24 |
Mar 26 02:57:10 PM PDT 24 |
355735582 ps |
| T921 |
/workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.2713292545 |
|
|
Mar 26 02:55:46 PM PDT 24 |
Mar 26 02:55:55 PM PDT 24 |
2700289209 ps |
| T922 |
/workspace/coverage/default/44.pwrmgr_glitch.3267752235 |
|
|
Mar 26 02:57:14 PM PDT 24 |
Mar 26 02:57:15 PM PDT 24 |
29788792 ps |
| T923 |
/workspace/coverage/default/48.pwrmgr_wakeup_reset.1000677953 |
|
|
Mar 26 02:57:14 PM PDT 24 |
Mar 26 02:57:15 PM PDT 24 |
187683935 ps |
| T924 |
/workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2973274910 |
|
|
Mar 26 02:54:51 PM PDT 24 |
Mar 26 02:54:52 PM PDT 24 |
89475466 ps |
| T925 |
/workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.3923539410 |
|
|
Mar 26 02:55:44 PM PDT 24 |
Mar 26 02:56:00 PM PDT 24 |
11354481148 ps |
| T926 |
/workspace/coverage/default/6.pwrmgr_wakeup_reset.375247095 |
|
|
Mar 26 02:55:36 PM PDT 24 |
Mar 26 02:55:37 PM PDT 24 |
204119516 ps |
| T25 |
/workspace/coverage/default/0.pwrmgr_sec_cm.2808295247 |
|
|
Mar 26 02:54:57 PM PDT 24 |
Mar 26 02:54:59 PM PDT 24 |
663281817 ps |
| T927 |
/workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2434247393 |
|
|
Mar 26 02:55:47 PM PDT 24 |
Mar 26 02:55:51 PM PDT 24 |
825360227 ps |
| T928 |
/workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.4173589916 |
|
|
Mar 26 02:56:39 PM PDT 24 |
Mar 26 02:56:48 PM PDT 24 |
6167462015 ps |
| T929 |
/workspace/coverage/default/39.pwrmgr_wakeup.2403263561 |
|
|
Mar 26 02:56:43 PM PDT 24 |
Mar 26 02:56:44 PM PDT 24 |
71265158 ps |
| T930 |
/workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2538159435 |
|
|
Mar 26 02:55:47 PM PDT 24 |
Mar 26 02:55:48 PM PDT 24 |
67191985 ps |
| T931 |
/workspace/coverage/default/18.pwrmgr_aborted_low_power.2587462307 |
|
|
Mar 26 02:55:47 PM PDT 24 |
Mar 26 02:55:48 PM PDT 24 |
30921797 ps |
| T77 |
/workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.42849735 |
|
|
Mar 26 02:55:32 PM PDT 24 |
Mar 26 02:55:49 PM PDT 24 |
14066668362 ps |
| T932 |
/workspace/coverage/default/40.pwrmgr_global_esc.1128774 |
|
|
Mar 26 02:56:37 PM PDT 24 |
Mar 26 02:56:38 PM PDT 24 |
47538493 ps |
| T933 |
/workspace/coverage/default/13.pwrmgr_wakeup.3722806819 |
|
|
Mar 26 02:55:45 PM PDT 24 |
Mar 26 02:55:47 PM PDT 24 |
251010697 ps |
| T934 |
/workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.2268745328 |
|
|
Mar 26 02:55:52 PM PDT 24 |
Mar 26 02:55:53 PM PDT 24 |
101064267 ps |
| T935 |
/workspace/coverage/default/42.pwrmgr_reset.2596651888 |
|
|
Mar 26 02:56:35 PM PDT 24 |
Mar 26 02:56:36 PM PDT 24 |
58544958 ps |
| T145 |
/workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.1862528713 |
|
|
Mar 26 02:56:56 PM PDT 24 |
Mar 26 02:57:20 PM PDT 24 |
18452291087 ps |
| T936 |
/workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2090708462 |
|
|
Mar 26 02:56:54 PM PDT 24 |
Mar 26 02:56:57 PM PDT 24 |
974100427 ps |
| T937 |
/workspace/coverage/default/34.pwrmgr_global_esc.2853601735 |
|
|
Mar 26 02:56:36 PM PDT 24 |
Mar 26 02:56:36 PM PDT 24 |
78486111 ps |
| T938 |
/workspace/coverage/default/10.pwrmgr_lowpower_invalid.1298061599 |
|
|
Mar 26 02:55:45 PM PDT 24 |
Mar 26 02:55:46 PM PDT 24 |
44114191 ps |
| T939 |
/workspace/coverage/default/18.pwrmgr_stress_all.2070156425 |
|
|
Mar 26 02:55:47 PM PDT 24 |
Mar 26 02:55:48 PM PDT 24 |
701548432 ps |
| T940 |
/workspace/coverage/default/6.pwrmgr_smoke.548803338 |
|
|
Mar 26 02:55:14 PM PDT 24 |
Mar 26 02:55:14 PM PDT 24 |
30679169 ps |
| T179 |
/workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.1866069894 |
|
|
Mar 26 02:57:09 PM PDT 24 |
Mar 26 02:57:10 PM PDT 24 |
73721442 ps |
| T941 |
/workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2138172195 |
|
|
Mar 26 02:57:14 PM PDT 24 |
Mar 26 02:57:16 PM PDT 24 |
932865414 ps |
| T942 |
/workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.2400019646 |
|
|
Mar 26 02:56:57 PM PDT 24 |
Mar 26 02:56:58 PM PDT 24 |
195930480 ps |
| T943 |
/workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.1207539495 |
|
|
Mar 26 02:56:56 PM PDT 24 |
Mar 26 02:56:57 PM PDT 24 |
96702076 ps |
| T944 |
/workspace/coverage/default/38.pwrmgr_escalation_timeout.2896319427 |
|
|
Mar 26 02:56:40 PM PDT 24 |
Mar 26 02:56:41 PM PDT 24 |
326687492 ps |
| T945 |
/workspace/coverage/default/25.pwrmgr_lowpower_invalid.2196332627 |
|
|
Mar 26 02:56:04 PM PDT 24 |
Mar 26 02:56:05 PM PDT 24 |
83163056 ps |
| T946 |
/workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3558477672 |
|
|
Mar 26 02:55:45 PM PDT 24 |
Mar 26 02:55:47 PM PDT 24 |
1165688913 ps |
| T947 |
/workspace/coverage/default/24.pwrmgr_smoke.2042572035 |
|
|
Mar 26 02:56:05 PM PDT 24 |
Mar 26 02:56:05 PM PDT 24 |
32897236 ps |
| T948 |
/workspace/coverage/default/31.pwrmgr_global_esc.1776246649 |
|
|
Mar 26 02:56:43 PM PDT 24 |
Mar 26 02:56:44 PM PDT 24 |
31002185 ps |
| T949 |
/workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3334509712 |
|
|
Mar 26 02:54:58 PM PDT 24 |
Mar 26 02:55:10 PM PDT 24 |
3859377788 ps |
| T26 |
/workspace/coverage/default/3.pwrmgr_sec_cm.2219416148 |
|
|
Mar 26 02:54:54 PM PDT 24 |
Mar 26 02:54:55 PM PDT 24 |
1333035037 ps |
| T950 |
/workspace/coverage/default/23.pwrmgr_wakeup_reset.2217210002 |
|
|
Mar 26 02:56:12 PM PDT 24 |
Mar 26 02:56:14 PM PDT 24 |
282921668 ps |
| T951 |
/workspace/coverage/default/42.pwrmgr_stress_all.3056224639 |
|
|
Mar 26 02:57:05 PM PDT 24 |
Mar 26 02:57:10 PM PDT 24 |
989578917 ps |
| T952 |
/workspace/coverage/default/37.pwrmgr_glitch.1729418704 |
|
|
Mar 26 02:56:43 PM PDT 24 |
Mar 26 02:56:43 PM PDT 24 |
57315277 ps |
| T953 |
/workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.3149105466 |
|
|
Mar 26 02:54:59 PM PDT 24 |
Mar 26 02:55:06 PM PDT 24 |
258101313 ps |
| T954 |
/workspace/coverage/default/19.pwrmgr_aborted_low_power.2946884135 |
|
|
Mar 26 02:55:45 PM PDT 24 |
Mar 26 02:55:46 PM PDT 24 |
90202712 ps |
| T955 |
/workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2124237987 |
|
|
Mar 26 02:55:47 PM PDT 24 |
Mar 26 02:55:48 PM PDT 24 |
31552291 ps |
| T956 |
/workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.556462321 |
|
|
Mar 26 02:56:39 PM PDT 24 |
Mar 26 02:56:41 PM PDT 24 |
1104583978 ps |
| T957 |
/workspace/coverage/default/40.pwrmgr_glitch.2366821998 |
|
|
Mar 26 02:56:43 PM PDT 24 |
Mar 26 02:56:44 PM PDT 24 |
29684590 ps |
| T958 |
/workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2058534496 |
|
|
Mar 26 02:55:42 PM PDT 24 |
Mar 26 02:55:44 PM PDT 24 |
92126943 ps |
| T959 |
/workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.102671499 |
|
|
Mar 26 02:56:54 PM PDT 24 |
Mar 26 02:56:55 PM PDT 24 |
65757872 ps |
| T960 |
/workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4050252114 |
|
|
Mar 26 02:55:15 PM PDT 24 |
Mar 26 02:55:17 PM PDT 24 |
776507117 ps |
| T961 |
/workspace/coverage/default/27.pwrmgr_glitch.973050675 |
|
|
Mar 26 02:56:24 PM PDT 24 |
Mar 26 02:56:24 PM PDT 24 |
62544947 ps |
| T962 |
/workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1840175556 |
|
|
Mar 26 02:56:20 PM PDT 24 |
Mar 26 02:56:22 PM PDT 24 |
876478500 ps |
| T963 |
/workspace/coverage/default/9.pwrmgr_reset_invalid.607316846 |
|
|
Mar 26 02:55:29 PM PDT 24 |
Mar 26 02:55:30 PM PDT 24 |
100311426 ps |
| T78 |
/workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.2396232556 |
|
|
Mar 26 02:56:14 PM PDT 24 |
Mar 26 02:56:35 PM PDT 24 |
14893014996 ps |
| T964 |
/workspace/coverage/default/12.pwrmgr_wakeup_reset.3112628200 |
|
|
Mar 26 02:55:42 PM PDT 24 |
Mar 26 02:55:44 PM PDT 24 |
91434836 ps |
| T965 |
/workspace/coverage/default/28.pwrmgr_reset.3356825920 |
|
|
Mar 26 02:56:16 PM PDT 24 |
Mar 26 02:56:18 PM PDT 24 |
302684369 ps |
| T966 |
/workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3087911462 |
|
|
Mar 26 02:56:18 PM PDT 24 |
Mar 26 02:56:21 PM PDT 24 |
825019634 ps |
| T967 |
/workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.136182910 |
|
|
Mar 26 02:56:02 PM PDT 24 |
Mar 26 02:56:03 PM PDT 24 |
35178508 ps |
| T968 |
/workspace/coverage/default/42.pwrmgr_global_esc.2516725933 |
|
|
Mar 26 02:57:03 PM PDT 24 |
Mar 26 02:57:04 PM PDT 24 |
43557591 ps |
| T969 |
/workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3965824486 |
|
|
Mar 26 02:55:24 PM PDT 24 |
Mar 26 02:55:24 PM PDT 24 |
29003963 ps |
| T970 |
/workspace/coverage/default/29.pwrmgr_wakeup.1239316105 |
|
|
Mar 26 02:56:22 PM PDT 24 |
Mar 26 02:56:23 PM PDT 24 |
172221154 ps |
| T971 |
/workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.2308127638 |
|
|
Mar 26 02:55:06 PM PDT 24 |
Mar 26 02:55:07 PM PDT 24 |
176120044 ps |
| T972 |
/workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1470053981 |
|
|
Mar 26 02:55:11 PM PDT 24 |
Mar 26 02:55:13 PM PDT 24 |
1200509751 ps |
| T973 |
/workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1464957576 |
|
|
Mar 26 02:55:37 PM PDT 24 |
Mar 26 02:55:39 PM PDT 24 |
213543953 ps |
| T974 |
/workspace/coverage/default/31.pwrmgr_lowpower_invalid.1305663617 |
|
|
Mar 26 02:56:45 PM PDT 24 |
Mar 26 02:56:46 PM PDT 24 |
52022770 ps |
| T975 |
/workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1238952146 |
|
|
Mar 26 02:55:40 PM PDT 24 |
Mar 26 02:55:43 PM PDT 24 |
1066491400 ps |
| T976 |
/workspace/coverage/default/19.pwrmgr_global_esc.331098157 |
|
|
Mar 26 02:55:57 PM PDT 24 |
Mar 26 02:55:58 PM PDT 24 |
37299952 ps |
| T977 |
/workspace/coverage/default/25.pwrmgr_stress_all.3555308664 |
|
|
Mar 26 02:56:17 PM PDT 24 |
Mar 26 02:56:22 PM PDT 24 |
1668883882 ps |
| T978 |
/workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.936773340 |
|
|
Mar 26 02:55:43 PM PDT 24 |
Mar 26 02:55:44 PM PDT 24 |
65043948 ps |
| T979 |
/workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.3873089129 |
|
|
Mar 26 02:57:06 PM PDT 24 |
Mar 26 02:57:08 PM PDT 24 |
318261580 ps |
| T980 |
/workspace/coverage/default/18.pwrmgr_glitch.2395336092 |
|
|
Mar 26 02:56:08 PM PDT 24 |
Mar 26 02:56:09 PM PDT 24 |
68342034 ps |
| T981 |
/workspace/coverage/default/29.pwrmgr_aborted_low_power.4138053935 |
|
|
Mar 26 02:56:19 PM PDT 24 |
Mar 26 02:56:21 PM PDT 24 |
46433965 ps |
| T982 |
/workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1675775486 |
|
|
Mar 26 02:55:52 PM PDT 24 |
Mar 26 02:55:53 PM PDT 24 |
385791745 ps |
| T983 |
/workspace/coverage/default/37.pwrmgr_reset.1658072101 |
|
|
Mar 26 02:56:53 PM PDT 24 |
Mar 26 02:56:53 PM PDT 24 |
160791785 ps |
| T984 |
/workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.634183363 |
|
|
Mar 26 02:56:53 PM PDT 24 |
Mar 26 02:56:54 PM PDT 24 |
93899853 ps |
| T985 |
/workspace/coverage/default/49.pwrmgr_lowpower_invalid.3639991260 |
|
|
Mar 26 02:57:15 PM PDT 24 |
Mar 26 02:57:16 PM PDT 24 |
43965069 ps |
| T986 |
/workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1758057335 |
|
|
Mar 26 02:56:38 PM PDT 24 |
Mar 26 02:56:41 PM PDT 24 |
822163928 ps |
| T987 |
/workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3719994374 |
|
|
Mar 26 02:56:49 PM PDT 24 |
Mar 26 02:56:51 PM PDT 24 |
1562919676 ps |
| T988 |
/workspace/coverage/default/7.pwrmgr_stress_all.3966487468 |
|
|
Mar 26 02:55:22 PM PDT 24 |
Mar 26 02:55:25 PM PDT 24 |
786864823 ps |
| T86 |
/workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.3194580310 |
|
|
Mar 26 02:56:35 PM PDT 24 |
Mar 26 02:56:57 PM PDT 24 |
18114021151 ps |
| T989 |
/workspace/coverage/default/15.pwrmgr_wakeup.1592387622 |
|
|
Mar 26 02:55:47 PM PDT 24 |
Mar 26 02:55:48 PM PDT 24 |
124446540 ps |
| T68 |
/workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.4258243523 |
|
|
Mar 26 02:55:33 PM PDT 24 |
Mar 26 02:55:59 PM PDT 24 |
6765112227 ps |
| T990 |
/workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1742856765 |
|
|
Mar 26 02:55:43 PM PDT 24 |
Mar 26 02:55:45 PM PDT 24 |
952422348 ps |
| T991 |
/workspace/coverage/default/12.pwrmgr_glitch.742194124 |
|
|
Mar 26 02:55:40 PM PDT 24 |
Mar 26 02:55:41 PM PDT 24 |
134068224 ps |
| T180 |
/workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1422210153 |
|
|
Mar 26 02:55:39 PM PDT 24 |
Mar 26 02:55:40 PM PDT 24 |
85549554 ps |
| T992 |
/workspace/coverage/default/33.pwrmgr_global_esc.3925608616 |
|
|
Mar 26 02:56:38 PM PDT 24 |
Mar 26 02:56:38 PM PDT 24 |
28932378 ps |
| T993 |
/workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3439879870 |
|
|
Mar 26 02:54:58 PM PDT 24 |
Mar 26 02:55:11 PM PDT 24 |
824002574 ps |
| T994 |
/workspace/coverage/default/25.pwrmgr_reset_invalid.3585799884 |
|
|
Mar 26 02:56:22 PM PDT 24 |
Mar 26 02:56:23 PM PDT 24 |
88551704 ps |
| T995 |
/workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.629783283 |
|
|
Mar 26 02:54:53 PM PDT 24 |
Mar 26 02:54:53 PM PDT 24 |
132923722 ps |
| T996 |
/workspace/coverage/default/48.pwrmgr_glitch.2611207566 |
|
|
Mar 26 02:57:25 PM PDT 24 |
Mar 26 02:57:26 PM PDT 24 |
41768850 ps |
| T997 |
/workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.4246524063 |
|
|
Mar 26 02:55:47 PM PDT 24 |
Mar 26 02:55:49 PM PDT 24 |
283735226 ps |
| T998 |
/workspace/coverage/default/18.pwrmgr_reset_invalid.3956637220 |
|
|
Mar 26 02:55:50 PM PDT 24 |
Mar 26 02:55:51 PM PDT 24 |
113383234 ps |
| T999 |
/workspace/coverage/default/1.pwrmgr_stress_all.2585079649 |
|
|
Mar 26 02:54:57 PM PDT 24 |
Mar 26 02:55:04 PM PDT 24 |
1971973106 ps |
| T155 |
/workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.272859583 |
|
|
Mar 26 02:57:08 PM PDT 24 |
Mar 26 02:57:35 PM PDT 24 |
7242657881 ps |
| T1000 |
/workspace/coverage/default/37.pwrmgr_reset_invalid.4139659161 |
|
|
Mar 26 02:56:49 PM PDT 24 |
Mar 26 02:56:50 PM PDT 24 |
126292756 ps |
| T53 |
/workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.690071970 |
|
|
Mar 26 02:38:44 PM PDT 24 |
Mar 26 02:38:45 PM PDT 24 |
99367662 ps |
| T43 |
/workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1910659580 |
|
|
Mar 26 02:38:50 PM PDT 24 |
Mar 26 02:38:52 PM PDT 24 |
540773297 ps |
| T54 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.795022052 |
|
|
Mar 26 02:38:46 PM PDT 24 |
Mar 26 02:38:47 PM PDT 24 |
161982099 ps |
| T59 |
/workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1162546226 |
|
|
Mar 26 02:38:45 PM PDT 24 |
Mar 26 02:38:46 PM PDT 24 |
22382755 ps |
| T112 |
/workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.754280859 |
|
|
Mar 26 02:39:07 PM PDT 24 |
Mar 26 02:39:08 PM PDT 24 |
104771715 ps |
| T44 |
/workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.575586009 |
|
|
Mar 26 02:38:54 PM PDT 24 |
Mar 26 02:38:55 PM PDT 24 |
96901611 ps |
| T174 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1163283287 |
|
|
Mar 26 02:39:00 PM PDT 24 |
Mar 26 02:39:01 PM PDT 24 |
33402205 ps |
| T175 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1881251972 |
|
|
Mar 26 02:38:34 PM PDT 24 |
Mar 26 02:38:37 PM PDT 24 |
518886959 ps |
| T173 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3015948647 |
|
|
Mar 26 02:38:56 PM PDT 24 |
Mar 26 02:38:59 PM PDT 24 |
77233111 ps |
| T85 |
/workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.762584721 |
|
|
Mar 26 02:38:58 PM PDT 24 |
Mar 26 02:38:59 PM PDT 24 |
61398127 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1801841644 |
|
|
Mar 26 02:38:45 PM PDT 24 |
Mar 26 02:38:47 PM PDT 24 |
166511271 ps |
| T48 |
/workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.772874672 |
|
|
Mar 26 02:38:59 PM PDT 24 |
Mar 26 02:39:00 PM PDT 24 |
24807213 ps |
| T165 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1635518184 |
|
|
Mar 26 02:38:42 PM PDT 24 |
Mar 26 02:38:43 PM PDT 24 |
63516085 ps |
| T56 |
/workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1626982785 |
|
|
Mar 26 02:39:13 PM PDT 24 |
Mar 26 02:39:15 PM PDT 24 |
48463637 ps |
| T49 |
/workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1554385637 |
|
|
Mar 26 02:38:45 PM PDT 24 |
Mar 26 02:38:46 PM PDT 24 |
189577108 ps |
| T60 |
/workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2142086382 |
|
|
Mar 26 02:39:07 PM PDT 24 |
Mar 26 02:39:08 PM PDT 24 |
29209328 ps |
| T57 |
/workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.974416234 |
|
|
Mar 26 02:38:54 PM PDT 24 |
Mar 26 02:38:57 PM PDT 24 |
411819170 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.796139513 |
|
|
Mar 26 02:38:43 PM PDT 24 |
Mar 26 02:38:45 PM PDT 24 |
64931999 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.752050883 |
|
|
Mar 26 02:39:27 PM PDT 24 |
Mar 26 02:39:27 PM PDT 24 |
39424983 ps |
| T64 |
/workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1251360219 |
|
|
Mar 26 02:39:09 PM PDT 24 |
Mar 26 02:39:11 PM PDT 24 |
30046692 ps |
| T113 |
/workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.3022342654 |
|
|
Mar 26 02:39:07 PM PDT 24 |
Mar 26 02:39:08 PM PDT 24 |
97229253 ps |
| T94 |
/workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1388742956 |
|
|
Mar 26 02:39:09 PM PDT 24 |
Mar 26 02:39:10 PM PDT 24 |
96506258 ps |
| T114 |
/workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3723711422 |
|
|
Mar 26 02:38:58 PM PDT 24 |
Mar 26 02:38:59 PM PDT 24 |
48904074 ps |
| T66 |
/workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2955291404 |
|
|
Mar 26 02:39:08 PM PDT 24 |
Mar 26 02:39:09 PM PDT 24 |
95791200 ps |
| T67 |
/workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.248526582 |
|
|
Mar 26 02:39:08 PM PDT 24 |
Mar 26 02:39:09 PM PDT 24 |
160607629 ps |
| T95 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3408726396 |
|
|
Mar 26 02:38:44 PM PDT 24 |
Mar 26 02:38:45 PM PDT 24 |
57591129 ps |
| T166 |
/workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1030295405 |
|
|
Mar 26 02:38:58 PM PDT 24 |
Mar 26 02:38:59 PM PDT 24 |
149855157 ps |
| T61 |
/workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1876027517 |
|
|
Mar 26 02:39:26 PM PDT 24 |
Mar 26 02:39:26 PM PDT 24 |
19771704 ps |
| T96 |
/workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1613675574 |
|
|
Mar 26 02:39:00 PM PDT 24 |
Mar 26 02:39:01 PM PDT 24 |
21950057 ps |
| T62 |
/workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2406520880 |
|
|
Mar 26 02:38:58 PM PDT 24 |
Mar 26 02:38:59 PM PDT 24 |
100422753 ps |
| T169 |
/workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.4139545773 |
|
|
Mar 26 02:39:24 PM PDT 24 |
Mar 26 02:39:25 PM PDT 24 |
28750264 ps |
| T1002 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2139236811 |
|
|
Mar 26 02:38:43 PM PDT 24 |
Mar 26 02:38:44 PM PDT 24 |
56950106 ps |
| T172 |
/workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.1713246414 |
|
|
Mar 26 02:39:25 PM PDT 24 |
Mar 26 02:39:26 PM PDT 24 |
19470042 ps |
| T58 |
/workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.235899328 |
|
|
Mar 26 02:39:09 PM PDT 24 |
Mar 26 02:39:11 PM PDT 24 |
139069122 ps |
| T1003 |
/workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1547556696 |
|
|
Mar 26 02:39:28 PM PDT 24 |
Mar 26 02:39:29 PM PDT 24 |
18758061 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.383715774 |
|
|
Mar 26 02:38:43 PM PDT 24 |
Mar 26 02:38:46 PM PDT 24 |
299490495 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.4202087143 |
|
|
Mar 26 02:38:43 PM PDT 24 |
Mar 26 02:38:44 PM PDT 24 |
112961674 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3412837225 |
|
|
Mar 26 02:38:43 PM PDT 24 |
Mar 26 02:38:44 PM PDT 24 |
20263901 ps |
| T1006 |
/workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3494902185 |
|
|
Mar 26 02:38:58 PM PDT 24 |
Mar 26 02:38:59 PM PDT 24 |
33205255 ps |
| T170 |
/workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2771090095 |
|
|
Mar 26 02:39:27 PM PDT 24 |
Mar 26 02:39:27 PM PDT 24 |
18277299 ps |
| T1007 |
/workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1753079688 |
|
|
Mar 26 02:39:10 PM PDT 24 |
Mar 26 02:39:11 PM PDT 24 |
72716324 ps |
| T1008 |
/workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1939920901 |
|
|
Mar 26 02:39:27 PM PDT 24 |
Mar 26 02:39:28 PM PDT 24 |
91860127 ps |
| T1009 |
/workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2239843664 |
|
|
Mar 26 02:38:34 PM PDT 24 |
Mar 26 02:38:37 PM PDT 24 |
42824585 ps |
| T97 |
/workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2982991000 |
|
|
Mar 26 02:39:06 PM PDT 24 |
Mar 26 02:39:07 PM PDT 24 |
58866116 ps |
| T63 |
/workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1606685747 |
|
|
Mar 26 02:38:33 PM PDT 24 |
Mar 26 02:38:36 PM PDT 24 |
114211444 ps |
| T171 |
/workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.3837879572 |
|
|
Mar 26 02:38:55 PM PDT 24 |
Mar 26 02:38:56 PM PDT 24 |
52076639 ps |
| T1010 |
/workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.206497478 |
|
|
Mar 26 02:39:01 PM PDT 24 |
Mar 26 02:39:02 PM PDT 24 |
230896703 ps |
| T1011 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3305452779 |
|
|
Mar 26 02:38:45 PM PDT 24 |
Mar 26 02:38:46 PM PDT 24 |
44353695 ps |
| T1012 |
/workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2623097572 |
|
|
Mar 26 02:38:59 PM PDT 24 |
Mar 26 02:38:59 PM PDT 24 |
26598332 ps |
| T1013 |
/workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2935000832 |
|
|
Mar 26 02:39:10 PM PDT 24 |
Mar 26 02:39:11 PM PDT 24 |
248331361 ps |
| T168 |
/workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3693621769 |
|
|
Mar 26 02:39:14 PM PDT 24 |
Mar 26 02:39:16 PM PDT 24 |
137703594 ps |
| T1014 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3589984334 |
|
|
Mar 26 02:38:43 PM PDT 24 |
Mar 26 02:38:44 PM PDT 24 |
49984930 ps |
| T1015 |
/workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1390228485 |
|
|
Mar 26 02:38:56 PM PDT 24 |
Mar 26 02:38:58 PM PDT 24 |
92207763 ps |
| T1016 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3377131277 |
|
|
Mar 26 02:38:55 PM PDT 24 |
Mar 26 02:38:57 PM PDT 24 |
370647195 ps |