Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	499504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

192852

1

T1

9

T2

129

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	361338	1			T1	16		T2	265		T3	21
values[0x0]	164886	1			T1	2		T2	121		T4	44
values[0x1]	166132	1			T1	6		T2	115		T4	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	395400	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

296956

1

T1

10

T2

192

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3403	1			T8	45		T9	3		T13	42
valid_sources[0x01]	2322	1			T8	44		T9	10		T13	22
valid_sources[0x02]	2977	1			T1	1		T8	58		T9	11
valid_sources[0x03]	2250	1			T8	48		T9	7		T13	36
valid_sources[0x04]	2636	1			T1	1		T8	44		T9	3
valid_sources[0x05]	2436	1			T8	37		T9	7		T18	6
valid_sources[0x06]	6535	1			T1	1		T2	9		T8	38
valid_sources[0x07]	2886	1			T8	47		T9	8		T13	24
valid_sources[0x08]	2197	1			T2	1		T8	31		T9	2
valid_sources[0x09]	2238	1			T8	47		T9	8		T13	32
valid_sources[0x0a]	2121	1			T8	28		T9	4		T13	19
valid_sources[0x0b]	2474	1			T8	45		T9	7		T13	39
valid_sources[0x0c]	2681	1			T2	8		T8	48		T9	12
valid_sources[0x0d]	2355	1			T8	43		T9	8		T13	23
valid_sources[0x0e]	3644	1			T2	6		T8	40		T9	14
valid_sources[0x0f]	6453	1			T8	32		T9	6		T13	32
valid_sources[0x10]	2436	1			T8	40		T9	5		T13	35
valid_sources[0x11]	2630	1			T8	44		T9	9		T13	32
valid_sources[0x12]	2312	1			T2	5		T8	38		T9	10
valid_sources[0x13]	2588	1			T8	39		T9	6		T13	31
valid_sources[0x14]	2285	1			T8	26		T9	6		T13	45
valid_sources[0x15]	2227	1			T8	41		T9	9		T13	32
valid_sources[0x16]	2587	1			T8	45		T9	11		T13	36
valid_sources[0x17]	4168	1			T8	46		T9	4		T13	22
valid_sources[0x18]	2225	1			T8	40		T9	6		T13	35
valid_sources[0x19]	2398	1			T8	38		T9	5		T13	35
valid_sources[0x1a]	5335	1			T2	15		T8	51		T9	4
valid_sources[0x1b]	2835	1			T2	1		T8	47		T9	9
valid_sources[0x1c]	4641	1			T2	1		T8	37		T9	7
valid_sources[0x1d]	2195	1			T1	1		T8	45		T9	6
valid_sources[0x1e]	2466	1			T2	35		T8	47		T9	5
valid_sources[0x1f]	2409	1			T8	34		T9	8		T13	25
valid_sources[0x20]	2142	1			T2	16		T8	36		T9	4
valid_sources[0x21]	2422	1			T8	58		T9	6		T13	30
valid_sources[0x22]	2730	1			T8	59		T9	6		T25	1
valid_sources[0x23]	2336	1			T8	55		T9	7		T13	30
valid_sources[0x24]	2211	1			T1	1		T8	42		T9	5
valid_sources[0x25]	3447	1			T8	41		T9	9		T18	12
valid_sources[0x26]	2071	1			T8	44		T9	9		T13	28
valid_sources[0x27]	2372	1			T8	25		T9	6		T13	31
valid_sources[0x28]	2236	1			T8	41		T9	6		T13	28
valid_sources[0x29]	2285	1			T8	41		T9	2		T13	29
valid_sources[0x2a]	2493	1			T8	45		T9	7		T13	27
valid_sources[0x2b]	2601	1			T8	45		T9	11		T13	27
valid_sources[0x2c]	2684	1			T8	48		T9	6		T13	32
valid_sources[0x2d]	2219	1			T8	34		T9	10		T13	34
valid_sources[0x2e]	3148	1			T2	17		T8	32		T9	5
valid_sources[0x2f]	2325	1			T8	39		T9	2		T13	27
valid_sources[0x30]	3677	1			T8	57		T9	8		T13	37
valid_sources[0x31]	2279	1			T8	43		T9	11		T13	26
valid_sources[0x32]	2243	1			T8	45		T9	7		T18	3
valid_sources[0x33]	2347	1			T8	51		T9	2		T13	31
valid_sources[0x34]	2391	1			T8	51		T9	6		T13	30
valid_sources[0x35]	2365	1			T8	37		T9	8		T13	37
valid_sources[0x36]	2427	1			T8	39		T9	14		T13	29
valid_sources[0x37]	2399	1			T8	42		T9	7		T10	1
valid_sources[0x38]	2310	1			T8	47		T9	6		T13	25
valid_sources[0x39]	2462	1			T2	2		T8	53		T9	7
valid_sources[0x3a]	2449	1			T8	54		T9	8		T13	20
valid_sources[0x3b]	2493	1			T8	48		T9	8		T18	6
valid_sources[0x3c]	2395	1			T8	38		T9	8		T13	35
valid_sources[0x3d]	2244	1			T8	37		T9	6		T13	30
valid_sources[0x3e]	2149	1			T8	30		T9	10		T13	29
valid_sources[0x3f]	2467	1			T8	54		T9	5		T13	34
valid_sources[0x40]	2581	1			T8	37		T9	8		T18	13
valid_sources[0x41]	3166	1			T1	1		T8	32		T9	9
valid_sources[0x42]	2040	1			T2	22		T8	39		T9	8
valid_sources[0x43]	2435	1			T8	41		T9	9		T13	28
valid_sources[0x44]	2265	1			T2	19		T8	41		T9	5
valid_sources[0x45]	3164	1			T8	33		T9	9		T13	28
valid_sources[0x46]	2213	1			T8	50		T9	9		T13	31
valid_sources[0x47]	2355	1			T7	1		T8	47		T9	6
valid_sources[0x48]	2282	1			T8	44		T9	9		T13	28
valid_sources[0x49]	3667	1			T2	5		T8	40		T9	6
valid_sources[0x4a]	3438	1			T8	48		T9	7		T13	24
valid_sources[0x4b]	3025	1			T8	36		T9	4		T25	2
valid_sources[0x4c]	2200	1			T2	14		T8	43		T9	11
valid_sources[0x4d]	2157	1			T8	39		T9	4		T13	29
valid_sources[0x4e]	3640	1			T8	50		T9	6		T13	43
valid_sources[0x4f]	2379	1			T8	37		T9	5		T13	33
valid_sources[0x50]	3595	1			T1	1		T2	22		T8	38
valid_sources[0x51]	2379	1			T8	37		T9	5		T25	1
valid_sources[0x52]	3502	1			T8	38		T9	3		T25	1
valid_sources[0x53]	3704	1			T8	56		T9	6		T14	1
valid_sources[0x54]	2433	1			T2	6		T4	170		T8	28
valid_sources[0x55]	2388	1			T8	39		T9	2		T13	41
valid_sources[0x56]	2363	1			T8	40		T9	5		T13	27
valid_sources[0x57]	2302	1			T1	1		T8	27		T9	9
valid_sources[0x58]	2326	1			T8	35		T9	12		T13	32
valid_sources[0x59]	2283	1			T2	14		T8	48		T9	6
valid_sources[0x5a]	2678	1			T8	31		T9	7		T13	25
valid_sources[0x5b]	2382	1			T8	37		T9	7		T13	39
valid_sources[0x5c]	2384	1			T8	43		T9	4		T13	41
valid_sources[0x5d]	2782	1			T2	11		T8	38		T9	8
valid_sources[0x5e]	2485	1			T8	48		T9	6		T25	1
valid_sources[0x5f]	2793	1			T2	1		T8	49		T9	7
valid_sources[0x60]	2439	1			T2	3		T3	21		T8	41
valid_sources[0x61]	2276	1			T2	5		T8	47		T9	11
valid_sources[0x62]	3732	1			T8	41		T9	8		T13	37
valid_sources[0x63]	2502	1			T2	3		T8	38		T9	4
valid_sources[0x64]	2257	1			T8	46		T9	4		T13	23
valid_sources[0x65]	2467	1			T8	29		T9	5		T13	38
valid_sources[0x66]	2485	1			T8	43		T9	5		T13	37
valid_sources[0x67]	2516	1			T8	50		T9	3		T13	29
valid_sources[0x68]	2262	1			T2	13		T8	53		T9	6
valid_sources[0x69]	2561	1			T8	48		T9	6		T13	26
valid_sources[0x6a]	2204	1			T8	58		T9	3		T25	1
valid_sources[0x6b]	2396	1			T8	43		T9	10		T13	36
valid_sources[0x6c]	3268	1			T8	40		T9	2		T18	2
valid_sources[0x6d]	2395	1			T8	36		T9	4		T13	31
valid_sources[0x6e]	2201	1			T1	1		T8	40		T9	7
valid_sources[0x6f]	2293	1			T8	38		T9	6		T25	1
valid_sources[0x70]	3599	1			T8	45		T9	6		T25	1
valid_sources[0x71]	2384	1			T2	7		T8	49		T9	11
valid_sources[0x72]	2970	1			T8	31		T9	7		T13	24
valid_sources[0x73]	2871	1			T2	36		T8	60		T9	4
valid_sources[0x74]	2585	1			T8	55		T9	4		T13	36
valid_sources[0x75]	4468	1			T8	45		T9	6		T13	33
valid_sources[0x76]	2520	1			T8	35		T9	7		T13	29
valid_sources[0x77]	2418	1			T6	244		T8	35		T9	7
valid_sources[0x78]	2423	1			T8	38		T9	7		T13	27
valid_sources[0x79]	2530	1			T8	32		T9	8		T13	36
valid_sources[0x7a]	2186	1			T8	38		T9	5		T13	29
valid_sources[0x7b]	2391	1			T8	33		T9	6		T13	31
valid_sources[0x7c]	2117	1			T8	45		T9	4		T13	23
valid_sources[0x7d]	2204	1			T8	53		T9	6		T13	29
valid_sources[0x7e]	2347	1			T8	47		T9	10		T13	27
valid_sources[0x7f]	2343	1			T1	1		T2	2		T8	50
valid_sources[0x80]	2251	1			T1	2		T8	45		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97402

1

T1

5

T2

76

T3

1

values[0x0]

all_enables

biggest_size

61507

1

T1

2

T2

36

T4

11

values[0x1]

all_enables

biggest_size

33943

1

T1

2

T2

17

T4

9