SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35120 | 1 | T27 | 370 | T29 | 402 | T30 | 393 | ||||
others[1] | 35007 | 1 | T27 | 437 | T29 | 405 | T30 | 387 | ||||
others[2] | 34877 | 1 | T27 | 408 | T29 | 372 | T30 | 403 | ||||
others[3] | 58549 | 1 | T27 | 658 | T29 | 692 | T30 | 696 | ||||
false | 18843 | 1 | T8 | 314 | T9 | 22 | T13 | 216 | ||||
true | 28770 | 1 | T1 | 1 | T2 | 5 | T3 | 81 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34830 | 1 | T27 | 419 | T29 | 399 | T20 | 1 | ||||
others[1] | 35212 | 1 | T27 | 416 | T29 | 397 | T20 | 2 | ||||
others[2] | 35452 | 1 | T27 | 385 | T29 | 419 | T30 | 372 | ||||
others[3] | 58042 | 1 | T27 | 672 | T29 | 664 | T30 | 668 | ||||
false | 12024 | 1 | T8 | 157 | T9 | 11 | T13 | 108 | ||||
true | 22028 | 1 | T1 | 1 | T2 | 5 | T3 | 81 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 706 | 1 | T8 | 7 | T9 | 1 | T13 | 6 | ||||
others[1] | 649 | 1 | T6 | 7 | T8 | 4 | T9 | 2 | ||||
others[2] | 692 | 1 | T6 | 10 | T8 | 7 | T9 | 2 | ||||
others[3] | 1116 | 1 | T6 | 8 | T8 | 14 | T13 | 20 | ||||
false | 13386 | 1 | T1 | 1 | T2 | 5 | T3 | 81 | ||||
true | 3930 | 1 | T8 | 66 | T9 | 18 | T18 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |