Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T25,T13

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24620852	6121	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24620852	258993	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24620852	10088661	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24620852	258978	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24620852	6121	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24620852	258993	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24620852	10088661	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24620852	258978	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	6121	0	0
T2	33134	2	0	0
T3	44536	0	0	0
T4	4407	0	0	0
T5	1152	1	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	92	0	0
T9	42879	5	0	0
T10	3725	0	0	0
T13	0	61	0	0
T14	3953	0	0	0
T25	0	2	0	0
T27	0	17	0	0
T28	0	18	0	0
T29	0	19	0	0
T30	0	21	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	258993	0	0
T2	33134	24	0	0
T3	44536	0	0	0
T4	4407	0	0	0
T5	1152	14	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	6320	0	0
T9	42879	285	0	0
T10	3725	0	0	0
T13	0	1921	0	0
T14	3953	0	0	0
T25	0	170	0	0
T27	0	467	0	0
T28	0	407	0	0
T29	0	477	0	0
T30	0	1658	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	10088661	0	0
T1	2496	1571	0	0
T2	33134	18778	0	0
T3	44536	0	0	0
T4	4407	1919	0	0
T5	1152	858	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	277998	0	0
T9	42879	12721	0	0
T10	3725	0	0	0
T13	0	126907	0	0
T25	0	149	0	0
T27	0	10388	0	0
T28	0	17018	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	258978	0	0
T2	33134	24	0	0
T3	44536	0	0	0
T4	4407	0	0	0
T5	1152	14	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	6320	0	0
T9	42879	285	0	0
T10	3725	0	0	0
T13	0	1921	0	0
T14	3953	0	0	0
T25	0	170	0	0
T27	0	467	0	0
T28	0	407	0	0
T29	0	477	0	0
T30	0	1658	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	6121	0	0
T2	33134	2	0	0
T3	44536	0	0	0
T4	4407	0	0	0
T5	1152	1	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	92	0	0
T9	42879	5	0	0
T10	3725	0	0	0
T13	0	61	0	0
T14	3953	0	0	0
T25	0	2	0	0
T27	0	17	0	0
T28	0	18	0	0
T29	0	19	0	0
T30	0	21	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	258993	0	0
T2	33134	24	0	0
T3	44536	0	0	0
T4	4407	0	0	0
T5	1152	14	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	6320	0	0
T9	42879	285	0	0
T10	3725	0	0	0
T13	0	1921	0	0
T14	3953	0	0	0
T25	0	170	0	0
T27	0	467	0	0
T28	0	407	0	0
T29	0	477	0	0
T30	0	1658	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	10088661	0	0
T1	2496	1571	0	0
T2	33134	18778	0	0
T3	44536	0	0	0
T4	4407	1919	0	0
T5	1152	858	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	277998	0	0
T9	42879	12721	0	0
T10	3725	0	0	0
T13	0	126907	0	0
T25	0	149	0	0
T27	0	10388	0	0
T28	0	17018	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	258978	0	0
T2	33134	24	0	0
T3	44536	0	0	0
T4	4407	0	0	0
T5	1152	14	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	6320	0	0
T9	42879	285	0	0
T10	3725	0	0	0
T13	0	1921	0	0
T14	3953	0	0	0
T25	0	170	0	0
T27	0	467	0	0
T28	0	407	0	0
T29	0	477	0	0
T30	0	1658	0	0