Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25161225	14413	0	0
intr_enable_rd_A	25161225	46369	0	0
reset_en_rd_A	25161225	925	0	0
reset_en_regwen_rd_A	25161225	782	0	0
wake_info_capture_dis_rd_A	25161225	880	0	0
wakeup_en_rd_A	25161225	1546	0	0
wakeup_en_regwen_rd_A	25161225	854	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25161225	14413	0	0
T8	659418	19	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T13	297410	14	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T19	0	6	0	0
T25	1384	0	0	0
T26	2766	0	0	0
T27	24368	0	0	0
T28	32462	0	0	0
T39	0	30	0	0
T110	0	4	0	0
T111	0	1	0	0
T112	0	110	0	0
T113	0	13	0	0
T114	0	2	0	0
T115	0	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25161225	46369	0	0
T4	4407	30	0	0
T5	1152	0	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	2752	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T25	1384	0	0	0
T27	0	101	0	0
T30	0	208	0	0
T45	0	8	0	0
T77	0	2	0	0
T116	0	62	0	0
T117	0	54	0	0
T118	0	12	0	0
T119	0	15	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25161225	925	0	0
T8	659418	15	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T13	297410	0	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T25	1384	0	0	0
T26	2766	0	0	0
T27	24368	0	0	0
T28	32462	0	0	0
T37	0	71	0	0
T38	0	49	0	0
T42	0	6	0	0
T66	0	7	0	0
T110	0	7	0	0
T111	0	11	0	0
T120	0	14	0	0
T121	0	1	0	0
T122	0	3	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25161225	782	0	0
T8	659418	14	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T13	297410	0	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T25	1384	0	0	0
T26	2766	0	0	0
T27	24368	0	0	0
T28	32462	0	0	0
T37	0	35	0	0
T57	0	3	0	0
T66	0	8	0	0
T110	0	15	0	0
T111	0	1	0	0
T120	0	8	0	0
T121	0	9	0	0
T122	0	6	0	0
T123	0	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25161225	880	0	0
T8	659418	13	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T13	297410	0	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T25	1384	0	0	0
T26	2766	0	0	0
T27	24368	0	0	0
T28	32462	0	0	0
T37	0	40	0	0
T39	0	6	0	0
T110	0	8	0	0
T111	0	8	0	0
T120	0	5	0	0
T121	0	7	0	0
T122	0	8	0	0
T124	0	8	0	0
T125	0	4	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25161225	1546	0	0
T8	659418	11	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T13	297410	0	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T25	1384	0	0	0
T26	2766	0	0	0
T27	24368	0	0	0
T28	32462	0	0	0
T37	0	154	0	0
T38	0	161	0	0
T42	0	2	0	0
T57	0	5	0	0
T110	0	7	0	0
T111	0	7	0	0
T121	0	6	0	0
T122	0	7	0	0
T124	0	10	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25161225	854	0	0
T8	659418	7	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T13	297410	0	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T25	1384	0	0	0
T26	2766	0	0	0
T27	24368	0	0	0
T28	32462	0	0	0
T37	0	41	0	0
T57	0	6	0	0
T66	0	8	0	0
T110	0	7	0	0
T111	0	11	0	0
T120	0	1	0	0
T121	0	4	0	0
T122	0	1	0	0
T123	0	1	0	0